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On Oct 12, 11:18=A0am, "gkonstan" <paraharak...@gmail.com> wrote: > hello everyone > > I have a problem: After downloading a mcs file to a xc18v02 PROM used for= a > XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now I > count only 2V instead of 2.5 or 3.3 V in the power supply. I am supposed = to > see what is going wrong, in order to change what has been broken. I have = no > idea what I should do. Any ideas? =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com try change mode pins to prevent fpga configuration maybe it still boots in unconfigured mode AnttiArticle: 143451
Antti.Lukats@googlemail.com wrote: > On Oct 12, 10:14 am, David Brown <da...@westcontrol.removethisbit.com> > wrote: >> rickman wrote: <snip> >>> However, clock speed is not the >>> determining factor of processor speed, as we all know. Most FPGA CPUs >>> are rather simple CPUs with simple instruction sets and get lower MIPS >>> per MHz. The real advantage of a soft CPU is the flexibility you have >>> to integrate it with peripherals or possibly the fact that you can >>> eliminate cost by not having a separate CPU. In other cases you can >>> connect multiple CPUs with high speed interfaces. It all comes down >>> to the cost and the flexibility, whichever is important to you. >> That part is all true. >> >> The general rule is that you get more bang for the buck (and for the >> power) with a hardware CPU - /if/ it does the job you need. Soft CPUs >> are for flexibility and convenience (if you've got a big FPGA already, >> the soft CPU is free).- Hide quoted text - >> >> - Show quoted text - > > David, > > yes/no as usual, right at the higher end, you defenetly get more > processor power in dedicated microcontroller than in FPGA > (despite Xilinx once tried to explain that Virtex4 outperforms Pentium > class processor both on performance AND price) > Of course, that depends on the application. > however the border is moving all the time, smallest and chepest FPGA > (that i still call FPGA) is A3P060, costs about 3.5$ > medium qty, it is just almost too small for soft core, but depending > the requirements it may still be possible to actually > have an small RISC core inside, the price of the RISC would be rather > high (in terms of utilization) say close to 2.5$ > but it would outperform the "real risc" it emulates on the clock > speed, so you get an superspeed AVR for 2.5$ > thats not that bad :) > besides my super speed AVR directly boots from sd card into RAM (ok > only 512 instruction so its tiny!) > Yes, but when you include everything else (flash for storing the FPGA image and cpu software, power supplies, higher cost PCB, clock sources, amortized development costs, etc.) you'll find the AVR much cheaper than a soft core in the FPGA if it will do the job you need. If you need the FPGA anyway, the numbers are different, of course. But it is probably always a mistake (economically) to use an FPGA just for the soft cpu. > in smallest Altera you can have soft cores wich cost in terms of % of > resources maybe around < 0.25$ what is BELOW > the price you can buy flash mcu's (OTP/ROM mcu can go below 0.2$) > Once you have an FPGA on the board, a soft core is almost free. > the price of 32 bit MCU capable of running uClinux made with FPGA (% > FPGA + ext ram) is around 5..10$ at the moment > (total price a bit higher as most of the FPGA is empty) > For higher power /general/ processing, microcontrollers/microprocessors definitely have the edge in mips per $ (and greatly outclass FPGAs in mips per mW). FPGA soft cpus win when you can make use of their features, such as with custom instructions, integration with the rest of the FPGA, etc., or when you simply have the FPGA space available giving you zero cost for the cpu core. > so in some cases the MCU-proc solutions are closing up the flash-mcu > solutions. > Both options are getting cheaper and more powerful - it's good to have the choice.Article: 143452
hello everyone I have a problem: After downloading a mcs file to a xc18v02 PROM used for a XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now I count only 2V instead of 2.5 or 3.3 V in the power supply. I am supposed to see what is going wrong, in order to change what has been broken. I have no idea what I should do. Any ideas? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143453
On Oct 11, 2:41=A0pm, "max" <ch...@e-chaos.com> wrote:
> Hi,
>
> I'm using the ML403 board for the interrupt-based system. In this system,
> floating point operations in interrupt handler are required and APU is
> employed to accelerate the single precision floating point operation. The
> software is running with the standalone BSP on the PPC.
> ...
> It seems that PPC is blocked when timer interrupt handler
> =93TimerCounterHandler=94 is executed. Any advice on how to resolve the
> problem.
When the PowerPC enters an interrupt handler, the MSR is altered in a
number of ways. One of those ways is that MSR[FP] is set to zero. This
means that, by default, you cannot use floating-point instructions
within an interrupt handler. To do so, you would have to re-enable the
FPU by writing a 1 to MSR[FP] at the start of your ISR.
If in your C code you #include "xpseudo_asm.h" from the PowerPC405
driver, then you should be able to write something like
mtmsr(mfmsr() | XREG_MSR_FLOATING_POINT_AVAILABLE);
There is another MSR bit defined by Xilinx which you might have to
modify, which is bit 6 (XREG_MSR_APU_AVAILABLE). I can't remember
offhand whether this bit gets cleared when inside an ISR, but it won't
hurt to set it anyway.
Have fun!
-Ben-
Article: 143454Nico Coesel wrote: > Joseph Yiu <joseph.yiu@somewhereinarm.com> wrote: > >> rickman wrote: >> >>> As others have indicated, it may be easy to implement CPUs in FPGAs, >>> but they do not run nearly as fast as high end CPUs in fixed silicon. >>> Martin indicated that if your algorithm is amenable to breaking it >>> into many processes running in parallel, many processors can be used, >>> each doing a part of the calculation with the load fairly balanced. >>> >> Regarding speed, actually you could have better performance by running a >> CPU in FPGA compared to standard microcontrollers. Flash memory usually >> have a flash memory of 25MHz to 50MHz, while block RAM in FPGA can be >> much faster. So you can run a processor at high clock speed on FPGA >> (e.g. 100MHz) with zero wait state, compared to microcontroller products >> running at 100MHz with 1 or 2 wait states on silicon. > > That's not true. Most of such microcontrollers have wider flash and > use pre-fetch and branch prediction buffers (a small smart cache) to > undo the effects of the slower flash. NXP has been doing this for > years with the LPC2000 series and has included similar schemes on > their new LPC1300 en LPC1700 series. > I wrote "you could have" :-) You're right that NXP has done really very on their wide flash in LPC product series. But many others are not doing as well. Even so, you can have a higher branch penalty in MCU with flash prefetch. So if you take the LPC1700 and run the Dhrystone benchmark at 100MHz, it is a bit lower than the ideal 1.25 DMIPS/MHz.Article: 143455
>On Oct 12, 11:18=A0am, "gkonstan" <paraharak...@gmail.com> wrote: >> hello everyone >> >> I have a problem: After downloading a mcs file to a xc18v02 PROM used for= > a >> XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now I >> count only 2V instead of 2.5 or 3.3 V in the power supply. I am supposed = >to >> see what is going wrong, in order to change what has been broken. I have = >no >> idea what I should do. Any ideas? =A0 =A0 =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >try change mode pins to prevent fpga configuration >maybe it still boots in unconfigured mode > >Antti > Probably my question is trivial, but I am sorry, I am realy new in the field. I checked the FPGA mode pins, and they are grounded (000 means Master serial mode). Should i try to change that, or did you mean something in the prom, which I was unable to find? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143456
On Sun, 11 Oct 2009 21:37:57 -0700 (PDT), "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote: >On Oct 12, 1:33 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> If you can't develop in Libero you can't use those FPGAs. >> But you may be able to develop in other tools, and then beg a little time on a >> machine that DOES run Libero. >> >> Or for $50-100 get another hardware platform. How much is your time worth? >> >> - Brian > >Brian, > >I have seen Libero to crash very very seldom (I have one design that >crashes actel fitter) Good to know; I have never tried it (and frankly, I don't think either of us would make the same statement about the Xilinx tools!) I was just following Jon's statement there. >hmm.. I havent upgraded to 8.6! could be 8.6 no longer works, unitl >8.5 all versions works for sure Maybe Jon should [up|down]grade to 8.5... - BrianArticle: 143457
>On Oct 11, 2:41=A0pm, "max" <ch...@e-chaos.com> wrote: >> Hi, >> >> I'm using the ML403 board for the interrupt-based system. In this system, >> floating point operations in interrupt handler are required and APU is >> employed to accelerate the single precision floating point operation. The >> software is running with the standalone BSP on the PPC. >> ... >> It seems that PPC is blocked when timer interrupt handler >> =93TimerCounterHandler=94 is executed. Any advice on how to resolve the >> problem. > >When the PowerPC enters an interrupt handler, the MSR is altered in a >number of ways. One of those ways is that MSR[FP] is set to zero. This >means that, by default, you cannot use floating-point instructions >within an interrupt handler. To do so, you would have to re-enable the >FPU by writing a 1 to MSR[FP] at the start of your ISR. > >If in your C code you #include "xpseudo_asm.h" from the PowerPC405 >driver, then you should be able to write something like > > mtmsr(mfmsr() | XREG_MSR_FLOATING_POINT_AVAILABLE); > >There is another MSR bit defined by Xilinx which you might have to >modify, which is bit 6 (XREG_MSR_APU_AVAILABLE). I can't remember >offhand whether this bit gets cleared when inside an ISR, but it won't >hurt to set it anyway. > >Have fun! > > -Ben- > Hi Ben, Thank you for your response. After adding "mtmsr(mfmsr() | XREG_MSR_FLOATING_POINT_AVAILABLE);" to the interrupt handler, it works now. Best Regards, Max --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143458
Jon Slaughter wrote: > > Also, Their is free software for the SystemC that you can "Synthesize" code. > I'm not sure how far it goes though. > > http://www.systemc.org/downloads/standards/ > > I prefer to program in C++ since I have been programming in C/C++/C# for > many years. While my simple applications do not require oop it's always nice > to have when things get more complex. > > Anyways, thanks for the help... Hi Jon, as far as I know there is limited free SystemC synthesis. There's a demo here: http://system-synthesis.org/fossy/home which will synthesize a limited amount of code to VHDL. Otherwise all the available synthesis tools are paid for (e.g. Forte Cynthesizer, SystemCrafter, CatapultC). I would suggest that even if you had access to one of these tools, you still need to understand hardware; i.e. you will to a greater or lesser extent have to write your C/C++/SystemC in a "hardware style". Support for object orientated features of C++/SystemC is limited, so in that sense you are probably better off using VHDL or Verilog, regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated.Article: 143459
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:htt5d59gfe9idqi5a2go9vfg1pmkoodu6h@4ax.com... > On Sun, 11 Oct 2009 21:37:57 -0700 (PDT), "Antti.Lukats@googlemail.com" > <antti.lukats@googlemail.com> wrote: > >>On Oct 12, 1:33 am, Brian Drummond <brian_drumm...@btconnect.com> >>wrote: > >>> If you can't develop in Libero you can't use those FPGAs. >>> But you may be able to develop in other tools, and then beg a little >>> time on a >>> machine that DOES run Libero. >>> >>> Or for $50-100 get another hardware platform. How much is your time >>> worth? >>> >>> - Brian >> >>Brian, >> >>I have seen Libero to crash very very seldom (I have one design that >>crashes actel fitter) > > Good to know; I have never tried it (and frankly, I don't think either of > us > would make the same statement about the Xilinx tools!) I was just > following > Jon's statement there. > >>hmm.. I havent upgraded to 8.6! could be 8.6 no longer works, unitl >>8.5 all versions works for sure > > Maybe Jon should [up|down]grade to 8.5... > Both have the problem. It is an issue with either the memory or the licensing manager. I installed it on my XP machine which uses a lot of flexlm licensing products and it crashes at the start. I attempted to debug the program to see what was causing it and it had something to do with it's memory manager(smartmemory IIRC). In any case it crashes which is not may fault but a problem with the program. I installed 8.5 on my vista dual boot and it worked but since I never use vista I didn't mess with it much. I went ahead and installed 8.6 hoping it would work but same problem. I then installed it on vista and now I get a licensing error(saying it's not the right license file or something). I attempted to get a new licensing file but never got it in the email and haven't bothered with it much. I guess I can always install 8.5 again on vista but I already have quartus installed and it looks better(libero looked like it hadn't been upgraded since win3.1).Article: 143460
LucienZ <lucien.zhang@gmail.com> writes: > Thanks a lot Martin and rickman! > Martin, an introduction to the stereo matching can be found in this > slides: http://www.vision.deis.unibo.it/smatt/Seminars/StereoVision.pdf > and related people are gathering here: http://vision.middlebury.edu/ > I bet you already have backgrounds in the stereo matching topics. Some, but I haven't evaluated quite as many ways of doing it as you :) > Each > of the stereo matching algorithms has its own features; however many > of them include intensive use Sum-of-Absolute-Difference (SAD) to find > out the best matches between the left and right image. <snip> > The aim is to find out the best match, and in this case it is obvious. > But in practice there are many other problems, and in our case the > pixel block and search space are NOT rectangular. Hmm, that may cause you some problems, as it implies somewhat disorganised memory accesses. > > Any recommended structures for this? I think the systolic array is a > promising solution (thanks to Glen); although by now it is not clear > to me how to do the mapping +_+. Well, the maths is just a bunch of subtract, abs() and an accumulator functions. The trick is getting the pixels from the memory efficiently. If you can store enough height of the image in internal BRAMs you can pull 2 pixels / cycle from each BRAM if you organise it right. If you have to go to an offchip framebuffer, optimising the memory access will be "interesting". > Thanks for you to mention the 'census > transform', I also bumped into the concept when looking into a > reference design (DeepSea Stereo Vision System) :). I will pay more > attention to it. It suits FPGAs well (the "single bit" part of it), and processors badly (I would imagine), so it's a bit of a weird one to benchmark... > > I did some related literature studies these days (not complete yet...) > and the most impressive solution did use a direct hardware > implementation of the SADs. One claims achieving 600 FPS at 450*375 > resolution (of course more parameters are involved). Presumably that is just "straightforward" square SADs along a scanline? > As comparison, > the same algorithm with software optimizations (trade memory for fast > calculations) can only achieve 1.48 FPS (3GHz Pentium IV). > > A practical implementation should be a streamed, pipelined approach > which interfaces cameras as well as a stereoscopic display. At the > beginning I think some external memories should be used to provide > ground truth test data. You don't need to test against ground truth in the embedded implementation - just demonstrate that as you build up your offline simulations. > > I was just thinking too 'software' and 'sequential', even if when I > talked about parallel (simply divide the work load by the number of > processors). And I overestimated the computation power of embedded > processors (I took many related courses, paper work...). Yes, stereo matching will have a large amount of really tiny parallel parts, if you decompose it that way. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 143461
gkonstan <paraharaktis@gmail.com> wrote: > hello everyone > I have a problem: After downloading a mcs file to a xc18v02 PROM used for a > XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now I > count only 2V instead of 2.5 or 3.3 V in the power supply. I am supposed to > see what is going wrong, in order to change what has been broken. I have no > idea what I should do. Any ideas? > Mostly you have a problem with nervoeous fingers: Tou posted the same messahe multiple times... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143462
On Oct 12, 5:34=A0am, "gkonstan" <paraharak...@gmail.com> wrote: > >On Oct 12, 11:18=3DA0am, "gkonstan" <paraharak...@gmail.com> wrote: > >> hello everyone > > >> I have a problem: After downloading a mcs file to a xc18v02 PROM used > for=3D > > a > >> XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now = I > >> count only 2V instead of 2.5 or 3.3 V in the power supply. I am suppos= ed > =3D > >to > >> see what is going wrong, in order to change what has been broken. I ha= ve > =3D > >no > >> idea what I should do. Any ideas? =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> This message was sent using the comp.arch.fpga web interface > onhttp://www=3D > >.FPGARelated.com > > >try change mode pins to prevent fpga configuration > >maybe it still boots in unconfigured mode > > >Antti > > Probably my question is trivial, but I am sorry, I am realy new in the > field. I checked the FPGA mode pins, and they are grounded (000 means > Master serial mode). Should i try to change that, or did you mean somethi= ng > in the prom, which I was unable to find? =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Yes. If you change the mode pins (even just one of them) the part will not perform self-configuration from the PROM. Then you can see if the power supply comes up without configuring the FPGA. Without its configuration, the FPGA should not take very much power unless it is blown. Regards, GaborArticle: 143463
Hello, I'm simulating a VHDL design after synthesis,placement & routing with the back-annotated model that ISE gives me. In order to debug it, I would like to find some internal signals. However all internal signal names have new names (different than the ones in the initial VHDL code). These new names probably have to do with the xilinx-cells to which the signals were maped. Does anyone know how I can search for the new name (post-placement name) of a signal from my initial design VHDL code? Does ISE provide a way to find this correspondence? If not how do people proceed to the debugging without access to internal signals? I have seen the post: "How to obtain original input/output signal name from SDF Timing Simulation within Modelsim? " but it's hard to believe that there is no way to find the relationship between source code and technology primitives (wherever it still exists after synthesis). Thank you in advance, GeorgeArticle: 143464
On Oct 12, 2:29=A0am, jay <heavenf...@gmail.com> wrote:
>
> I have a module named moduleA, I have a testbench moduleA_tb and
> instantiate moduleA_uut inside, and use $sdfannotate ("delay.sdf") to
> back annotate the design.
I don't know anything about SDF annotation, but I can make some
guesses.
> I use ncverilog to run timing simulation, and got below warnings:
> ncelab: *W,SDFINF: Instance moduleA not found at scope level <top-
> level> <./delay.sdf, line 283422>.
It is trying to find your moduleA at the top of the design. But in
your version of the design, it isn't at the top any more (and isn't
named moduleA). I assume that is the problem.
> The delay.sdf is gotten from ASIC team, I found the instance names in
> it are moduleA.i1.xxx etc. I think I need to change all of them to
> moduleA_uut.i1.xxx, then I don't get the SDFINF warning when rerun the
> simulation, but thousands of "ncelab: *W,SDFNEP: Unable to annotate to
> non-existent path (xxx)" warnings and "Warning! =A0Timing violation"
> during simulation.
I suspect you would have to change moduleA to moduleA_tb.moduleA_uut,
not just moduleA_uut.
However, I doubt that modifying the SDF file is the proper way to do
this. SDF annotation has to deal with this all the time, so there has
to be an easy way to do this. You also have to be able to apply SDF
annotation for multiple DUTs, when they are incorporated into larger
systems. I would guess that you can add another argument to
$sdf_annotate to tell it what subpart of the design the SDF applies
to. Something like $sdf_annotate("delay.sdf",
moduleA_tb.moduleA_uut). But since I am just guessing based on what
seems to make sense, you should consult your documentation or another
more knowledgeable engineer.
Article: 143465
"gkonstan" <paraharaktis@gmail.com> wrote:
>hello everyone
>
>I have a problem: After downloading a mcs file to a xc18v02 PROM used for a
>XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now I
>count only 2V instead of 2.5 or 3.3 V in the power supply. I am supposed to
>see what is going wrong, in order to change what has been broken. I have no
>idea what I should do. Any ideas?
You might have a broken FPGA. Did you connect any probes to the board?
Perhaps used a cheap net adapter?
Is this your own design? If so, the power supplies may not be able to
provide the rush-in current of the FPGA. I've seen a Xilinx device
fail before under this condition.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143466On Oct 12, 6:02=A0am, Giorgos_P <giorgos.puik...@gmail.com> wrote: > Hello, > > I'm simulating a VHDL design after synthesis,placement & routing with > the back-annotated model that ISE gives me. > > In order to debug it, I would like to find some internal signals. > However all internal signal names have new names (different than the > ones in the initial VHDL code). These new names probably have to do > with the xilinx-cells to which the signals were maped. > > Does anyone know how I can search for the new name (post-placement > name) of a signal from my initial design VHDL code? > Does ISE provide a way to find this correspondence? > If not how do people proceed to the debugging without access to > internal signals? > > I have seen the post: > "How to obtain original input/output signal name from SDF Timing > Simulation within Modelsim? " > but it's hard to believe that there is no way to find the relationship > between source code and technology primitives (wherever it still > exists after synthesis). > > Thank you in advance, > George I look in my synthesis tool's technology viewer (Synplicity). If the signal hasn't been optimized away, I can usually track it down. And yes, it is rather tedious. BarryArticle: 143467
On Oct 11, 9:05=A0am, GrIsH <grishkun...@gmail.com> wrote:
> I got the problem while receiving the value of "count" (i.e. of
> integer type with value positive as well as negative) in MICROBLAZE
> that was send from custom IP =A0named as encoder module using "User
> Logic Software Register" =A0IPIF. Encoder module counts the value of
> encoder pulses ranges from -5000 to +5000.
>
> I assigned value of =A0 "count" =A0to =A0IP2Bus_Data by converting it to
> std_logic_vector type and receive this value in microblaze software
> application using variable "Data_receive" of int type. and
> "Data_received" was displayed into Hyper Terminal But data received
> was not as expecting mainly the negative numbers.....so how this
> problem is resolved to get exact data, positive as well as negative.
>
> Can i receive the data in Microblaze application in std_logic_vector
> form?? i mean std_logic_vector equivalent form....
>
> OR is there any easier method of transferring negative data ...??
>
> Another problem is...... i found SIGNED(N downto 0) is same as
> std_logic_vector except it represents +ve as well as -ve
> numbers....But it didn't work in my program...why??
>
> my code written in "user_logic".vhd template is given below.....
> -------------------------------------------------------------------------=
-----------------------------------------------------
> signal cnt: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 integer range -5000 to 5000:=3D0;
>
> =A0my_uut1:process(channel_A) is
> =A0 =A0 begin
> =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> =A0 =A0 =A0 =A0 =A0 =A0 direction<=3D '1' and channel_B;
> =A0 =A0 =A0 =A0 end if;
> =A0 =A0 end process;
>
> =A0 =A0 my_uut2:process(channel_A) is
> =A0 =A0 begin
> =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> =A0 =A0 =A0 =A0 =A0 =A0 if(direction=3D'0') then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt+1;
> =A0 =A0 =A0 =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt-1;
> =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
> =A0 =A0 end process;
>
> IP2Bus_Data(0 to 15) =A0<=3D (others=3D>'0');
> IP2Bus_Data(16 to 31) <=3D conv_std_logic_vector(cnt,16);
> -------------------------------------------------------------------------=
----------------------------------------------------
> SOFTWARE APPLICATION IN MICROBLAZE
>
> Xint DataRead;
>
> encoder_module_p =3D (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR;
> XASSERT_NONVOID(encoder_module_p !=3D XNULL);
> encoder_module =3D (Xuint32 *)encoder_module_p;
>
> =A0 =A0 =A0 =A0 while(1){
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DataRead =3D ENCODER_MODULE_mReadSlaveReg=
0(encoder_module, 0);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xil_printf("Received data: %d\r\n", DataR=
ead);
>
> =A0 =A0 =A0 =A0 }
You only included part of your code, I don't see your library
declarations and the other signal declarations. I guess IP2Bus_Data
is an output maybe?
Your problem likely is in the numbering of your bus. How was it
declared, 31 downto 0 (the most common convention) or 0 to 31 (not so
common)? You are assigning the msb of the integer to bit 16 of your
SLV which is in the middle of the vector. I can see why uBlaze is
confused.
I also recommend that you not use std_logic_arith. This has been
covered many, many times here and elsewhere. There are some sticky
issues with using this package. It is highly recommended to use
ieee.std_logic_1164 and ieee.numeric_std. I won't go into the details
of why this is better, but if you continue to use std_logic_arith
don't say you weren't warned.
Rick
Article: 143468On Oct 11, 8:34=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > Please help. > > I want to enclose the following equation data n/2**j with a lower > boundary character pair within Microsoft Office Word 2007. > > 0 <=3D i <=3D low_boundary(n/2**j) ; > > Thank you. > > Weng Have you checked the insert symbol table? If what you need is not there, try inserting a Microsoft Equation object. Insert, Object, Create New, Microsoft Equations 3.0 is the process in Word 2003. RickArticle: 143469
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LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tfAo+Cj4g RGVhciBTaXIvTWFkYW0sCj4KPiBBZnRlciBmb2xsb3dpbmcgYSBudW1iZXIgb2YgaHlwZXJsaW5r cywgSSB3YXMgZXZlbnR1YWxseSBpbmZvcm1lZCBvbgo+IFdXVy5BbHRlcmEuY29tL2IvdHdpdHRl ci1mYWNlYm9vay1naXZlYXdheS1ydWxlcy5odG1sCj4gOiJbLi5dCj4KPiAxLiBFbGlnaWJpbGl0 eTogT25seSBsZWdhbCBwZXJzb25zLCAoaSkgd2hvIGFyZSBwaHlzaWNhbGx5IGxvY2F0ZWQgYW5k Cj4gcmVzaWRpbmcgaW4gdGhlIENvbnRpbmVudGFsIFUuUy4gb3Igb3RoZXJ3aXNlIGVsaWdpYmxl IHVuZGVyCj4gYXBwbGljYWJsZSBsb2NhbCBsYXdzLCBbLi5dCj4KPiBbLi5dIgo+Cj4gSSBoYXZl IG5ldmVyIGJlZW4gaW4gdGhlIENvbnRpbmVudGFsIFUuUy46IHNvIGFtIEkgZWxpZ2libGUgdG8g d2luIG9uZQo+IG9mIHRob3NlIGtpdHMgb3IgZGlkIHlvdSB3YXN0ZSBteSB0aW1lPwo+Cj4gWW91 cnMgZmFpdGhmdWxseSwKPiBDb2xpbiBQYXVsIEdsb3N0ZXIKCndhc3RlIG9mIHRpbWUKbW9zdCBz dWNoIHRoaW5ncyBhcmUgZm9yIFVTIHJlc2lkZW50cyBvbmx5CgpBbnR0aQ==Article: 143470
On Oct 12, 3:14=A0am, David Brown <da...@westcontrol.removethisbit.com> wrote: > rickman wrote: > > On Oct 10, 5:51 am, n...@puntnl.niks (Nico Coesel) wrote: > >> Joseph Yiu <joseph....@somewhereinarm.com> wrote: > >>> rickman wrote: > >>>> As others have indicated, it may be easy to implement CPUs in FPGAs, > >>>> but they do not run nearly as fast as high end CPUs in fixed silicon= . > >>>> Martin indicated that if your algorithm is amenable to breaking it > >>>> into many processes running in parallel, many processors can be used= , > >>>> each doing a part of the calculation with the load fairly balanced. > >>> Regarding speed, actually you could have better performance by runnin= g a > >>> CPU in FPGA compared to standard microcontrollers. Flash memory usual= ly > >>> have a flash memory of 25MHz to 50MHz, while block RAM in FPGA can be > >>> much faster. So you can run a processor at high clock speed on FPGA > >>> (e.g. 100MHz) with zero wait state, compared to microcontroller produ= cts > >>> running at 100MHz with 1 or 2 wait states on silicon. > >> That's not true. Most of such microcontrollers have wider flash and > >> use pre-fetch and branch prediction buffers (a small smart cache) to > >> undo the effects of the slower flash. NXP has been doing this for > >> years with the LPC2000 series and has included similar schemes on > >> their new LPC1300 en LPC1700 series. > > > Yes, but they only get speeds up to roughly 100 MHz. =A0An FPGA CPU wit= h > > internal memory can run 200 MHz or faster, depending on the CPU. =A0The > > only ARM parts that run much faster than 100 MHz are not using Flash > > at that speed or have cache. > > That's a very mixed-up argument. =A0Microcontrollers aimed at lower speed= s > run happily from flash (especially with wider buses and some buffering). > =A0 At higher speeds, you run from RAM or flash with caches. =A0Whereas o= n > an FPGA, you run from RAM or from flash with caches. =A0What's the > difference? =A0In either case, you fit your memory buses, bandwidths and > caches to suit the desired throughput of the processor. Yes, in reality I don't care if the program is running from RAM or Flash, I only care how fast it runs. But the difference is cost. The high end 200+ MHz CPUs are not as close to free as the low end MCUs and FPGA cores are. I know that if you figure the cost per whatever of FPGAs vs MCUs, the MCUs are less expensive. But you can often put a CPU in an FPGA without it impacting the size of the design significantly (meaning requiring a larger part and more money). In fact, I am working on adding features to an FPGA design where I don't have the option of using a larger part and it is going to push the envelope on capacity. My last fallback plan is to replace significant amounts of logic with a small CPU for a net savings of LUTs. In reality, FPGA CPUs and MCUs are different animals and have very different advantages and disadvantages. But when it comes to speed, an FPGA CPU will always have a high clock speed (assuming you don't pick a lame core) while MCUs have a price/performance curve. But then when was the last time you used an MCU that was truly speed limited? I know this seldom happens to me. RickArticle: 143471
hello everyone, i have been trying to integrate chipscope pro in the EDK using XPS but i didnt find any appropriate tutorials. i am using a microblaze processor and a plb bus. Please help me if you could suggest some approproate links. i tried to find out such tutorial by myself but all of them refered to integrating chipscope using ISE. any kind of help would be highly appreciated. PrashantArticle: 143472
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On October 12th, 2009, Altera Announcements apparently misleadingly
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Article: 143473
On Oct 12, 9:02=A0am, rickman <gnu...@gmail.com> wrote:
> On Oct 11, 9:05=A0am, GrIsH <grishkun...@gmail.com> wrote:
>
>
>
> > I got the problem while receiving the value of "count" (i.e. of
> > integer type with value positive as well as negative) in MICROBLAZE
> > that was send from custom IP =A0named as encoder module using "User
> > Logic Software Register" =A0IPIF. Encoder module counts the value of
> > encoder pulses ranges from -5000 to +5000.
>
> > I assigned value of =A0 "count" =A0to =A0IP2Bus_Data by converting it t=
o
> > std_logic_vector type and receive this value in microblaze software
> > application using variable "Data_receive" of int type. and
> > "Data_received" was displayed into Hyper Terminal But data received
> > was not as expecting mainly the negative numbers.....so how this
> > problem is resolved to get exact data, positive as well as negative.
>
> > Can i receive the data in Microblaze application in std_logic_vector
> > form?? i mean std_logic_vector equivalent form....
>
> > OR is there any easier method of transferring negative data ...??
>
> > Another problem is...... i found SIGNED(N downto 0) is same as
> > std_logic_vector except it represents +ve as well as -ve
> > numbers....But it didn't work in my program...why??
>
> > my code written in "user_logic".vhd template is given below.....
> > -----------------------------------------------------------------------=
-------------------------------------------------------
> > signal cnt: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 integer range -5000 to 5000:=3D0;
>
> > =A0my_uut1:process(channel_A) is
> > =A0 =A0 begin
> > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> > =A0 =A0 =A0 =A0 =A0 =A0 direction<=3D '1' and channel_B;
> > =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 end process;
>
> > =A0 =A0 my_uut2:process(channel_A) is
> > =A0 =A0 begin
> > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> > =A0 =A0 =A0 =A0 =A0 =A0 if(direction=3D'0') then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt+1;
> > =A0 =A0 =A0 =A0 =A0 =A0 else
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt-1;
> > =A0 =A0 =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 end process;
>
> > IP2Bus_Data(0 to 15) =A0<=3D (others=3D>'0');
> > IP2Bus_Data(16 to 31) <=3D conv_std_logic_vector(cnt,16);
> > -----------------------------------------------------------------------=
------------------------------------------------------
> > SOFTWARE APPLICATION IN MICROBLAZE
>
> > Xint DataRead;
>
> > encoder_module_p =3D (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR;
> > XASSERT_NONVOID(encoder_module_p !=3D XNULL);
> > encoder_module =3D (Xuint32 *)encoder_module_p;
>
> > =A0 =A0 =A0 =A0 while(1){
>
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DataRead =3D ENCODER_MODULE_mReadSlaveR=
eg0(encoder_module, 0);
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xil_printf("Received data: %d\r\n", Dat=
aRead);
>
> > =A0 =A0 =A0 =A0 }
>
> You only included part of your code, I don't see your library
> declarations and the other signal declarations. =A0I guess IP2Bus_Data
> is an output maybe?
>
> Your problem likely is in the numbering of your bus. =A0How was it
> declared, 31 downto 0 (the most common convention) or 0 to 31 (not so
> common)? =A0You are assigning the msb of the integer to bit 16 of your
> SLV which is in the middle of the vector. =A0I can see why uBlaze is
> confused.
>
> I also recommend that you not use std_logic_arith. =A0This has been
> covered many, many times here and elsewhere. =A0There are some sticky
> issues with using this package. =A0It is highly recommended to use
> ieee.std_logic_1164 and ieee.numeric_std. =A0I won't go into the details
> of why this is better, but if you continue to use std_logic_arith
> don't say you weren't warned.
>
> Rick
Here is my complete code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
---------------------------------------------------------------------------=
---
-- Entity section
---------------------------------------------------------------------------=
---
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible
registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer
acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer
acknowledgement
-- IP2Bus_Error -- IP to Bus error response
---------------------------------------------------------------------------=
---
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer :=3D 32;
C_NUM_REG : integer :=3D 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
channel_A: in std_logic;
channel_B: in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to
C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to
C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to
C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to
C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to
C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
---------------------------------------------------------------------------=
---
-- Architecture section
---------------------------------------------------------------------------=
---
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register
example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to
C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal cnt: integer range -1000 to 1000:=3D0;
signal direction: std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible
registers
--
-- Note:
-- The example code presented here is to show you one way of reading/
writing
-- software accessible registers implemented in the user logic slave
model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
-- to one software accessible register by the top level template.
For example,
-- if you have four 32 bit software accessible registers in the user
logic,
-- you are basically operating on the following memory mapped
registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <=3D Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <=3D Bus2IP_RdCE(0 to 0);
slv_write_ack <=3D Bus2IP_WrCE(0);
slv_read_ack <=3D Bus2IP_RdCE(0);
-- Encoder Module Code
-----------------------------------------------
=20
----------------------------------------------------------------------
my_uut1:process(channel_A) is
begin
if(channel_A 'event and channel_A=3D'1') then
direction<=3D '1' and channel_B;
end if;
end process;
my_uut2:process(channel_A) is
begin
if(channel_A 'event and channel_A=3D'1') then
if(direction=3D'0') then
cnt<=3Dcnt+1;
else
cnt<=3Dcnt-1;
end if;
end if;
end process;
=20
----------------------------------------------------------------------
=20
----------------------------------------------------------------------
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk =3D '1' then
if Bus2IP_Reset =3D '1' then
slv_reg0 <=3D (others =3D> '0');
else
case slv_reg_write_sel is
when "1" =3D>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) =3D '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=3D Bus2IP_Data
(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others =3D> null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" =3D> slv_ip2bus_data <=3D slv_reg0;
when others =3D> slv_ip2bus_data <=3D (others =3D> '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
--IP2Bus_Data <=3D slv_ip2bus_data when slv_read_ack =3D '1' else
--(others =3D> '0');
-- my logic--------------------------------------------------------
=20
-------------------------------------------------------------------
IP2Bus_Data(0 to 15) <=3D (others=3D>'0');
IP2Bus_Data(16 to 31) <=3D conv_std_logic_vector(cnt,16);
-------------------------------------------------------------------
-------------------------------------------------------------------
IP2Bus_WrAck <=3D slv_write_ack;
IP2Bus_RdAck <=3D slv_read_ack;
IP2Bus_Error <=3D '0';
end IMP;
Article: 143474On Oct 12, 9:07=A0am, rickman <gnu...@gmail.com> wrote: > On Oct 11, 8:34=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > Hi, > > Please help. > > > I want to enclose the following equation data n/2**j with a lower > > boundary character pair within Microsoft Office Word 2007. > > > 0 <=3D i <=3D low_boundary(n/2**j) ; > > > Thank you. > > > Weng > > Have you checked the insert symbol table? =A0If what you need is not > there, try inserting a Microsoft Equation object. =A0Insert, Object, > Create New, Microsoft Equations 3.0 is the process in Word 2003. > > Rick Hi Rick, Thank you. I will try your method. The character pair is not within the insert symbol table. Weng
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