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Pete Fraser wrote: > I'm just finishing up design of an analog data acquisition system > (16 bits, 100 kHz sampling), and need to come up with a > test / verification scheme. I've looked at some of the arbitrary > waveform generators available, and they seem to be expensive, > and not very accurate (13 or 14 bits). > There seems to be a wide variety of inexpensive USB and > firewire audio DACs available, and some of them are > specified to 192 kHz sampling and 24 bits. If I could buy > a DAC with 24 bits and 192 kHz (or higher) sampling I > could write some code to generate a source file, play it through > the DAC, capture the resultant signals in the test system, and > analyze the system performance. If your system actually performs to 16 bit @ 100kHz, you will be analysing then imperfections of the abovementioned stuff rather then your performance. > Has anyone here done that? Can you offer any pointers? > It's not clear from the specifications / manual of the DACs I've > looked at whether filtering can be disabled. Most are > specified from 20 Hz to 20 kHz, and seem intended to > take in 44.1 kHz or 48 kHz, do a filtered up-conversion, > and (presumably) have a sloppy output filter. Some specify > that they can accept 192 kHz, but I've no idea what filters > they use and whether they can be bypassed. AD5791 > Any thoughts / observations? We developed the data acqusition board for geophysics: http://www.abvolt.com/projects_and_solutions/data_acquisition_board.htm SNR ~ 133dB, THD ~ 0.0001% We had exactly the same problem, so we had to design in the generator for self testing. That generator should be DC accurate, allow for the generation of the pulsed waveforms as well as the super clean sinewave. I used the general purpose DAC with heavy analog filtering. Audio DACs are delta-sigmas, their bandwidth is from 0 to ~0.9 of Nyquist at the corresponding sample rate. Audio DACs aren't DC accurate. By nature of operation of delta sigma, the signal is bandlimited, i.e. you can't generate a sharp pulse. Other feature of the audio DACs is the huge pile of the noise shaping residuals in the near ultrasound area. Also, audio DACs are power hungry, work only synchronously and can't be stopped so you have to feed them with the data continuously. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 149501
"Vladimir Vassilevsky" <nospam@nowhere.com> wrote in message news:h9CdnVgyyrq7HVDRnZ2dnUVZ_vadnZ2d@giganews.com... > AD5791 It looks like a nice part. The eval board is cheap, and it will give me a chance to play with a Blackfin also. > We developed the data acqusition board for geophysics: > > http://www.abvolt.com/projects_and_solutions/data_acquisition_board.htm > > SNR ~ 133dB, THD ~ 0.0001% Looks cool. I'm impressed that you got in on 4-layer. Thanks PeteArticle: 149502
Pete Fraser wrote: > "Vladimir Vassilevsky" <nospam@nowhere.com> wrote in message > news:h9CdnVgyyrq7HVDRnZ2dnUVZ_vadnZ2d@giganews.com... > >>We developed the data acqusition board for geophysics: >>http://www.abvolt.com/projects_and_solutions/data_acquisition_board.htm >>SNR ~ 133dB, THD ~ 0.0001% > > > Looks cool. > I'm impressed that you got in on 4-layer. But for EMC requirements and BGA packages, just about anything could be laid in two layers. Multilayer boards only enfeeble the developers. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 149503
Hello, hello, I'm trying to use a DCM on my Microblaze (EDK 11.2) project so that I can multiply the 200MHz output clock of the project-generated clock_generator IP (the CLKOUT2 output) by a factor of two (for 400MHz total that I want to drive a custom peripheral with). The clock_generator also generates the 100MHz clock that drives the Microblaze. I require the generated 400MHz clock to be in phase with the 100MHz clock. The following ports are set up: - 200MHz signal from the clock_generator IP is fed to the CLKIN port of the DCM IP - DCM's CLK0 (buffered) to the CLKFB port - feed the CLK2X (buffered) signal into the IP that I want to drive at 400MHz When I try to generate the bitstream I get the following error: Analyzing implementation/system.par ******************************************************************************** ERROR: 3 constraints not met. PAR could not meet all timing constraints. A bitstream will not be generated. To disable the PAR timing check: 1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS. OR 2> Type following at the XPS prompt: XPS% xset enable_par_timing_error 0 ******************************************************************************** ******************************************************************************** ERROR: 3 constraints not met. PAR could not meet all timing constraints. A bitstream will not be generated. To disable the PAR timing check: 1> Disable the "Treat timing closure failure as error" option from the Project Options dialog in XPS. OR 2> Type following at the XPS prompt: XPS% xset enable_par_timing_error 0 ******************************************************************************** make: *** [implementation/system.bit] Error 2 It is my understanding that bypassing timing errors is a good way to get the project to fail in a strange way, has anyone dealt with this problem before? Is there a better way to multiply the clock that doesn't involve using a DCM? Thanks in advance, Sean.Article: 149504
Sean What fpga are you using? Have you checked the datasheet to confirm that it can run at the frequency you want? If ISE is giving timing errors then you should be able to see what it is complaining about. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149505
On Sun, 31 Oct 2010 19:15:11 -0700 (PDT), Griffin <captain.griffin@gmail.com> wrote: >Hello, hello, > >I'm trying to use a DCM on my Microblaze (EDK 11.2) project so that I >can multiply the 200MHz output clock of the project-generated >clock_generator IP (the CLKOUT2 output) by a factor of two (for 400MHz >total that I want to drive a custom peripheral with). The >clock_generator also generates the 100MHz clock that drives the >Microblaze. I require the generated 400MHz clock to be in phase with >the 100MHz clock. DCM IS the right way to do this. If the >PAR could not meet all timing constraints. A bitstream will not be >generated. >1> Disable the "Treat timing closure failure as error" option from the >Project Options dialog in XPS. This looks like the tools have put you in a double-bind: you need to analyze timing on the bitfile to see where the errors are: but the tool won't create a bitfile. Turn off the error as per the instructions, and generate a bitfile, simply to see the timing analysis report. You may need to pipeline your peripheral more deeply, to meet 400MHz timings, especially at the interface between it and the Microblaze local bus. - BrianArticle: 149506
On Nov 1, 4:10=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 31 Oct 2010 19:15:11 -0700 (PDT), Griffin <captain.grif...@gmail.= com> > wrote: > > >Hello, hello, > > >I'm trying to use a DCM on my Microblaze (EDK 11.2) project so that I > >can multiply the 200MHz output clock of the project-generated > >clock_generator IP (the CLKOUT2 output) by a factor of two (for 400MHz > >total that I want to drive a custom peripheral with). The > >clock_generator also generates the 100MHz clock that drives the > >Microblaze. I require the generated 400MHz clock to be in phase with > >the 100MHz clock. > > DCM IS the right way to do this. > > If the > > >PAR could not meet all timing constraints. A bitstream will not be > >generated. > >1> Disable the "Treat timing closure failure as error" option from the > >Project Options dialog in XPS. > > This looks like the tools have put you in a double-bind: > you need to analyze timing on the bitfile to see where the errors are: > but the tool won't create a bitfile. > > Turn off the error as per the instructions, and generate a bitfile, simpl= y to > see the timing analysis report. > > You may need to pipeline your peripheral more deeply, to meet 400MHz timi= ngs, > especially at the interface between it and the Microblaze local bus. > > - Brian > you need to analyze timing on the bitfile This isn't correct, the timing analysis will be done on the design netlist at the various stages of implementation. The only thing that the bitfile is used for is programming the device. The OP indicated that PAR reported 3 timing constraint errors. Looking at the PAR report file or running the Timing Analyzer (aka trce) on the placed and routed NCD file from PAR will indicate which paths failed timing. BTW, 400 MHz is pretty fast so there is a good chance that the design doesn't meet timing unless careful consideration has been made to the design construction. Ed McGettigan -- Xilinx Inc.Article: 149507
Hey, Thanks everyone for the tips - after reading through all the info, I decided it all seemed a bit daunting, and hence I'm not sure it'll work out as intended, and that in turn limits my budget. (If I can't get it working due to not having the right software licenses for example, I'll end up having wasted loads of money on hardware, and the details of exactly what I would or would not need seemed challenging) That being the case, I went for the lowest end Altera Cyclone II mini development board, a bigger flash configuration chip (16Mbit) to solder to the board, and a USB blaster programmer. All from ebay for $65. I plan to get a NIOS II processor, and hook it up so it can execute code from spare space at the end of the flash configuration chip. The choice was partly motivated by my desire to have it portable, because I've realised it would be much cooler if I could demonstrate my device handheld powered from some AA batteries than a desk mounted version. I have also realised that no FPGA's seem to come in packages which I have equipment to hand solder, so I've gotta use a dev board rather than just sticking it in a DIP24 socket... Altera parts also makes sense because my college already has contracts from Altera for software. There is talk here of the Cortex M1/3 processor here - is that the kind of thing you can just download and use in a softcore as a student, or do you have to pay a multi-million dollar license to get hold of it? Thanks OliverArticle: 149508
Hi Folks, we just published the latest edition of Xcell Journal with some great how-to and methodology articles: http://www.xilinx.com/publications/xcellonline/index.htm. Contact me if you would like to contribute an article to an upcoming issue Xcell. Cheers, Mike SantariniArticle: 149509
@Jon and Ed: I am using the Virtex-4 SX (ML402 devellopment board). I compiled the peripheral using ISE and the compiler told me that the fastest I can clock it at is ~430MHz. 400MHz is well below that, so I don't think it's an issue with the design of the peripheral itself. For a better idea as to what I'm doing, I have a peripheral connected via FSL to the microblaze. My code inside the peripheral essentially counts the number of pulses it receives from the outside world and then maps that value to the registers of the peripheral so I can read them out to the microblaze. I tried to do this asynchronously, but encountered readout errors where (what we think happened) the counters were being read out while the bits were rolling over mid-count, creating an output that was nonsense. So, I switched to a counter that is synchronous with the readout clock (ie, every clock cycle I check to see if the input is high, then I see if the input is high, if so, and I haven't already counted that high pulse, I increment the counter). I want to multiply the clock speed so I can probe the input faster to make sure that I'm not missing any counts, but still work in phase with the readout clock (ie, the FSL bus clock, 100MHz). This is a little oversimplified, but that's the jist of it.Article: 149510
On Nov 1, 3:46=A0pm, Griffin <captain.grif...@gmail.com> wrote: > @Jon and Ed: I am using the Virtex-4 SX (ML402 devellopment board). I > compiled the peripheral using ISE and the compiler told me that the > fastest I can clock it at is ~430MHz. 400MHz is well below that, so I > don't think it's an issue with the design of the peripheral itself. > > For a better idea as to what I'm doing, I have a peripheral connected > via FSL to the microblaze. My code inside the peripheral essentially > counts the number of pulses it receives from the outside world and > then maps that value to the registers of the peripheral so I can read > them out to the microblaze. > > I tried to do this asynchronously, but encountered readout errors > where (what we think happened) the counters were being read out while > the bits were rolling over mid-count, creating an output that was > nonsense. So, I switched to a counter that is synchronous with the > readout clock (ie, every clock cycle I check to see if the input is > high, then I see if the input is high, if so, and I haven't already > counted that high pulse, I increment the counter). I want to multiply > the clock speed so I can probe the input faster to make sure that I'm > not missing any counts, but still work in phase with the readout clock > (ie, the FSL bus clock, 100MHz). > > This is a little oversimplified, but that's the jist of it. What the synthesis tools report for timing is just an estimate. If can be off by quite bit, either high or low. If you are trying to read the counter from a clock domain that is different than the one it is in, then you need to synchronize it. A simple way to do this is to use a Gray code counter, and convert it back to binary either in the clock domain you are reading it into, or just do it in software. There is an example of how to code a Gray code counter in Project Navigator in the language templates library. The language templates library is under the edit menu, or just click the light bulb icon. Regards, John McCaskill www.FasterTechnology.comArticle: 149511
On Mon, 1 Nov 2010 08:21:01 -0700 (PDT), Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: >On Nov 1, 4:10 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Sun, 31 Oct 2010 19:15:11 -0700 (PDT), Griffin <captain.grif...@gmail.com> >> wrote: >> This looks like the tools have put you in a double-bind: >> you need to analyze timing on the bitfile to see where the errors are: >> but the tool won't create a bitfile. >This isn't correct, the timing analysis will be done on the design >netlist at the various stages of implementation. The only thing that >the bitfile is used for is programming the device. oops, not enough coffee this morning, obviously! I was under the impression that PAR was not writing its output. Of course it is; however the subsequent "bitgen" process is not running. Static timing requires the PAR output, which the original poster will have. The rest of my message still stands; he will have to get the actual problem from timing analysis and fix it. - BrianArticle: 149512
On Mon, 1 Nov 2010 13:46:26 -0700 (PDT), Griffin <captain.griffin@gmail.com> wrote: >@Jon and Ed: I am using the Virtex-4 SX (ML402 devellopment board). I >compiled the peripheral using ISE and the compiler told me that the >fastest I can clock it at is ~430MHz. 400MHz is well below that, so I >don't think it's an issue with the design of the peripheral itself. If "the compiler" is the synthesis tool, then be aware that its reported timing is merely an estimate. It is often within 10% of the final speed, so you cannot rule out a design issue yet. One "fiddle" worth trying when you are close to meeting timing, is to re-run MAP and PAR with another placement seed. You will get different results from a different seed, sometimes by 5% or so, and that might be enough to meet timing. Otherwise, be guided by the errors listed in the timing report (file.twx or .twr). - BrianArticle: 149513
Hi all,
I have a very simple statemachine that sets some control signals to
interact with a third party IP. The code looks roughly as follows:
entity testip is
port (
...
fifo_dataout : in std_logic_vector(0 to 31);
ip_dataout : in std_logic_vector(0 to 31);
ip_ce : out std_logic;
ip_we : out std_logic;
ip_datain : out std_logic_vector(0 to 31);
);
end entity testip;
architecture imp of testip is
signal ip_ce_ns : std_logic;
signal ip_we_ns : std_logic;
signal ip_ce_cs : std_logic;
signal ip_we_cs : std_logic;
signal ip_dataout_i : std_logic_vector(0 to 31);
...
begin
COMB : process (...)
begin
ip_ce_ns <= ip_ce_cs;
ip_we_ns <= ip_we_cs;
case ip_nstate_cs is
when IDLE =>
...
end case;
end process COMB;
REG: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ip_ce_cs <= '1';
ip_we_cs <= '1';
...
else
ip_ce_cs <= ip_ce_ns;
ip_we_cs <= ip_we_ns;
...
end if;
end if;
end process REG;
S0: ip_ce <= ip_ce_cs;
S1: ip_we <= ip_we_cs;
S2: ip_datain <= fifo_dataout;
S3: ip_dataout_i <= Ip_dataout;
end architecture imp;
Sythesis works fine, however, when applying the following constraint
file I get ERROR:ConstraintSystem:59 - NET "testip/ip_we" not found.
The same occurs for testip/ip_datain and testip/ip_ce.
Net testip/ip_datain<*> MAXDELAY = 2 ns;
Net testip/ip_ce MAXDELAY = 2 ns;
Net testip/ip_we MAXDELAY = 2 ns;
I checked the netlist, and indeed there is neither a testip/ip_we, a
testip/ip_ce nor a testip/ip_datain net. I checked the sythesis log and
it does not say that the signals have been trimmed! Anyone an idea why
these signals are not in the netlist, all very confusing.
Many thanks for any feedback!
Article: 149514On Nov 1, 4:22=A0pm, Richard <Rich...@yahoo.com> wrote: > Hi all, > > I have a very simple statemachine that sets some control signals to > interact with a third party IP. The code looks roughly as follows: > > entity testip is > =A0 =A0port ( > =A0 =A0 =A0... > =A0 =A0 =A0fifo_dataout =A0 =A0 =A0 =A0: in =A0std_logic_vector(0 to 31); > =A0 =A0 =A0ip_dataout =A0 =A0 =A0 =A0 =A0: in =A0std_logic_vector(0 to 31= ); > =A0 =A0 =A0ip_ce =A0 =A0 =A0 =A0 =A0 =A0 =A0 : out std_logic; > =A0 =A0 =A0ip_we =A0 =A0 =A0 =A0 =A0 =A0 =A0 : out std_logic; > =A0 =A0 =A0ip_datain =A0 =A0 =A0 =A0 =A0 : out std_logic_vector(0 to 31); > =A0 =A0 =A0); > > end entity testip; > > architecture imp of testip is > > =A0 =A0signal ip_ce_ns =A0 =A0 : std_logic; > =A0 =A0signal ip_we_ns =A0 =A0 : std_logic; > =A0 =A0signal ip_ce_cs =A0 =A0 : std_logic; > =A0 =A0signal ip_we_cs =A0 =A0 : std_logic; > =A0 =A0signal ip_dataout_i : std_logic_vector(0 to 31); > =A0 =A0... > > begin > > COMB : process (...) > =A0 =A0 =A0 =A0begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0ip_ce_ns <=3D ip_ce_cs; > =A0 =A0 =A0 =A0 =A0 =A0 =A0ip_we_ns <=3D ip_we_cs; > > =A0 =A0 =A0 =A0 =A0 case ip_nstate_cs is > =A0 =A0 =A0 =A0 =A0 =A0 =A0when IDLE =A0 =A0 =A0=3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0... > > =A0 =A0 =A0 =A0 =A0 end case; > end process COMB; > > REG: process (Clk) is > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0if (Clk'event and Clk =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (Rst =3D '1') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ip_ce_cs <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ip_we_cs <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ip_ce_cs <=3D ip_ce_ns; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ip_we_cs <=3D ip_we_ns; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0end if; > end process REG; > > S0: =A0 =A0 ip_ce <=3D ip_ce_cs; > S1: =A0 =A0 ip_we <=3D ip_we_cs; > S2: =A0 =A0 ip_datain <=3D fifo_dataout; > S3: =A0 =A0 ip_dataout_i <=3D Ip_dataout; > > end architecture imp; > > Sythesis works fine, however, when applying the following constraint > file I get ERROR:ConstraintSystem:59 - =A0NET "testip/ip_we" not found. > The same occurs for testip/ip_datain and testip/ip_ce. > > Net testip/ip_datain<*> MAXDELAY =3D 2 ns; > Net testip/ip_ce MAXDELAY =3D 2 ns; > Net testip/ip_we MAXDELAY =3D 2 ns; > > I checked the netlist, and indeed there is neither a testip/ip_we, a > testip/ip_ce nor a testip/ip_datain net. I checked the sythesis log and > it does not say that the signals have been trimmed! Anyone an idea why > these signals are not in the netlist, all very confusing. > > Many thanks for any feedback! The signals are (probably) there with a new (and somewhat confusing) name. Every synthesis tool I have ever used has been loose and free about renaming signals. RK.Article: 149515
On Nov 1, 1:46=A0pm, Griffin <captain.grif...@gmail.com> wrote: > @Jon and Ed: I am using the Virtex-4 SX (ML402 devellopment board). I > compiled the peripheral using ISE and the compiler told me that the > fastest I can clock it at is ~430MHz. 400MHz is well below that, so I > don't think it's an issue with the design of the peripheral itself. > > For a better idea as to what I'm doing, I have a peripheral connected > via FSL to the microblaze. My code inside the peripheral essentially > counts the number of pulses it receives from the outside world and > then maps that value to the registers of the peripheral so I can read > them out to the microblaze. > > I tried to do this asynchronously, but encountered readout errors > where (what we think happened) the counters were being read out while > the bits were rolling over mid-count, creating an output that was > nonsense. So, I switched to a counter that is synchronous with the > readout clock (ie, every clock cycle I check to see if the input is > high, then I see if the input is high, if so, and I haven't already > counted that high pulse, I increment the counter). I want to multiply > the clock speed so I can probe the input faster to make sure that I'm > not missing any counts, but still work in phase with the readout clock > (ie, the FSL bus clock, 100MHz). > > This is a little oversimplified, but that's the jist of it. 430 MHz =3D 2326 pS 400 MHz =3D 2500 pS The difference here is 174pS between the two rates. This is well below the margin of error of a synthesized timing estimate as John and Brian have pointed out. Have you been able to determine the failing paths yet? Ed McGettigan -- Xilinx Inc.Article: 149516
On Nov 1, 2:24=A0pm, Oliver Mattos <omat...@gmail.com> wrote: > Hey, > > Thanks everyone for the tips - after reading through all the info, I > decided it all seemed a bit daunting, and hence I'm not sure it'll > work out as intended, and that in turn limits my budget. (If I can't > get it working due to not having the right software licenses for > example, I'll end up having wasted loads of money on hardware, and the > details of exactly what I would or would not need seemed challenging) > > That being the case, I went for the lowest end Altera Cyclone II mini > development board, a bigger flash configuration chip (16Mbit) to > solder to the board, and a USB blaster programmer. =A0All from ebay for > $65. > > I plan to get a NIOS II processor, and hook it up so it can execute > code from spare space at the end of the flash configuration chip. > > The choice was partly motivated by my desire to have it portable, > because I've realised it would be much cooler if I could demonstrate > my device handheld powered from some AA batteries than a desk mounted > version. =A0I have also realised that no FPGA's seem to come in packages > which I have equipment to hand solder, so I've gotta use a dev board > rather than just sticking it in a DIP24 socket... =A0Altera parts also > makes sense because my college already has contracts from Altera for > software. > > There is talk here of the Cortex M1/3 processor here - is that the > kind of thing you can just download and use in a softcore as a > student, or do you have to pay a multi-million dollar license to get > hold of it? > > Thanks > Oliver Yeah, it's a megabuck core. The only way you can use a CM1 is to go the Actel route where they have already paid the license fee. I'm not sure of their arrangement with ARM, but I expect they are also paying a per chip fee as well. They only support the CM1 on a "special" version of the FPGA which I suspect is only special in the higher price to pay the per unit license fee. RickArticle: 149517
> The signals are (probably) there with a new (and somewhat confusing) > name. > > Every synthesis tool I have ever used has been loose and free about > renaming signals. And is there any good way to find out in what they have been renamed? ThanksArticle: 149518
On Nov 1, 6:07=A0pm, Richard <Rich...@yahoo.com> wrote: > > The signals are (probably) there with a new (and somewhat confusing) > > name. > > > Every synthesis tool I have ever used has been loose and free about > > renaming signals. > > And is there any good way to find out in what they have been renamed? > > Thanks Unless the signal has been merged into the middle of a LUT the name is usually the highest level net name. In this case it would likely be the net that is connected to the ip_we and ip_ce ports on this core. Ed McGettigan -- Xilinx Inc.Article: 149519
On Mon, 01 Nov 2010 23:22:05 +0000, Richard <Richard@yahoo.com> wrote: >Hi all, > >I have a very simple statemachine that sets some control signals to >interact with a third party IP. The code looks roughly as follows: ... >Sythesis works fine, however, when applying the following constraint >file I get ERROR:ConstraintSystem:59 - NET "testip/ip_we" not found. >The same occurs for testip/ip_datain and testip/ip_ce. > >Net testip/ip_datain<*> MAXDELAY = 2 ns; >Net testip/ip_ce MAXDELAY = 2 ns; >Net testip/ip_we MAXDELAY = 2 ns; > >I checked the netlist, and indeed there is neither a testip/ip_we, a >testip/ip_ce nor a testip/ip_datain net. I checked the sythesis log and >it does not say that the signals have been trimmed! Anyone an idea why >these signals are not in the netlist, all very confusing. Combinational net names can get sliced, diced, absorbed and further processed so it might be difficult to find out what they've become, if indeed they've survived at all. So my suggestion would be to set your constraints based on clock period and chip IOs instead of trying to set delays on nets. One helpful note might be that register names are almost always preserved so you might be able to refer to ip_we_cs etc more easily. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149520
Sean Looing at the V4 datasheet the max freq of the CLK2X is 400MHz, so you might have a problem with timing. Maybe if you had a better speed grade device things might be a bit easier. But all you can do is look at the failing paths and see if you can get them to time. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149521
> Combinational net names can get sliced, diced, absorbed and further > processed so it might be difficult to find out what they've become, if > indeed they've survived at all. So my suggestion would be to set your > constraints based on clock period and chip IOs instead of trying to > set delays on nets. > One helpful note might be that register names are almost always > preserved so you might be able to refer to ip_we_cs etc more easily. Thanks for all your feedback, is there any way that with some kind of options I can make sure that the name of the nets is preserved? The problem is that these nets interact with a third party IP, and the constraints on these nets are apparantly mandotory, so in other words I have to contrain these particular signals to make the whole design working.Article: 149522
On 31/10/2010 15:06, Pete Fraser wrote: > I'm just finishing up design of an analog data acquisition system > (16 bits, 100 kHz sampling), and need to come up with a > test / verification scheme. I've looked at some of the arbitrary > waveform generators available, and they seem to be expensive, > and not very accurate (13 or 14 bits). > > There seems to be a wide variety of inexpensive USB and > firewire audio DACs available, and some of them are > specified to 192 kHz sampling and 24 bits. If I could buy > a DAC with 24 bits and 192 kHz (or higher) sampling I > could write some code to generate a source file, play it through > the DAC, capture the resultant signals in the test system, and > analyze the system performance. > > Has anyone here done that? Can you offer any pointers? > It's not clear from the specifications / manual of the DACs I've > looked at whether filtering can be disabled. Most are > specified from 20 Hz to 20 kHz, and seem intended to > take in 44.1 kHz or 48 kHz, do a filtered up-conversion, > and (presumably) have a sloppy output filter. Some specify > that they can accept 192 kHz, but I've no idea what filters > they use and whether they can be bypassed. > > Any thoughts / observations? > If you get an appropriate DAC (such as the AD5791) with an SPI interface, you could connect it up to an FTDI FT4232H module. That would let you fairly easily run a high speed SPI bus directly from a PC. If I remember the figures correctly, the FT4232H can run an SPI bus at 30 MHz. You get relatively long latencies using USB and a PC - it's not much good if you have to mix reading and writing. But you can write out a continuous stream at full speed.Article: 149523
I have the Nios 2 board with cyclone II like this: http://www.altera.com/products/devkits/altera/kit-nios-2c35.html My problem is that I can't implement very simple program on the fpga. On the beginning I want use switches and leds to view that my program is running. When I plug in the power adapter to the board, the led factory is on( Is this mode I red in the documentation is running the NIOS 2 with simple program) . When I program fpga via USB Blaster for a one second led User is on but after that it returns to the factory mode and led factory is on. I don't know how to program this board with simple logic program. Can anyone explain me what am I doing wrong?Article: 149524
> When I program fpga via USB Blaster for > a one second led User is on but after that it returns to the factory > mode and led factory is on. I don't know how to program this board > with simple logic program. Can anyone explain me what am I doing wrong? From memory one of the FPGA pins is 'reset_n' (or reset) into the CPLD that controls configuration. If this isn't held at the right polarity the image will be immediately reset. Have a look at the example designs provided on the Altera web site. Nial.
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