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All the CAM really is, is a soft version of the hard coded logic. What I
mean is
by using the CAM you have the capability of reloading the 'tables' used
for the
hard coded decode. In the case of the Xilinx CAM implementation, it is
basically
an SRL-16 that gets reloaded when you write the CAM. Reads are the same
as if
the SRL16 was just a LUT. If your character set reference is not
changing, then a
LUT will serve the exact same function with possibly less overhead (the
CAM needs
a full decode on the match to handle all possibilities).
Seth wrote:
> Has anyone used Content Addressable Memory to perform string matching?
>
> I don't know much of anything about CAM, but I can imagine it would be
> much more flexible than hard-coding the strings I want to search for.
> However, will there be a huge hit in speed? I realize they can be
> read in 1 clk, but will the max speed of the FPGA take a hit?
>
> I don't suppose there are coded examples out there?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58751I could have emailed this directly to Peter, but I thought it might be useful to others. I have a socket on my board which requires 5 volt tolerance on a number of pins. It also has to be reasonably low power meaning I can't power a high current surge on power up. The part I currently have selected is the Altera EP1K30 which seems to do everything I need and should live with my 200 mA power on surge limitation. But all the other parts on the board can be Xilinx. So I would like to find a Xilinx alternative for this socket. In the Xilinx camp I have considered a couple of devices which are 5 volt tolerant. Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part. SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only. Spartan2 - 2.5 volt, very high power, block RAM, current part. Is this a correct summary? Are there any parts that I have not listed that I should consider? I have been given a very good price on the Coolrunner XCR3512XL, but even with 512 macrocells, including small FIFOs (8 bits x 16 words, two FIFOs) uses up half the chip. The Spartan 2 is not an option due to the startup power. If I am willing to work with the SpartanXL and I can get a good price on it, I could put that on the board. I am not crazy about having to use older, not so well supported tools. Having to use a different tool is the only real reason to not use the Altera part. What tools are available exactly? If I don't buy a third party VHDL synthesis tool, is there something equivalent to XST in the older "Classic" tools? Are the "Classic" tools "paid for" only? Any other chip family alternatives? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58752
I thought this was discussed in a thread here, but I can't find it even with Google Groups. Anyone have the skinny on what version will support the XC3S400 and when that is likely to be out? Hmmm... maybe I should search my email instead of here. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58753
I've written an open source tool to look at a gate level netlist and find all crossings between clock domains. I've also added a few other options to the tool to report information like what clocks are associated with each input and output, whether any signals that tie into flop set/reset pins are also feeding into flop D inputs, and some ability to trace all paths from one flop to another. For now, the tool just reads an Altera EQN format netlist, but I hope to add other netlist formats. I'm calling the tool Logic Investigator, or 'li' - a google search didn't come up with anyone else using that name yet... It's written as a perl script that reads the netlist, then presents a 'shell prompt' where the user can enter commands to run specific reports/checks. I polished this tool for public use for several reasons: - general contribution to the design community - productive use of time in between jobs - self-promotion (I am available for consulting on designs) I mention these reasons because I want to encourage other designers/verifiers that are between jobs to consider making their own contributions to such open source work. Logic Investigator is free at my web site: http://asics.chuckbenz.com (which also has other stuff such as my open source 8b/10b design, another tool, and some writings I've done about logic design). I will be maintaining updates there as well. \chuck benzArticle: 58754
Hi, Marc Guardiani wrote: > Since you're doing schematics with tristate buffers in them, you need to > consider a bug in 5.x that will not be fixed until 6.1i. Iterated > instances of IOBUFs and BUFTs are processed incorrectly. A dummy net is > created then not connected to the buffer. The only work-around is to > hand edit the HDL output of the synthesized schematic. > > Thanks for your reply, it confirms there are troubles with tri-states buffers, and I'll stay away from iterated BUFT/BUFE symbols. however, I'm not using iterated symbols (I use BUFE8 / BUFE16, I don't think they are treated like iterated BUFE, but I might be wrong) and looking at the HDL output ".vhf" file, everything seems ok. Also in my application, there are other tri-state busses that are ok, and only the 2 having the most sources have a problem. This thus seems to be a different problem/bug, with somewhat similar symptoms. Looking at the busses that splitted in the RTL schematic viewer, I noticed that the "lost" half of them is named _n[4 digits number], such as: _n0131 Another strange case is a 8 bits bus that kept it's original name on 7 of it's signals and got a _n0145(3) assigned to it's fourth line for no apparent reason. --- I was wondering if there are "rules" when using these buffers, such as a maximum number of sources per bus line, not mixing bus widths (I have some sources that are 16 bits, some that are 8 bits, should the remaining 8 bits be connected to BUFE with their input tied to GND ?), having all connections to the bus in a single sheet (they are 6 in my top level diagram), buffer placement issues or other rules derived from people's experience designing with tri-state buffers in Xilinx devices. --- Finally, are tri-state buffers so poorly supported that using multiplexers is the way to go ? I must admit I don't like the idea of adding so many levels of logic in my signal path and it defeats the whole purpose of having a bus, but if that's the only way out ... Still trying to sort it out, any help appreciated ... Eric.Article: 58755
HI, I also get into this problem. I can only add area_group to mostly logic to let the critical logic to be able to be mapped to the specific area. Hope to get easier way. Regards, seyiorArticle: 58756
When I was in the situation of needing to teach myself VHDL from scratch, I looked for a book first. After I bought one and installed the Xilinx Web Pack, I found that this was packed with far more useful examples than the non-cheap book. Personally I find it easier to learn by looking at examples than ploughing through someone's explanation. And I already had a hardware with software background, which helped a lot.Article: 58757
> > "There is probably no reason to use global buffers for any of the QCM inputs. > If you are just measuring their frequencies, each QCM input is probably only > driving a single counter, which is then sampled into the system clock > domain. Since each QCM load is small, you don't need a global buffer. You > just need one for the system clock." > -Kevin Hi Kevin, Thanks for the response. Actually i have another clock input which operate at 1KHz, this clock will to to counter which will then produce pulse every 1s. This pulse will to each of the QCM counter. Once the QCM counter detected this pulse it will latch the measured frequency of the QCM. So do i need to put Global buffers for this 1KHz clock input and just use normal buffer for 8 of the QCM clock input ? regards emiliaArticle: 58758
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F2923F5.32975097@yahoo.com... > Prasanna wrote: (snip) > > Lets say, you do a complex logic such as a CRC and find that your > > final CRC evaluation takes more than one clock cycle (based on byte > > enables) and cannot meet the speed requirements. You can pipeline the > > data and calculate final CRC in multiple clock cycles. > > This is exactly what multicycle is not. If you allowed the CRC > calculation to have two or three clock cycles for the logic delays to > settle out and used an enable on the register at the end, that would be > a multicycle path. This requires a separate multicycle timing spec > since otherwise the tool will try to optimize this to get it to run in > one clock cycle. If you add pipeline registers, then each stage will > need to be done in a single clock cycle and will definitely *not* be > multicycle. In an FPGA the register is pretty much free (in most architectures, anyway) so you probably should pipeline it. -- glenArticle: 58759
Rick,
I do not know if are aware about the new Lattice devices. In what
is called ispXP technology Lattice offers a CPLD architecture with the
option of using some of the Multi Function Blocks as Memory (FIFO,
Dual Port RAM, Pseudo Dual Port RAM).
The software is free from the Lattice website
(www.latticesemi.com) that comes with Synlify and Leonardo Spectrum as
synthesis tool.
This device is 5V tolerant and there is no "power surge"
problems.
Regards,
Paul,
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F29C212.EC74896B@yahoo.com>...
> I could have emailed this directly to Peter, but I thought it might be
> useful to others. I have a socket on my board which requires 5 volt
> tolerance on a number of pins. It also has to be reasonably low power
> meaning I can't power a high current surge on power up. The part I
> currently have selected is the Altera EP1K30 which seems to do
> everything I need and should live with my 200 mA power on surge
> limitation. But all the other parts on the board can be Xilinx. So I
> would like to find a Xilinx alternative for this socket.
>
> In the Xilinx camp I have considered a couple of devices which are 5
> volt tolerant.
>
> Coolrunner - XCR3512XL - 3.3 volt, very low power, no RAM, current part.
> SpartanXL - 3.3 volt, low power, distributed RAM only, old tools only.
> Spartan2 - 2.5 volt, very high power, block RAM, current part.
>
> Is this a correct summary? Are there any parts that I have not listed
> that I should consider?
>
> I have been given a very good price on the Coolrunner XCR3512XL, but
> even with 512 macrocells, including small FIFOs (8 bits x 16 words, two
> FIFOs) uses up half the chip.
>
> The Spartan 2 is not an option due to the startup power.
>
> If I am willing to work with the SpartanXL and I can get a good price on
> it, I could put that on the board. I am not crazy about having to use
> older, not so well supported tools. Having to use a different tool is
> the only real reason to not use the Altera part. What tools are
> available exactly? If I don't buy a third party VHDL synthesis tool, is
> there something equivalent to XST in the older "Classic" tools? Are the
> "Classic" tools "paid for" only?
>
> Any other chip family alternatives?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 58760Hi I do not have expirience in Xilinx hardware and did not find (in DS, XAPP139, XAPP151) answer for the following questions: 1) does IMPACT (or other tool in ISE5) allow access to configuration registers (or issue JTAG comands like in figure 23 in XAPP151)? Is there any tool that allow to insert user comands in bitstream, or tool similar to IMPACT but more powerfull (compatible with Cable III)? 2) for full reconfiguration: Can one issue "shutdown sequence" (using JTAG) instead of reseting FPGA via PROGRAM pin? If "yes" what commands should be given to bitgen/impact or another tool? May be I made mistake in system design, but access to PROGRAM pin is dificult and I wish clear configuration memory (if posible) by JTAG comand. 3) partial reconfiguration (may be I'll need it late): Is there any "practical" example that explain how one should prepare and download "main" bitstream and "overlay" bitstream (suggesting that design rules for project are sutisfied)? I am sorry if the message was posted several times (i've tried several to post different ways). Thanks. Sergey.Article: 58761
Andrew Paule wrote: > Thad - > > sounds good in theory - but there has never been a 12 bit DAC with 12 > bits of reality - the LSB is junk with power supply noise and > non-linearity. The 12 bit DACs are really capable of 11 - 11.3 bits > with GOOD (excellent) gound planes and linear regulators and a cold > plate for temperature stability. For this application, the OP has error feedback, which removes the need for long term stability, accuracy, and good linearity. Noise would be more of a problem, though. > The phase error means that his load into the m and n integer will not do > well in this application - they only increment on cross. The m and n integer? What do you mean here? ThadArticle: 58762
Robert Scott wrote: > On Wed, 30 Jul 2003 19:45:56 -0600, Thad Smith <ThadSmith@acm.org> > wrote: >>I'm following up my own post for a correction. >> >> >>>Assuming that the DAC is updated once each cycle of the output >>>frequency, you want your frequency to be within f (1 +- 1/3600), which >>>would generate the maximum phase error, assuming that the phase was >>>exactly matched at the beginning. That suggests that you want at least >>>a 12-bit converter. >> >>12 bits should be sufficient for the full scale frequency. Since the OP said he needed to >>track 1 to 50 Hz with 0.1 degree max phase error, he will need an additional 6 bits to get >>the required resolution at the low end (1 Hz). > > > Not true. The OP quoted the phase error spec in terms of degrees, not > microseconds. .1 deg is 1 out of 3600 at any frequency. So 12 bits > (which gives 1 out of 4096) is good enough at any frequency. Yes, one part in 4096 gives sufficient resolution, but assuming that he uses 12 bits to achieve the span 0 to 50 Hz, at the minimum frequency of 1 Hz, his relative resolution is 1/50 of what is available at 50 Hz. Hence he needs more bits for the same relative resolution at the low end. There are other ways of handling it, such as a non-linear transformation. ThadArticle: 58763
"louis lin" <n2684172@ms17.hinet.net> news:bgb60i$lem@netnews.hinet.net... : : > Subject: RAM reset question - Xilinx Virtex : > From: "Jamie Sanderson" <jamie@nortelnetworks.com> : > Date: Fri, 26 Jan 2001 11:39:30 -0500 : : >Since Virtex came out, Xilinx has been recommending against use of the : >global reset logic. I'm wondering now if that doesn't affect initialisation : >of memory components. If I do require my memories to be re-initialised, : >could I simply hook up my reset line to a manually instantiated startup : >block, without changing any of my other logic? Or is it an all or nothing : >decision? : > : >Your input is appreciated! : > : I read the above article in archive of this NG. I think : the "global reset logic" meaned GSR. : But I didn't find any offcial document about the GSR usage from Xilinx. : OK, I found it. Some description about GSR usage in Vertex. http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=67 13 : "rickman" <spamgoeshere4@yahoo.com> news:3F27FFBD.12C17DA0@yahoo.com... : : : : I don't think anyone has said that the global reset should not be used. : : I belive the issue is that because of its slow propagation delay, it can : : not guarantee a clean exit from reset. That is, it can't guarantee a : : clean exit unless you do some thinking about your design. : : : : For example, if you use FSMs, the initial transition should depend on an : : external signal or some other delayed reset. That way you can be sure : : that the reset has been removed from all FFs in the FSM and they will : : not startup out of sync. : : : : In essence, any part of your design that can get out of kilter if the : : reset ends on different clock cycles should be synchronized using some : : other signal. You can think of this as a post-reset enable signal. : : : : -- : : : : Rick "rickman" Collins : : : : rick.collins@XYarius.com : : Ignore the reply address. To email me use the above address with the XY : : removed. : : : : Arius - A Signal Processing Solutions Company : : Specializing in DSP and FPGA design URL http://www.arius.com : : 4 King Ave 301-682-7772 Voice : : Frederick, MD 21701-3110 301-682-7666 FAX : :Article: 58764
erik.coenders@philips.com (Erik Coenders) wrote in message news:<f5fc2c9a.0307310717.4d340e4a@posting.google.com>... > Hi, > > As a study for a project I need to investigate the possibility of > implementing a tiny TCP/IP stack and tiny MAC controller on FPGA. This > stack is capable to transfer some data packets directly into S(D)RAM > without help of the microcontroller. Thus a simple communication via > Ethernet from the desktop PC is required for download/upload to/from > the memory. > > The FPGA board is attached to an Ethernet PHY device such as DP83847A. > In this case a MAC controller was implemented in FPGA but the FPGA > utilitization is too high. There is less room available for other > blocks. My intention is to build a small TCP/IP stack and MAC blocks > in the FPGA and the transaction between FPGA/Ethernet PHY and the > desktop PC has to kept as simple as possible. Thus no heavy/extensive > protocol is needed. > > The questions raised are: > 1. What is the minimum TCP/IP function set required to do simple file > transfer and etc.? you may investigate TCP/IP stacks implemented on very small microcontroller AVR, PIC, I guess some those are already 'stripped down' to the minimum required :) > 2. Is it possible to perform all tasks only in FPGA without help of > the microprocessor? impossible are only things we have not done (because we had fear we could succeed) a plain FPGA implementation is sure possible, question is how reasonable. it would be probably more elegant to design a special purpose 'control-engine' lets do not call it a microprocessor, and implement all possible tasks in the software for that special processing unit. this would allow all that things that take valuable FPGA space to be placed in external RAM :) one funny example of this kinda thing is a possible implementation of USB device by 'inserting' a AT90S2313 AVR RISC Core (free vhdl) and 100% USB software stack into FPGA, the resulting gate cound is a bit more than plain USB core, but hence you have USB function and a free microcontroller, and that micro was not design for USB so in your case you should do in FGPA hw only things a 'processor' can not handle, that is maybe only serdes. I think scenix ubicom has a almost 100% software etherner (except serdes) > 3. Are there any resources (VHDL code and C program on PC) available > on this topic? 1) get opencores ehternet mac (2,600 virtex slice, 100,000+ gates) and start stripping it down :) well at least its a starting point > I will welcome all comments and suggestions. please feel free to write > us at erik.coenders@philips.com Thank you all.Article: 58765
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F29C811.5B21458E@yahoo.com>... > I thought this was discussed in a thread here, but I can't find it even > with Google Groups. Anyone have the skinny on what version will support > the XC3S400 and when that is likely to be out? > > Hmmm... maybe I should search my email instead of here. hmmm, I would say no-one knows or at least is allowed to say in public. it has been said that information has been given that next version(s) will support larger Spartan III and V2Pro VP7 at least, but dont expect to get deadline dates for releases (until its finally released). anttiArticle: 58766
> I can't say anything about distribution in Europe. But here in > Maryland, I can not complain at all about the level of support and > cooperation I am getting on both pricing and technical issues. > > I do find however, that it often requires meeting the sales people face > to face and letting them in on your hopes, plans and fears. You don't > have to give away the company jewels in terms of detail. But the > vendors need a certain amount of information from you to be able to go > back to the manufacturers and get the pricing you want. > > I just made a decision to use the Spartan 3 in my current design because > my Nuhorizons sales person did not give up on me and brought in the > local sales rep who had enough pull with Xilinx to get me the price I > needed. > > I understand that engineers are loath to "play the game", but it is not > really a hard game to play. Basically you need to give up your > expectations of getting an immediate answer to pricing requests and keep > working it until they give you what you need (assuming it is > reasonable). It also does not hurt to have competitive bids on similar > parts :). BTW, my pricing is at 100 pieces (or maybe 250). That is how it should be, and that is how I work together for example with the distributor I buy my oscillators from. (In my case the oscillators cost twice as much as the FPGA :-) Or with my board manufacturer. But apparently the distributors who make 90% their FPGA revenue with three customers figured that they are better of if they not talk to small customers. They sell me chips if they are in stock. At a high price. But that's all. No support, no discussion about the price. Another anekdote: Insight forced me to buy two complete lots of 24 -I needed 30 - because breaking up a lot alledgedly was to much hassle and than delivered three lots of 15, 10 and 23. Kolja SulimmaArticle: 58767
> I thought this was discussed in a thread here, but I can't find it even > with Google Groups. Anyone have the skinny on what version will support > the XC3S400 and when that is likely to be out? I asked the original question. If I remember correctly it is 6.1 and will be released in September.Article: 58768
Tom Seim <soar2morrow@yahoo.com> wrote in message news:6c71b322.0307311617.14f09f6e@posting.google.com... > I have inherited a project developed with Handle-C. My initial > impressions of the language are good. Handle-C has a well thought out > development environment which includes a debugger that supports > parallel execution of statements (the debugger identifies all > statements that will execute each clock cycle). Previous threads on > this subject have raised doubts about turning programmers into > engineers (I am an engineer), but I think this misses the point. > Developers aren't likely to pay $25K for Handle-C to design a UART, > although you could. Most likely they are interested in a problem that > is much more complex. In our case it involves real-time image > processing of two cameras attached to FRET confocal microscope. A > Xilinx XC2V6000 does image coadding, distortion correction and > registration. The code runs for a couple hundred pages. Have you > looked at VHDL code for a simple counter? in C count_val++ in VHDL count_val <= count_val + 1; ? > The best (short) response I > found in favor of this kind of tool is that it manages complexity. > > I don't have enough experience to judge how much more logic would be > required to implement an algorithm in Handle-C versus VHDL, if any. I > do believe that you can significantly reduce development time. I think they're targeting it at faster development where the cost/performance ratio of the results isn't critical. How many of your product do you have to sell before the price of a XC2V6000 becomes a limiting factor? It would be interesting to see a comparison of the devices needed to implement a fairly complex function (SDH/Sonet TU11 -> STM1 device) when designed in HandelC and an HDL, and the corresponding development times. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 58769
Hello all, I would like to reuse a 14 inch TFT screen of a IBM T21 laptop, this LCD panel is a HT14X14-101. But I can't find any information about the pinout of the connector, or what protocol I should use to drive this screen. Can anyone give me information on how to use this kind of screen? Thanks in advance. Kind regards, YvesArticle: 58770
Hi, My application requires a lot of core but few physical i/o lines. Can anyone suggest a modern fpga that is delivered in a 68-pin plcc and/or 80-pin pqfp package? Thanks, RobArticle: 58771
Kolja, I'll buy this statement about distribution. Larger companies seem to completely forget that one successful design can propel a garage start-up into a megalith. Or so we all keep hoping. :) Sales sections in large distribution companies only bother with existing large clients, because it's what pays immediately. This is very myopic thinking but that's the nature of sales. If they're having a slow day they still won't do your quote, being more inclined to spend their time plotting how to steal more major customers from the opposition instead. I'll tell you something else about this game - manufacturers, are you listening? - is that a distributor that doesn't keep stock of common component families doesn't deserve to be a distributor. That rule alone would exclude every major electronics supplier here in Australia. If I have to wait three months for parts, why the hell can't I buy them direct across the 'net? And before anyone screams about how hard it is to do web commerce, I'd like to point out that I worked on a project to convert an international employment agency to a totally web-based business, and it wasn't really that hard. Think M*np*w*r. Rob Kolja Sulimma wrote: > > Peter Alfke <peter@xilinx.com> wrote in message news:<3F1F1F1A.C5C50F9E@xilinx.com>... > > Your question can best be answered by a Xilinx salesperson, or most > > likely a Sales Representative. If they cannot get you the answer > > dirctly, they contact the factory. > > They will love to talk to you and give you a quote with "budgetary > > figures". They really are your friend, because they have a vested > > interest to make you succeed. That is the only way they will get paid. > > Peter, > unfortunately this is not entirely correct. > You are right if you talk about small companies talking to small > distributors or large companies talking to large distributors. > But if you are a small company talking to a large distributor - and > xilinx uses only the largest distributors - than the distributor is > your enemy. > At least I had the feeling during my last couple of calls to > distributors. > > A few weeks ago I send out a request for quotes for 100 pieves XC2S200 > to all european xilinx distributors and got a single response! > > When XC2S was really new I asked Xilinx UK for samples. They did a > search in some stock database an pointed me to Insight Munich who had > a few parts in stock. But Insight simply denied that. "No Stock" was > their answer. After calling three people at Xilinx in three countries > and calling insight again and again finally sample stock magically > apeared in munich exactly in the quantity that Xilinx hat told me. > > Please Xilinx: > Hire some small, independant distributor in europe that is willing to > talk to people who place orders that are worth just a few thousand > dollars. > > To answer the original question: > For quantities below 100 the prices never dropped in the past by more > than a few percent. But there appeared new parts that are cheaper. > > Kolja SulimmaArticle: 58772
Hi Folks, I am running a load of simulations using vsimsa (Active-HDL 5.2). Problem is that the .mgf files within the designs grow with every unique simulation (there are a lot of them) - some of the mgf files have grown to almost 1GB in size and since I have multiple designs, I am getting disk space issues and simulation failures at 3am. Is there any way to prevent the .mgf files from growing each time? I have looked at the vsimsa docs and config files extensively but cannot see any option that might do this. Alternatively - how about simply getting vsimsa to clear the simulation data? The adel command does not seem to do this and manually deleting the mgf files leads to error messages. I know about the "clearlibrary" macro command that works within avhdl but this cannot be used directly from within a vsimsa script. I could get vsimsa to execute a system command that runs avhdl up in batch mode with a script to execute the clearlibrary command but this is slow and less than ideal. So, any ways to clear the simulation data/delete the mgf files from within vsimsa (or prevent mgf file growth)? Thanks very much for your time, KenArticle: 58773
I have a design (admittedly making heavy use of the device resources) which successfully fits into an XC9536 but not an XC9536XL. This is something I hadn't anticipated when migrating to the newer part. Is this to be expected, and is it likely that by tweaking any fitter options (or otherwise) I will be able to get the design to fit ? I am using Xilinx Foundation F4.2i, Build 3.1.196. Richard. http://www.rtrussell.co.uk/Article: 58774
Hi all
I am running a project that has to use "embedded ROM" of ALTERA
APEX20KE to execute code. With the aid of MegaWizard in Quartus, I
select LPM_ROM megafunction and specify an intel hex file for ROM
initialization. ROM is used as a black box in Synplify. Finally Quartus
uses the netlist to place and route.
If I modify code in "embedded ROM", the whole project has to be
complied again and it takes about 40 minutes. I wonder if anybody knows
is it possible to "manually" modify SOF file or POF file without
compiling the whole project? Instead I know I can modify my APEX20KE
prototype by adding external rom. Hope that's not the final solution.
Thanks a lot
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