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We sell low cost FPGA boards. Check them out at http://www.associatedpro.com p52mofej@uco.es wrote: > Where could I find information to make an experimental board for FPGA? > Thanks. > > -- > Jose Moreno > p52mofej@uco.es > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 13076
On Fri, 13 Nov 1998 11:19:08 GMT, thor@sm.luth.se_SPAM_ME_NOT (Jonas Thor) wrote: >It is possible to write structural VHDL with RLOCs for the XC6200 >device. You can use a tool called VELAB that translates your VHDL to >EDIF. However to my knowledge there is no such tool for the other >Xilinx devices.... which is the problem in this case... i think velab may be the only option for the 6200, but it's not difficult to RLOC the other families - i personally use exemplar to do this, targetting 4k/spartan (and, of course, i don't have to write structural-only code, as is the case with velab). all you need is a synthesiser which supports user-defined attributes (BTW, this rules out FPGA express), and which outputs them as properties in the edif. exemplar's tools do this and, for all i know, lots of others may do it as well. incidentally, this gives you as much (or more?) control over your netlist as you would get with schematic entry. exemplar does have a bug which means that your first example wont work (P4742/P4743, for anyone who wants to mail them to remind them how important it is). this is unfortunate, since it means that generates aren't particularly useful, but you can get around it. evanArticle: 13077
i've got a project where i'm looking at using CPLDs from either Altera or Xilinx. it looks like they both have chips that will fit the bill. my question, however, is what're the relative pros and cons of Xilinx Foundation vs. Altera Max Plus? what's easier to learn? what will serve me better in the future? thanks, glenn k.Article: 13078
i've got a project where i'm looking at using CPLDs from either Altera or Xilinx. it looks like they both have chips that will fit the bill. my question, however, is what're the relative pros and cons of Xilinx Foundation vs. Altera Max Plus? what's easier to learn? what will serve me better in the future? thanks, glenn k.Article: 13079
Does this mean that VHDL allows the formation of arbitrary attribute
strings? Using your example:
ATTRIBUTE u_set : STRING;
ATTRIBUTE u_set of u1 : LABEL IS foobar;
can I take an incoming integer (or natural?) generic and compose a
string to place in foobar. In other words, if x=25, will something
like this produce a u_set attribute of "SET25":
ATTRIBUTE u_set of u1 : LABEL IS "SET" & x;
I guess there is also some cunning trick to amalgamate strings into
attributes. Does this work:
ATTRIBUTE u_set of u1 : LABEL IS "SET" & "25";
However, if you had a big array of sub-circuits, it could be pretty
tedious forming the array "0", "1", .... "999".
"Edward Moore" writes:
> Philip Freidin writes
> > Edward Moore writes:
> >> etc, etc..
> >>4. Contrary to popular belief, structured hierarchical relative
> >>placement is possible with VHDL too. In fact it's easier and quicker.
> >>Edward Moore
> >
> >This is an amazing (to me at least) claim. Please give an example of how
> >you do structured hierarchical relative placement in VHDL.
> >
> >Philip Freidin
> >
>
> Sorry about the delay in replying to everyone. Where do i begin ?. Well,
> firstly I don't think this is anything new. It is the mechanism used by
> Exemplar Leonardo to generate what they call 'modgens' (carry chains and
> ram blocks), which are created internally in VHDL (even for Verilog
> synthesis). Other examples can be found in the vhdl source directories
> for Xilinx LogiBlox.
>
> I should have left out the last comment in my orignal post about it
> being quicker and easier in VHDL. It is once you have done all of the
> ground work in creating parameterizable VHDL code, but thats not much
> use to the original postee, who probably needed a quick fix, and was
> using Verilg-XL anyway. (which i have absoloutely no experience with, so
> the following may not be possible in Verilog, and perhaps that's why
> Examplar use VHDL internally).
>
> Relative placement in VHDL requires the following:
>
> 1. 'Black box' VHDL components (similar to schematic symbols) for the
> Xilinx primitives, ie FD, LD, CY4, FMAP, HMAP, CY4, CY4_1-49 etc etc.
> Also create underlying simulation models for all of these.
>
> 2. The ability to pass attributes to these components so they will
> appear in the XNF file, ie RLOC, HU_SET or U_SET, CYMODE etc. For
> Leonardo, this kind of thing is done using:
>
> ATTRIBUTE u_set : STRING;
> ATTRIBUTE u_set of u1 : LABEL IS "whatever";
>
> 3. The ability to pass STRING's (for U_SETs) and INTEGERs (for RLOCs)
> down through the VHDL hierarchy using GENERICs. I am told that this may
> not be possible with some synthesizers, which only implement a small
> sub-set of the VHDL language.
>
> Structures created using this method can be parameterizable (is that a
> real word?). A high level ram block can be passed:
>
> GENERIC MAP(
> width => 16,
> depth => 128,
> use_tristates => TRUE, -- as opposed to muxes'
> x_rloc => 0,
> y_rloc => 0,
> huset_name => "my_ram_block" )
>
> Or you could have a high level CORDIC rotator component with
> parameterized precision and pipeline delay.
>
> Either the same huset_name is passed to several components with varying
> x and y rloc's, or a unique huset name is passed to each instantiation
> of the top-level block.
>
> I hope this makes things a little clearer; the fine details can be
> figured out for yourselves. (This stuff takes time to write, and I am a
> litle uneasy about posting large sections of our source code).
>
> All of this stuff was created a few years back when the synthesizers and
> Xilinx M1 tools were not so good, and we were worried that inferred
> designs wouldn't run at the required 75 MHz. Ironically, since the tools
> have improved so much relative placement is required less and less, and
> our top-level entity often has the following line:
>
> CONSTANT use_rlocs : FALSE; -- let M1 choose placement
>
> --
> Edward Moore
> Not speaking officially for Snell & Willcox Ltd.
>
--
Simon
Article: 13080<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> Hey Jo . <BR>What's up ? <BR>Just about three hours ago I met a girl at the Good bar pub . <BR>She learn physiotherapy at the Be'er sheva (?) university , <BR>for the second or third year . Her name is Reut . <BR>She seems to be cute girl , even though I don't really remember <BR>since I was pretty drunk . <P>please say Hi to her if you happen to see her <P>Thanks <BR> Noam</HTML>Article: 13081
> > The libraries for use with Viewdraw and ViewSim are available on the CD > with your vendors place and route software. Not in the Xilinx 'Design Environment Foundation Series 1.5' CD...at least I can't find them there. Austin Franklin darkroom@ix.netcom.comArticle: 13082
> > The libraries for use with Viewdraw and ViewSim are available on the CD > > with your vendors place and route software. > > Not in the Xilinx 'Design Environment Foundation Series 1.5' CD...at least > I can't find them there. Xilinx apparently decided to have two separate releases of their software, Foundation and Alliance. The Foundation release does not contain any other vendor libraries, but does contain a Xilinx 'supported' 'complete' design environment. To interface with Viewlogic, you have to use the 'Alliance' series... Austin Franklin darkroom@ix.netcom.comArticle: 13083
On Sun, 15 Nov 98 00:49:34 GMT, Simon@NOTtile.demon.co.uk (Simon
Bacon) wrote:
>Does this mean that VHDL allows the formation of arbitrary attribute
>strings?
yes, in general. the following examples (for a string attribute, from
a test file to generate diagonal component blocks) will simulate, but
you'll have to check if your synthesiser supports them ('i' is a
generate index):
-- (1): use 'image attribute, '93 only
attribute RLOC of INST1: label is "R0" & integer'image(i) &
"C0" & integer'image(i+1);
-- (2): function to convert an integer to a string
attribute RLOC of INST2: label is "R0" & itoa(i) &
"C0" & itoa(i+1);
-- (3): arbitrary function call, returning a string
attribute RLOC of INST3: label is getloc(i);
-- (4): just read the string from a constant array
attribute RLOC of INST4: label is rloc_locs(i);
note that velab doesn't use kosher VHDL syntax (it inserts a generate
index directly into a string), so you occasionally can't use velab
source directly.
evan
Article: 13084
I understand some security schemes use the hard disk 'serial number' stored
in the boot sector of the disk. I need to upgrade my hard disk to a larger
disk, and as such, need to modify the serial number.
Has anyone had any problems using 'debug', as outlined below (that someone
posted to this news group originally), to modify their disk serial number?
C:\>debug
l 0 2 0 1 - load one sector beginning with sector 0 of
drive 2 (C:) into address 0 (of some segment)
e 27 - hex entry mode
DD <SPACE> CC <SPACE> BB <SPACE> AA <RETURN>
d 0 - display to verify results
w 0 2 0 1 - write boot sector back to hard drive
q - quit
Thanks for any help!
El
Article: 13085
Hi:
I have questions about WorkView/IntelliFlow
, my Workview version is 7.31, and design a altera
10K device,
1. Does Workview 7.31 and Maxplus2 8.3 can work
together?
2. If so, how to setup environment, Path, etc.
3. I got a error code 1601 when synthesis, that
say "Unable to set up Altera environment",
how can I resolve this error? It say I must
put directory "altera" within WDIR, and set
PATH to it's bin, I use under statementS in
my autoexec.bat
....
SET PATH=C:\WVOFFICE;C:\MAXPLUS2;%PATH%
....
SET WDIR=C:\WVOFFICE\STANDARD;C:\MAXPLUS2
SET VANTAGE_VSS=C:\WVOFFICE\V
SET VANTAGE_CC=C:\WVOFFICE\CL
SET LM_LICENSE_FILE=C:\WVOFFICE\standard\license.dat
SET QUADBIN=C:\WVOFFICE
SET QUADHOME=C:\WVOFFICE
SET HOME=C:\
SET INCLUDE=C:\WVOFFICE\MSVCNT\INCLUDE
SET LIB=C:\WVOFFICE\MSVCNT\LIB
SET ROOTDIR=C:\WVOFFICE\STANDARD\VCS
SET VCS_HOME=C:\WVOFFICE\STANDARD\VCS
SET TMP=C:\WINDOWS\TEMP\
SET TMPDIR=C:\WINDOWS\TEMP\
SET CYPRESS_DIR=C:\warp
SET ALT_HOME=c:\maxplus2
SET ABEL5DEV=C:\WVOFFICE\STANDARD\LIB5
SET ABEL5DB=C:\WVOFFICE\STANDARD\LIB5\DEVICES
SET MINC_PATH=C:\WVOFFICE
Article: 13086Elron Osafat wrote: > > I understand some security schemes use the hard disk 'serial number' stored > in the boot sector of the disk. I need to upgrade my hard disk to a larger > disk, and as such, need to modify the serial number. > > Has anyone had any problems using 'debug', as outlined below (that someone > posted to this news group originally), to modify their disk serial number? > > C:\>debug > l 0 2 0 1 - load one sector beginning with sector 0 of > drive 2 (C:) into address 0 (of some segment) > e 27 - hex entry mode > DD <SPACE> CC <SPACE> BB <SPACE> AA <RETURN> > d 0 - display to verify results > w 0 2 0 1 - write boot sector back to hard drive > q - quit > > Thanks for any help! > > El I can't verify the details of offset and commands. But I can verify that the process works. I used debug to set several disk drives to the same serial number. I verified the location of the serial number by comparing what I found doing a dir with what I found in memory. On my machine the offset was at 43 hex. Remember that the serial number is binary with the bytes displayed in reverse order. A serial number of 1234-5678 will show up as 78 56 34 12 in debug. In my case I have to work on more than one machine located in different locations. Another valid reason for doing such a modification is when you need to replace the disk drive. However, you can get Xilinx to issue you a new licence file if that is the case, a lot less risk also. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13087
We studied and optimized DES for the Xilinx XC4000 series
with -3 speed grade. Here are our main results:
#pipeline stages Mb/sec CLBs used device
1 99 262 4008
2 184 433 4013
4 403 741 4028
More info is in our SAC '98 paper and in Jens Kaps' thesis,
both of which can be found on our web page at
http://ece.wpi.edu/Research/crypt
Regards,
Christof
***********************************************************************
Christof Paar, Assistant Professor
Cryptography and Information Security (CRIS) Group
ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon: (508) 831 5061 email: christof@ece.wpi.edu
fax: (508) 831 5491 www: http://ee.wpi.edu/People/faculty/cxp.html
***********************************************************************
Article: 13088See my sig at the bottom for something you might like. Simon ======================================== p52mofej@uco.es wrote: >Where could I find information to make an experimental board for FPGA? >Thanks. >Jose Moreno >p52mofej@uco.es Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htmArticle: 13089
On Fri, 13 Nov 1998 19:54:28 GMT, p52mofej@uco.es wrote: > > >Where could I find information to make an experimental board for FPGA? >Thanks. > >-- >Jose Moreno >p52mofej@uco.es > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own Insight Electronics Xilinx FPGA / CPLD and CODEC Demo Boards Developed by ACS, Sarasota, FL see them on the Web at: http://www.acscontrol.com/fpgacpld.htm contact Insight Electronics at: http://www.insightelectronics.com Xilinx FPGA / CPLD Demo Board ----------------------------- Features: Test moderate complexity FPGA / CPLD designs without building a prototype All user I/O pins brought out to labeled 0.1" pin dual-row headers for easy access, expansion 3" x 5" form factor. Xilinx XC9536-VQ44 In System Programmable CPLD 36 Macrocells with 800 usable gates 34 I/O pins available on 40 pin header Xilinx Spartan XCS30-VQ100 FPGA 1368 Logic cells with 30,000 gates 74 I/O pins available on two 40 pin headers Xilinx XC17S30 Serial Configuration PROM (Optional) Installable in socket for external programming Dallas DS1075 Programmable Oscillator 200KHz - 100MHz Installed in socket for external programming Eight User LEDs 2 Red, 2 Orange, 1 Yellow, 1 Green, 1 White, 1 Blue Connected to XC9536 CPLD via 40 pin header Two User Push Button Switches Connected to CPLD 40 pin header JTAG Programming Connector Daisy-chained to both CPLD / FPGA FPGA / CPLD Vcc Jumpers Allows current consumption monitoring D.C. Power and Battery Connectors Supplied with 9VDC wall-mounted transformer Burr Brown REG1117-5v Low Dropout Regulator CODEC Demo Daughter Board ------------------------- Features: Stacks on FPGA/CPLD Demo Board headers for Power and Digital I/O Provides line level and stand-alone audio I/O on standard jacks When used with the Elanix Software provides Draw / Compile / Download DSP capabilities 3" x 4" form factor Burr Brown PCM3000 CODEC 18-bit Monolithic Delta-Sigma ADC and DAC 16 or 18-bit I/O Data Stereo ADC with 64x Oversampling Stereo DAC with 8x Oversampling Digital Filter Digital De-emphasis Digital Attenuation with 256 steps Soft Mute Analog Loop Back Multiple sample rates Atmel AVR AT90S1200 1K In System Programmable Flash memory 64 bytes EEProm 1 MHz operation, most instructions single-cycle Sets CODEC PCM Format, Attenuation Installed in socket for external programming AVR ISP connector provided Microphone Pre-amplifier 3.5mm Monaural Microphone Jack Optional bias power jumper Jumperable to either or both channels Audio Line-Level Input / Output Jacks RCA Phono Jacks Stereo Head Phone Amplifier 3.5mm Stereo Jack -- Steven J. Ackerman, Consultant ACS, Sarasota, FL sja@gte.net http://www.acscontrol.comArticle: 13090
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> Sorry for the last post , <BR>I guess I was really drunk that night . . .</HTML>Article: 13091
15 November, 1998
New and interesting things in the Qualis Library
------------------------------------------------
We've added several new items to the Qualis Library on topics related to
System-on-Chip Verification, Behavioral Synthesis and other informative
briefs and papers. Check them out by clicking on the hotlinks shown below:
1. Attend our Online Seminar on System-on-Chip verification to find out
how successful SoC design teams tackle chip verification. Presented
at this year's IP98 Europe conference just a few weeks ago, you can
attend the Seminar with a RealAudio feed, or simply review the
text transcript.
http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=op002
2. Are you dealing with the cultural change associated with retooling
your company for design reuse? Listen to what industry veterans have
to say about the matter by checking out Dan Scholsky's insightful
article.
http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tt006
3. David Black, our resident "guru" on Behavioral Synthesis, shares
some helpful hints for users of Synopsys' Behavioral Compiler.
Find out how to properly use the Verilog 'disable' statement,
how to bring debug information out of your design at the gate level,
pick up a checklist of common BC traps, and more.
http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=dd006
4. Are you dealing with logic area headaches on your chip or FPGA using
Synopsys DC? Here are a few "survival tricks from the front line"
to help you reach your area goals.
http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=dd005
5. Speaking of logic area, how about an interesting article on estimating
your gate and I/O counts before you start designing?
http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=dd007
As you are probably aware, we have created the Qualis Library as a
opinionated, selective repository for high-quality information about
complex ASIC, SoC and system design issues. Sharing knowledge is an
integral part of the Qualis culture, and the Qualis Library is our
way of giving back to the engineering community. Check it out
and send us your feedback.
We'll keep you posted as new content is added to the Library.
Michael
Article: 13092GSB <brunergs@pcisys.net> wrote in article <01be0e01$4395cec0$1868cad0@none>... > To all on this newsgroup, > > I have a old Atari 8bit computer (1450XLD model) that > uses two 40 pin LSI chips for a good portion of the > memory management and timing. Both of these chips > appear to be prototype. Both are in ceramic packages > with gold cover and pins. The cover is held on by scotch > tape, which when removed exposes the die inside. Neither > chip has even one sort of marking of any kind at all. > > I have manage to trace out the connections to the rest > of the computer to get a idea of some of the signals going > to/from the chips. But I'm at a lost now of wether or not > these are programmable logic array chips. > > My questions are as follows: > > During the 1982-1984 time frame, were there any > programmable logic chips made that came in a 40 > pin package? > > If there was, what companies would have been making > them? > > Could these chips be PAL, GAL, or FPGA? > > I'd appreicate any leads someone could give me to go > by to try and identify these chips. I'm looking to find out > if I can duplicate these chips to preserve this rare Atari > computer that I have. I have an some additonal info to add to this posting. Maybe this can help or maybe not. I did some quick glances thru some databooks by Intel and MMI from around 1981-1984. They did make 40 pin programable logic then (mainly PEEL type of devices). Neither one had chips that came close to matching the VCC and GND pin positions though. Both of these chips that I have, don't have any markings on the outside. I peeled back the covers (only held down by tape) and tooked a look at the die's inside under a microscope. On both I found the initials MHS and a copyright 1982 on them. On one I also found what appears to be part numbers. The numbers were: Z104-71 and 1023. About 85% of the die appeared to to be a fuse array. There were light areas to looked like blown fuses. But the microscope wasn't powerful enough to get down close enough to verify that. Can the MHS possibly be the designers initials or company initials? -- ****************************************************** Glenn Bruner Email: brunergs@pcisys.net Visit my web page of images of rare Atari items http://www.pcisys.net/~brunergs/Atari/ ******************************************************Article: 13093
Hi all, I am trying to programming a XC1701L eprom for my XC4028XL. however, I find out that in the PROM file formatter of M1, there is no device called XC1701L (which is the suggested device for 4028 by xilinx). I've tried to access the software update page in xilinx's site to see if there is any clue but seems nothing related. Does anyone have the same problem ? Thanks a lot. Rgds, OliverArticle: 13094
In article <01be10ec$b4b77200$ce36e6d0@none> "GSB" <brunergs@pcisys.net> writes: >GSB <brunergs@pcisys.net> wrote in article >> To all on this newsgroup, >> I have a old Atari 8bit computer (1450XLD model) that >> uses two 40 pin LSI chips for a good portion of the >> memory management and timing. Both of these chips >> appear to be prototype. Both are in ceramic packages >> with gold cover and pins. The cover is held on by scotch >> tape, which when removed exposes the die inside. Neither >> chip has even one sort of marking of any kind at all. Almost certainly these are ASIC prototypes. Scotch tape and lack of marking are the strong evidence. >> I have manage to trace out the connections to the rest >> of the computer to get a idea of some of the signals going >> to/from the chips. But I'm at a lost now of wether or not >> these are programmable logic array chips. Probably not. >> My questions are as follows: >> During the 1982-1984 time frame, were there any >> programmable logic chips made that came in a 40 >> pin package? In this time frame, MMI was the leader in programmable logic, with AMD just getting started. MMI did do some large parts, but these were not successful. The state of the art at that time was 16, 20 and 24 pin PALs. >> If there was, what companies would have been making >> them? >> Could these chips be PAL, GAL, or FPGA? Too big to be PALs, GALs and FPGAs didn't exist yet. >> I'd appreicate any leads someone could give me to go >> by to try and identify these chips. I'm looking to find out >> if I can duplicate these chips to preserve this rare Atari >> computer that I have. Pray they dont fail. >I have an some additonal info to add to this posting. Maybe >this can help or maybe not. >I did some quick glances thru some databooks by Intel and >MMI from around 1981-1984. They did make 40 pin programable >logic then (mainly PEEL type of devices). Neither one had >chips that came close to matching the VCC and GND pin >positions though. >Both of these chips that I have, don't have any markings on >the outside. I peeled back the covers (only held down by tape) >and tooked a look at the die's inside under a microscope. On both >I found the initials MHS and a copyright 1982 on them. MHS is either the designer's name, or maybe Matra Harris Semiconductor, but I dont think Matra Harris Semi was in business back then. > On one I >also found what appears to be part numbers. The numbers were: >Z104-71 and 1023. Could be anything. >About 85% of the die appeared to to be a fuse array. There were >light areas to looked like blown fuses. You are almost certainly looking at either a mask programmed ROM, or a PLA. If it is a ROM, then you may be able to reverse engineer it by hooking up a logic analyser (be careful you dont short anything, and blow the only chip you have). The ROM might be any one of: boot code, main code, or character ROM for display/graphics. If it is controlling something like a floppy disk, then it is more likely to be a PLA based state machine. > But the microscope wasn't >powerful enough to get down close enough to verify that. >Can the MHS possibly be the designers initials or company initials? See above. Good luck Philip Freidin.Article: 13095
Try some floating point circuits. They are challenging and you will *LEARN* a heck of a lot in modelling! In article <72g0mm$uud$1@nnrp1.dejanews.com>, leslie.yip@asmpt.com wrote: > Hello > > I think that a 16-bit x 16-bit binary multiplier will be quite challenging. > After you implemented your project, would you place on the web site or give me > to have a look? > > Leslie Yip > > In article <3ej22.1081$4S.3996@weber.videotron.net>, > "Stephane Marcouiller" <mars02@gel.usherb.ca> wrote: > > I have to find a suitable VHDL project for my course Computer Architecture > > II > > Suggestions are welcome > > > > Currently I have a couple of ideas like : branch prediction buffer, > > pipelined CPU, L1 et L2 cache,... > > > > Do you have other ideas ? > > > > P.S. It must be possible to do it whitin 3 weeks * 5 hours/week = 15 hours > > approx. > > > > Thx > > > > > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13096
Hi, 1. What are the arguments for and against making a system Big or Small Endian? 2. Isn't Little Endianness somehow "counter-intuitive"? 3. Why are most(all?) RISCs designed to be (primarily) Big Endian? Any references/URLs on the Endianness issue would be welcome. Thanks in advance, --shail bains -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13097
Todd Kline wrote: > Leprechaun wrote: > > > Hi all, > > Recently I am working on a circuit which require 2 Xilinx XC4028XL-1-PG299 > > communication to the same DSP on the same bus. One of the chips is for > > outputting to DSP while the other is for inputting from DSP. To prevent > > crosstalk between the 2 xilinx, I used tristate buffer to control the > > input / output port of the 2 chips. > > The problem is as follows : > > After I downloading the circuit to the 2 chips separately (one after the > > other, instead of in a daisy chain manner), those input/output pins > > would have a value of 1/0, when I connected the 2 ports on the same bus, > > the current goes up 10 times (probably because a '1' pin is connected to > > a '0' pin) and all the pins will have a voltage value around 2 V (0 = 0V, > > 1 = 3.5V). Then, no matter what I do, it cannot restore to normal state > > unless I re-download the circuit. > > > > Did anyone experience similar problem? > > > > Thanks a lot. > > > > Oliver > > 1) Are the tri-state buffers external to the FPGAs or internal? > 2) Can both FPGAs drive the bus or just one FPGA and the DSP? > > Before programming, all user I/Os are tri-stated. After programming > the I/Os are user defined. You almost certainly have multiple active > drivers on the bus driving different values. Double check your tri-state > control logic. If the tri-states are internal, make sure that tri-state > buffers are actually being inserted. > > Todd Hello Do you have a bus master and a bus slave? Is it possible than one fpga is always programming while the other one is ready to work? In this case, may be one fpga interpret the tri-state level of the other fpga as valid signals. Good luck. Michel.Article: 13098
ovilup wrote: > Hello ! > > I am working on an I2C controller. Now, I am designing the > internal clock generator. I have an 1.5 MHz internal clock, > from which I have to generate the 100 KHz, 90 KHz, 44 KHz > 1.5 KHz SCL clocks. > > Any examples of such an clock generator would be appreciated ! > > Thank you in advance. > OL Hello I do not know exactly what it is but I heard about the direct numeric synthesis. It is use in the signal generators to privide a wave of a specific frequency. Bye. Michel.Article: 13099
Loic Lagadec wrote: > Hi > > I'm looking for a survey dealing with the FPGAs' evolution > - density > - cost per function > - reconfiguration time > - speed > > I would be realy pleased to get help from the net. > > Loic Bonjour. You can try www.xilinx.com or www.altera.com for the main ones used in France. Lucent is used in usa, there is Atmel too. And many others .... Their salors in France are Avnet, Compress, Tekelec. Data books are free. Bye. Michel.
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