Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Dave, You will find it VERY difficult to implement a 64 bit PCI interface in an FPGA. All of the current FPGA vendors that offer soft cores had to work very hard to implement a 32 bit version. I a not saying that it can't be done, but the experienec that I have had with target and Initiator/target have not been easy. One potential solution will be a 64 bit 66Mhz core that Lucent will be offering in for its Orca 3C line 1Q98. It will have an embedded PCI core that you could run at 33Mhz and have teh 64 bit wide features. Hope that this helps.. TonyArticle: 7976
Dave, You will find it VERY difficult to implement a 64 bit PCI interface in an FPGA. All of the current FPGA vendors that offer soft cores had to work very hard to implement a 32 bit version. I a not saying that it can't be done, but the experienec that I have had with target and Initiator/target have not been easy. One potential solution will be a 64 bit 66Mhz core that Lucent will be offering in for its Orca 3C line 1Q98. It will have an embedded PCI core that you could run at 33Mhz and have teh 64 bit wide features. Hope that this helps.. TonyArticle: 7977
Oliver WOOD writes: In article <345F44F2.7DBC@mmu.ac.uk> Oliver WOOD <o.wood@mmu.ac.uk> writes: OW> OW> Has anyone found any differences between the timming values seen in the OW> maxplus2 (altera version 8.0) simulator and that of the *.sdo files OW> generated for simulation in a third party simulator. OW> OW> There seems to be a difference of a factor of 2 : OW> eg : 10 ns in maxplus2 simulator .. becomes a 20 ns delay when OW> simulating using the V-system simulator. Oliver, I think this is a known problem, at least I remember an FAE telling me that the VITAL files produced inaccurate timing. If you dump a VHDL model *.vho, which is what I guess you mean by the Maxplus2 simulator files, then the timing is correct. You can use the *.vho file in any third party simulator. I was using version 7.x at the time and so I am surprised that this hasn't been fixed. I can only suggest you contact your Altera apps engineer, or try the web site for information and patches. MarkArticle: 7978
In article <345E2DA1.7FD8@ece.nwu.edu>, Zhi Ye <ye@ece.nwu.edu> wrote:
>Hi,
> I'm going to work on some compiler, the goal is to make a C program
>run on a FPGA integrated system.
have a look at the Altera FLEX series. you can change the configuration while
the system is runnng (well not the whole system of course)
Holger
++
Cut "MIX" out of the email adress when replying to this message.
--
Need a powerfull ICE? Visit http://www.lauterbach.com/
Article: 7979Hi all Could anyone provide info on design techniques used to implement arithmetic division on FPGAs (both LUT and sea-of-gates)? Thanks in advance. Reetinder SidhuArticle: 7980
We are about to design a digital reverberator on the Altera's FPGAs.
The main problem is the big amount of memory requirement (about 50K for a
stereo reverberator with a max sample rate of 48Khz).
Is there anyone who can suggest us a possible solution?
Thank you all
=========================================
Baleani Massimo
mail-to: mass@ascu.unian.it
Universita' Degli Studi Di Ancona
Dipartimento Di Elettronica E Automatica
=========================================
Article: 7981Zhi Ye wrote: > > Hi, > I'm going to work on some compiler, the goal is to make a C program > run on a FPGA integrated system. Have a look at our C-based compiler called Handel-C, it may be just what you want. There will be a free demo copy available soon from our web site, and there is a University Program with special low prices. > As I see it,I have some questions: > 1. What is going on with FPGA integrated system now? Is there any > product ? > (What I mean by 'FPGA integrated system', is some computer with a > CPU and a FPGA, the CPU can dynamicly change the FPGA's function, > ie:when CPU tries to run a MPEG program, the FPGA can be a MPEG > card;when CPU tries to run a JPEG program, the FPGA can then be a JPEG > card.) There are plenty of plug-in cards with FPGAs eg our RC1000-II ISA card. Also look at the following sites for leads: http://www.optimagic.com/ http://www.io.com/~guccione/HW_list.html > 2. How to change the function of a FPGA? How long does it take?Is > there a standard among all the products from different companies? > Assume there is a function library, containing the pre-designed FPGA > configuration file for the functions. I takes of the order of milliseconds or 10s of milliseconds > 3. What language can I use to generate a FPGA design? There seems to > be several choices:VHDL,X-BLOX ? Handel-C!!!!! > 4. How can I know some more about FPGA? > Try the Xilinx web site http://www.xilinx.com Regards, Charles Charles Sweeney, Engineering Director, Embedded Solutions Ltd Tel/fax +44 1235 510456 <http://www.embedded-solutions.ltd.uk/> Email CharlesSweeney@compuserve.com or csweeney@embedded-solutions.ltd.uk 6 Main Road, East Hagbourne, Didcot, Oxfordshire. OX11 9LJ. UK.Article: 7982
Hello reader, i would announce two development boards of Alcatel Telecom. The two boards are useful for ASIC prototyping and simulation. We already used the boards to verify DSP algorithms written in VHDL, to test the behaviour of PLL circuits, to built test equippment (complex signal generators written in VHDL) for our fab and for other applications. Short description of the boards: HW_SIM * 200.000 gates logical resources (4*Altera EPF10K50) (300.000 gates if equpipped with 1EPF10K70) * 2 Slots for SIMM memory modules (30 pin types) * 2 on board oscillators (48,640 MHz, 16,384MHz) * PBA size 233mm*210mm * breadboard area * reset circuit * ... DEV_KIT * 20.000 gates logical resource (2*Altera EPF81188) * on board oscillator (16,384 MHz) * PBA size 233mm*160mm (possible splitting 2 times 100mm*160mm) * breadboard area * reset circuit * ... For more information about the development boards contact one of the persons listed below. Financial Questions: R.Prestin@stgl.sel.alcatel.de Technical Questions: brod@lts.sel.alcatel.de Best regards Lothar Brodbeck p.s. An user wrote: ... We successfully used the HW_SIM development board to verify our complex signal processing algorithm. ... The programming and the handling of the evaluation board stands out. ...Article: 7983
Entry level ASIC Design Engineer, presenting an ideal starting place for entry into this fast-moving and lucrative field. The candidate must have a sound knowledge of digital design techniques, and previous experience with ASIC design would be an advantage. Main responsibilities and skills: * Design of test benches using Verilog HDL for functional verification AND to produce sets of test vectors for production testing. * Liase with technical authoring department in the production of data sheets and programming/technical manuals for new devices. * Later work will include the design of glue logic ASICs for various networking products and sub blocks of our larger projects. * The ability to work to a goal unsupervised and to be able to set your own targets and estimate timescales is essential. * Familiarity with normal ASIC design flows and circuit techniques. * A user level of competence with UNIX would be helpful This is an ideal opportunity for a person who can show commitment to the position, which is a ground level entry into a fast growing company. Initial rewards will be based on ability and the longer term prospects are for a senior position within the company. We are located in Burgess Hill, in the Sussex countryside. For those that prefer a livelier place to live, Brighton is only 15 miles down the A23. Commuting from Brighton is easy by car or train, we are just 10 minutes walk from Burgess Hill station. Send e-mail only to: dmould@network-technology.comArticle: 7984
Dave Blair wrote: > > Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge > along with some additional special functions incorporated into a single > FPGA. Is this possible with any FPGA that is currently available? The most difficult challenge with any 64-bit normal bridge is getting it to handle all the different transfer modes and exception cases without dropping any data. (not a simple feat) Add on top of this all the specific PCI bridge functional requirements, posted writes, delayed reads, primary and secondary busses, upstream and downstream transfers, etc, while maintaining 100% compliance to specifications and you end up with almost an impossible task for today’s FPGA technology given the complexity of the required design. You might be able to reduce the complexity of the design task but you did not state what all your functional requirements are. For example, insight to this would be if your application is a plug device, which needs to operate with all PCI devices and operational modes (the mostly impossible task) or an simpler embedded application that has a reduced functional set and a reduced set of other PCI devices it needs to operate with (only realistic direction). Otherwise, many people use off-the-shelf PCI to PCI bridge chips, which do have the 64-bit to 64-bit functionality you’re looking for, then use an FPGA on the back end. Cary Snyder, NewBUS Corp.Article: 7985
Tony, Thanks for the tip! I have to admit that I wasn't thinking about the Lucent Orca family of parts as a possible solution. I may be able to use two of these parts to do what I need. It looks like the Orca 3C line will be delayed till 2Q98. Regards, Dave --------------------------------------------------------------- | Dave Blair Voice: (801)977-1640 | Principal Engineer Fax: (801)977-1602 | E-Mail: mailto:DBlair@phbtsus.com | Philips Broadcast Television Systems Company | http://www.PhilipsBTS.com | 2300 South Decker Lake Blvd. | Salt Lake City, Ut. 84119 --------------------------------------------------------------- DaveArticle: 7986
Ray Andraka wrote: > > Massimo Baleani wrote: > > > > We are about to design a digital reverberator on the Altera's FPGAs. > > The main problem is the big amount of memory requirement (about 50K for a > > stereo reverberator with a max sample rate of 48Khz). > > Is there anyone who can suggest us a possible solution? > > > > Thank you all > > if you don't want to take all the address lines of chip, using up a lot of io, you might want to look at the nec/hitachi video frame-buffer memories. the look just like a 300+kbyte fifo. real simple to interface to. bob engle embedded solutions rengle@ix.netcom.comArticle: 7987
> Otherwise, many people use off-the-shelf PCI to PCI bridge chips, which > do have the 64-bit to 64-bit functionality you’re looking for, then use > an FPGA on the back end. What are the 64 bit PCI bridge chips that you know of that are commercially available right now? Thanks, Austin Franklin darkroom@ix.netcom.comArticle: 7988
Zhi Ye wrote: > > Hi, > I'm going to work on some compiler, the goal is to make a C program > run on a FPGA integrated system. > As I see it,I have some questions: > 1. What is going on with FPGA integrated system now? Is there any > product ? > (What I mean by 'FPGA integrated system', is some computer with a > CPU and a FPGA, the CPU can dynamicly change the FPGA's function, > ie:when CPU tries to run a MPEG program, the FPGA can be a MPEG > card;when CPU tries to run a JPEG program, the FPGA can then be a JPEG > card.) > 2. How to change the function of a FPGA? How long does it take?Is > there a standard among all the products from different companies? > Assume there is a function library, containing the pre-designed FPGA > configuration file for the functions. > 3. What language can I use to generate a FPGA design? There seems to > be several choices:VHDL,X-BLOX ? > 4. How can I know some more about FPGA? > > Thanks. > > -- > Z. Alex Ye There is quite a bit of research going on in this area. Check out http://fpga.gsfc.nasa.gov This site has links to other related sites. -- Terry L. Graessle Lockheed Martin - Space Mission Systems NASA Code 521/ Microelectronics Systems Branch graessle@vlsi.gsfc.nasa.gov (301) 286-9698Article: 7989
Dave Blair <DBlair@phbtsus.com> wrote in article <345FCC74.ECCD7648@phbtsus.com>... > Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge > along with some additional special functions incorporated into a single > FPGA. Is this possible with any FPGA that is currently available? I know > that there are third party "mega-functions" that are available for 32 > bit PCI interfaces. Has anyone done work on 64 bit versions of these? Is > it possible or practical to incorporate two if these in one FPGA? There is no significant differences between 32 bits PCI and 64 bit PCI except for the extra 32 bits, extra 4 CBEs, PAR64#, REQ64# and ACK64#, all the target and master state machines, configuration space (except notable bits...) etc. is pretty much the same. Though, being a bridge will bring on additional difficulties...depending on what cycles you want to pass through. Since the address is still only 32 bits (except in 64 bit dual address mode...see PCI spec section 3.10.1), you could choose to implement the upper 32 bits of data with external transceivers. What are the special requirements you need that you can't use an off the shelf part....they will be available quite soon, if not already. DEC may have one.. Austin Franklin darkroom@ix.netcom.comArticle: 7990
Massimo Baleani wrote: > > We are about to design a digital reverberator on the Altera's FPGAs. > The main problem is the big amount of memory requirement (about 50K for a > stereo reverberator with a max sample rate of 48Khz). > Is there anyone who can suggest us a possible solution? > > Thank you all > > ========================================= > Baleani Massimo > mail-to: mass@ascu.unian.it > > Universita' Degli Studi Di Ancona > Dipartimento Di Elettronica E Automatica > ========================================= Simple. Hang an SRAM on the FPGA. All of the address and control can be done by a very small amount of logic in the FPGA. Using a single chip, you will get better performance than the worst case times called out in the memory spec sheet due to the light loading on the data lines. A 12ns SRAM will give you better than 40 MHz interleaved read/write performance when coupled with a -2 or -3 Xilinx 4K part. For your 48Khz data rate, you should be able to get away with a nice cheap SRAM. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 7991
>I'm using Protel 2.4. We have got version 3 but are not happy with some of >the changes (although minor). > >As far as a way to develope for Xilinx with schematic based tools, this is >the best I've seen. Protel 2.4 is a really well designed, intuitive tool. Erik, what do you about simulation? AFAIK Protel don't have any good integrated offerings there. They still haven't got around to integrating their latest PCB router into their PCB prog - a year later. Using the old DOS Viewlogic 4, I got by with Viewsim's unit delay simulation perfectly well, and that is all I need, no need for post-route sims. With Viewsim, I like the way one can highlight some signals in the sch and open a Viewsim window, and just run it. Or, for big projects which may have to be revisited years in the future, one can do everything with script files. I am basically looking for sch tools which I can use for both PCB and FPGA design. Actually I have been using Orcad SDT/386 for PCB sch and Protel PCB 2.8 for the PCB, but SDT/386 (being DOS) has almost the same hassles for me as Viewlogic 4 (except it is not dongled!), and I prefer Protel's sch to Orcad's sch. OTOH Orcad do have a simulator... I know there are some cheap FPGA tools, and most probably they will get cheaper and cheaper. But I am reliably advised that Foundation is crap (compared to my Viewlogic+XACT6) and these cheapo tools tend to disappear (support-wise) after a short time. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 7992
Ray Andraka <no_spam_randraka@ids.net> writes:
>Massimo Baleani wrote:
>>
>> We are about to design a digital reverberator on the Altera's FPGAs.
>> The main problem is the big amount of memory requirement (about 50K for a
>> stereo reverberator with a max sample rate of 48Khz).
>> Is there anyone who can suggest us a possible solution?
>>
>> Thank you all
>>
>> =========================================
>> Baleani Massimo
>> mail-to: mass@ascu.unian.it
>>
>> Universita' Degli Studi Di Ancona
>> Dipartimento Di Elettronica E Automatica
>> =========================================
>Simple. Hang an SRAM on the FPGA. All of the address and control can
>be done by a very small amount of logic in the FPGA. Using a single
>chip, you will get better performance than the worst case times called
>out in the memory spec sheet due to the light loading on the data
>lines. A 12ns SRAM will give you better than 40 MHz interleaved
>read/write performance when coupled with a -2 or -3 Xilinx 4K part. For
>your 48Khz data rate, you should be able to get away with a nice cheap
>SRAM.
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930 Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
Even better, use DRAM. You could put a huge SIMM (say 16 megs!)
and it'll be real cheap. You could do some nice, long reverberators
and simulate much better impulse responses. Some long reverbs last
longer than 4-6 seconds.
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 7993Has anyone out there come across and schematic or VHDL description of implementing SPI in a FPGA? We are trying to implement in a Xilinx 5200 FPGA, and want to embed SPI interface internally. Any help would be greatly appreciated. Gus Anderson gcanderson@aol.comArticle: 7994
Darxus <darxus@monet.op.net> wrote:
[snip]
:Any and all information you can give me on where I can get this stuff, how
:much this technology will cost me, how much power I can get for this cost
:(I'm looking for around $500 ?), and what I can do with it -- and how I
:can learn how to do what I can do with it, will be most greatly
:appreciated.
:
Xilinx are running a promotion just now, called "Foundation". Afaik,
the base kit is around $150, and will give you enough tools to get
started, using an in-built schematic editor. To add VHDL capability
ups the cost to around $700 (Australian prices).
Xilinx are good for development work, as they are RAM based, so you
don't need any costly programming kit. The kits mentioned include a
serial download cable, but it's quite easy to do yourself (there's one
on my website, using the JTAG port).
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7995Austin Franklin wrote: > > What are the 64 bit PCI bridge chips that you know of that are commercially > available right now? > Hi Austin, I know that Digital is actually shipping 64-bit products and has data sheets available. Galileo Technology has announced the GT-64120 which is billed as a system controller and not a bridge. Its data sheet is only available under NDA. Sun has its Advanced PCI Bridge or SME2411, which is a 66 MHz, 32-bit PCI-to-PCI bridge chip that two 32-bit, 5 V or 3.3 V, PCI buses (each running up to 33 MHz), on the secondary interface. Other companies are working on various 64-bit solutions including bridges but they aren’t shipping as far as I know. Some of the PCI core company's (for ASIC's) have various 64-bit PCI solutions but the I understand that a fully compliant 64-Bit bridge core might not be a standard product. Last time I checked all the 32/64 bit bridge cores were priced > $200 as its complexity, volume and heavy support require a the higher "fair price". The following are web pages for these devices: Data Sheets for Digital Equipment Corporation second-generation 64-bit PCI-to-PCI bridge chip called the 21154 and the 21554 are at its web page: http://ftp.europe.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html#bridges The Data Sheet for Galileo Technology’s GT-64120, the industry's first system controller to offer 66MHz 32/64-bit PCI and I2O support for the MIPS CPU architecture family needs an NDA according to the web site http://www.galileot.com/. The Sun SME2411 data sheet is at: http://www.sun.com/microelectronics/sme2411bga-66/datasheet/01.html Regards, CaryArticle: 7996
Hello, can anybody make any suggestions on how best to implement a small (5 level max.) 'psuedo' asynchronous FIFO in a Xilinx 9500 series CPLD? I realise the FPGA architecture is better suited to this but it is to be fitted into an existing CPLD design as a patch. Thanks, Graeme RobertsonArticle: 7997
I'm defining a state machine in ABEL HDL. Some nodes are LOW only during 1 state of 16. I have assigned the logic level to the node during each state: state 0: foobar = 1; state 1: foobar = 1; state 2: foobar = 1; state 2: foobar = 0; state 4: foobar = 1; state 5: foobar = 1; ... This is very tiring and invites to forget it once, especially when adding new nodes to the design. I have 20 or so nodes and clks that I have to repeat all over. How can I tell Synario that I want foobar to be 1 anytime I don't explicitly say otherwise?Article: 7998
Hi out there, I'm sorry to bother you with such a silly question, but I've tried many times to download the entry level software from Lattice semiconductor to program the simplest Lattice PLD's (Es. 1032), but I didn't succeed and I'd like to ask you if you can give me sone address or some way to download them from somewhere else. Sine I'm in europe, I think that the connection to the Lattice site is so slow that it's not reliable. Thanks in advance Cristiano MianiArticle: 7999
Jacob W Janovetz wrote: > z80@ds.com (Peter) writes: > > >The reason for this > > >>|I like what I've heard of this technology, and it blows my mind > that it > >>is not much more commonplace. > > >is mainly this: > > >>Most of the available design software will cost you between $1,000 > and > >>$5,000 > > >Peter. > > >Return address is invalid to help stop junk mail. > >E-mail replies to z80@digiXYZserve.com but > >remove the XYZ. > > I agree with this... I use FPGAs and CPLD and such on a daily > basis here at school. We have several projects going on which use > Xilinx FPGAs, Altera FLEX parts, and Cypress CPLDs. Unfortunately, > once I leave school, I probably won't do much with them at all > because I can't afford the development tools. The cheap/free stuff > has such severe limitations that it isn't worth it. > > The Cypress ISP FLASH CPLDs (373i, etc.) are the only ones which > have reasonably priced tool support. Warp itself isn't even all > that good as a VHDL compiler. You can almost change the organization > of concurrent processes and it compiles differently... > > Anyhow, tool vendors: lower your prices! > > Cheers, > Jake > > -- > janovetz@uiuc.edu | Once you have flown, you will walk the earth > with > University of Illinois | your eyes turned skyward, for there you have > been, > | there you long to return. -- da Vinci > PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html We can get you into XILINX or Lucent devices at very low prices. Please check our website for the tools we offer. The XILINX Foundation Series and PeakLucent kits can get you entry tools and router and development boards in the hundreds of dollars. This was unheard of in the recent past. For those interested in the full blown Foundation series with or without VHDL compiler please contact us for pricing and you will be pleased at what we can do. THe Foundation VHDL kits will soon be switching to Synopsis FPGA Express, and if you order your FOUNDATION Kits now you will recieve the upgrade as a normal part of the one years maint.! Email us and let us know if you are interested. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z