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David R. Brooks (daveb@iinet.net.au) wrote: : I have been asked to locate vendors who can take an FPGA-based design : (Xilinx, specifically), and migrate it to an ASIC for economy in large : volumes. I know of Xilinx' own Hardwire service, and Orbit : Semiconductor. What other sources would anyone recommend? : : TIA : : David R. Brooks <daveb@iinet.net.au> Tel/fax. +61 9 434 4280 : Since you live in Europe you may want to check out Temic FPGA services. I haven't tried them but if what they say (e.g. No NRE and guaranteed functionality without test vectors from you) is true; it's some thing worth looking at. Regards, Kayvon Irani H/W Design Engineer Los Angeles,USArticle: 2226
Iv'e been told by my Xilinx Sales guy that I should be using X-Blox. PLease comment on good and bad experiences. TedArticle: 2227
>...try and place logic near the edges to free up >the center which can then be used for routing. > >Steve Casselman That's what I did after all. I placed empty rows and columms as routing channels in areas of high connectivity. I also left CLBs beneath IOBs empty. This highly improved routability. Christian GrebeArticle: 2228
This is part of the documentation for the 'Xilinx Synopsys Interface' (XSI) design tool kit. Christian GrebeArticle: 2229
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3rd Workshop on Designing Correct Circuits
==========================================
The third workshop on Designing Correct Circuits will be held on Monday
2 September from Wednesday 4 September 1996 at Baastad in Southern
Sweden. The two previous DCC workshops have been held in Oxford and
Lyngby. This workshop is being organised by Satnam Singh (Glasgow), Mary
Sheeran (Chalmers) and Geraint Jones (Oxford).
Relevant topics include but are not limited to:
> formal hardware design languages,
> hardware design by transformation,
> computer-aided design and verification of hardware,
> high level synthesis and silicon compilation,
> techniques for the design of FPGA circuits,
> methods for designing testable circuits,
> analysis of circuit descriptions,
> novel VLSI algorithms and architectures,
> asynchronous circuit design.
The workshop will be of interest to researchers in the area of formal
methods for hardware design, and to engineers in industry wishing to
keep abreast of this fast-moving and exciting field.
The program committee for this workshop will include:
> Kees van Berkel (Philips, The Netherlands)
> Graham Birtwistle (University of Leeds, UK)
> Albert Camilleri (Hewlett-Packard, USA)
> Carlos Delgado Kloos (Universidad Politicnica de Madrid)
> Arnold Ginetti (Compass Design Automation, France)
> Mark Greenstreet (University of British Columbia, Canada)
> Keith Hanna (University of Kent, UK)
> Geraint Jones (University of Oxford, UK)
> Miriam Leeser (Cornell University, USA)
> Wayne Luk (Imperial College, UK)
> Tom Melham (University of Glasgow, UK)
> Robin Sharp (Technical University of Denmark, Denmark)
> Mary Sheeran (Chalmers Technical University, Sweden)
> Satnam Singh (University of Glasgow, UK)
> Richard Taylor (Hewlett-Packard, UK)
Call for Papers
===============
You are invited to submit a draft full paper (four copies if
convenient) on a relevant subject by Wednesday 31 January 1996. Notification
of acceptance will be posted by mid April, and revised papers will be
due about six weeks later.
The email address for submissions and more information is:
dcc-workshop@comlab.ox.ac.uk
The most up-to-date information about this workshop can be found at the URL:
http://www.dcs.gla.ac.uk/~satnam/dcc.html
Papers can be sent by post to:
DCC'96 Workshop
Satnam Singh
Dept. Computing Science
University of Glasgow
Scotland, G12 8QQ
United Kingdom
Tel: +44 141 330 4454
Email: satnam@dcs.gla.ac.uk
______________________________________________________________________________
Satnam Singh T +44 141-330-4454
Dept. Computing Science, F +44 141-330-4913
The University of Glasgow, E satnam@dcs.glasgow.ac.uk
Scotland G12 8QQ, United Kingdom. I http://www.dcs.gla.ac.uk/~satnam
______________________________________________________________________________
"You should be glad that bridge fell down - I was planning to build thirteen
more to that same design" - I.K. Brunel
Article: 2230At least 8,000,000 men, women and children are dying every year and 1,000,000,000 others all over the world have their health seriously effected, from something that we are all exposed to at some time, and most of us are exposed to very often. You are invited to make yourself fully aware of these dangers to yourself and your loved ones and to be introduced to preventative measures which may be taken immediately. By taking a few minutes to visit this very informative and well presented web site <http://www.ozlink.com/yinyang/> you could be saving yourself and those you care about a whole lot of suffering and sorrow. If you don't have time right now, please BOOKMARK this address now and go to it as soon as possible. A life may depend on it.Article: 2231
Derek Chang (dchang@san-jose.ate.slb.com) wrote: : What do you mean the design is different ? : You can do anything with an FPGA that discrete ICs : can do. : Derek Yeah! How about speed ? HarryArticle: 2232
I developed the partitioner for FPGA, I want to test this system but I have few test data. The Larger, the better I'm looking for VHDL code synthesizable at synopsys. and Circuit's primary IO must be less than 180. Circuit's size is good for 10~14 FPGA. If you have a question to me, Please Send me a mail. part95 Dept. of Computer Science Sogang Univ. e-mail : part95@dalab2.sogang.ac.krArticle: 2233
Hello guy,
I use X-blox frecuently. If you have a Sun station or a Pentium-200Mhz,
it's
possible X-blox runs okey. However, I don't have such equipment. If I run big
designs (with X-blox), Xmake 5.1 it's not able to route it completely because
X-blox symbols are placed as vertical RPM. If you use a large shifter, for
example, and you want to use all its outputs, ppr won't finish the routing
process (maybe yes if you use NeoCad soft).
Of course, if you use X-blox for small designs, probably you'll be happy.
Regards,
Fernando
Article: 2234X-Blox is OK if you are using schematics only, and you have the intention to NEVER switch to another FPGA family, or switch to an HDL like VHDL or Verilog. In 5 years, X-Blox will be dead, replaced by HDL's, I'm sure. However, for the moment, it's better than flat schematics if you can't afford a compiler. X-Blox designs can't really be translated to other formats (before flattening), and netlist flattening is required before a design can be turned into an XNF file that 3rd party tools can read. You can still go to hardwire or gate array, but the netlist is a flattened variety like that generated from an ordinary schematic. John McCluskeyArticle: 2235
--I'm developing a prototype stack-based multithreading RISC
processor using Xilinx FPGAs and a "BORG II" development board
produced by UC Santa Cruz. In order to connect the BORG
board to a PC externally -- it's currently connected in
an I/O expansion slot -- I need a "Protozone Adapter Card/Cable".
**Does anyone know where I can get one of these cards/cables?
The source listed in the BORG documentation seems to have gone
out of business.
The protozone card/cable consists of:
one end: 8-bit XT male expansion card
other end: ribbon cable connected to 50-pin female (IDC?) connector
I realize that I could use a bus extender card, but I'd rather not
cut a hole in the side of my PC case...
Also, is anyone else using a BORG multi-FPGA board? What kind of
projects are you working on? Have you had any problems with
the BORG?
**Replies by email are preferred, as my local news server is a bit
eccentric.
Thanks in advance.
--Jeff Bain
Cal Poly, San Luis Obispo
jbain@ohm.elee.calpoly.edu
Article: 2236In article <47n7n3$38i@ccsun2.sogang.ac.kr>, NAM MIN WOO <esfree> wrote: > I developed the partitioner for FPGA, I want to test this system > but I have few test data. > > The Larger, the better > I'm looking for VHDL code synthesizable at synopsys. > and Circuit's primary IO must be less than 180. > Circuit's size is good for 10~14 FPGA. > > If you have a question to me, Please Send me a mail. I'm using synopsis to simulate and synthesize a 32-bit RISC CUP-core. The target is a ZyCad hardware emulator using a stack of Xilinx FPGAs. Is this what you are looking for? BTW, your return email address is invalid. -- damir smitlener | damir@mindspring.com | smitty@optica.mirc.gatech.edu |Article: 2237
>>>>> "Don" == Don Husby <husby@fnal.gov> writes:
Don> I prefer the pro-series to the older workview. It's much
Don> more pleasant to use, and works well with Windows 3.1 (but
Don> NOT win95)...
We bypassed the whole adolescent Win95 phase by running our ProSeries
tools on our existing OS/2 systems, with good results. Although some
of the ProSeries' capabilities *are* a step backwards from Workview
(e.g. the abysmal plot quality), I think that most of the DOS
executables are there to allow (undocumented) work-arounds (e.g. use
placer.exe and transer.exe).
--
Roger Williams PGP key available from PGP public keyservers
Coelacanth Engineering consulting & turnkey product development
Middleborough, MA wireless * DSP-based instrumentation * ATE
tel +1 508 947-8049 * fax +1 508 947-9118 * http://www.coelacanth.com/
Article: 2238
In article <DHFC7I.9Dy@zoo.toronto.edu>
henry@zoo.toronto.edu "Henry Spencer" writes:
<snip>
>> In fairness, there is one tricky problem: customers who want to make
>> their products reverse-engineering-proof. This is hard to do with the
>> Xilinx approach, in which the bit stream to program the FPGA *must* come
>> from an external source and hence is easily tapped. To handle this in the
>> context of an open architecture, the chip needs to have either encryption
>> hardware or on-chip nonvolatile memory, neither of which is trivial.
But would it not be relatively straightforward for Xilinx to add a few bytes
of non-volatile public key memory (read/write) plus private key memory (write
only) and implement a small decryption engine. The configuration data rates
are so low that a serial arithmetic scheme should be possible.
Even a simple system would give a huge increase in design security.
<snip>
--
Regards
Tim Eccles
Article: 2239I desparately need 15 of the above devices. The lead time given by our distributor has been extending and it is causing us some severe problems. If you have any stocks of this device or know where I can get some then please contact me. Please note that this is a 'L' (i.e. 3.3V) part and a 5V XC3090 will not do. Thanks, Mark Snook (mark.snook@armltd.co.uk)Article: 2240
**************************************************************************** FPD'96 - Call for Papers The 4th Canadian Workshop on Field-Programmable Devices May 20 - 21, 1996, Toronto, Ontario, CANADA **************************************************************************** The fourth Canadian Workshop on Field-Programmable Devices, FPD'96, will be held at the University of Toronto. The workshop provides a forum for discussion of all aspects of FP technology, including architecture and CAD tools for FPGAs, CPLDs, FPGA-based systems, FPGA-based computing, and FP Analog Arrays. The workshop strives both to advance the state of research for FP technology, as well as to promote better understanding of uses and design techniques of FPDs. Of interest are papers describing original research in FPD architecture and CAD algorithms, as well as design oriented papers that discuss novel uses of FPDs or design methodologies. Extensions of previously published work will also be considered. Full-length papers are solicited in, but are not limited to, the following areas: o Architecture of CPLDs/FPGAs o CAD: HLS, partitioning, logic opt, tech mapping, placement, routing o Application-specific FPGA architectures o System design methodologies/experience o FP technology issues o Trade-offs between area-efficiency and speed-performance for FPDs o New commercial architectures o Interactions between logic synthesis and layout synthesis o Field-Programmable Analog Arrays o Novel uses of FPDs o FPDs in education o FP-systems: emulators, compute engines, partitioning, interconnect, routing ********************************************* * Important Dates: * * Submission deadline: January 21, 1996 * * Acceptance notification: March 20, 1996 * * Camera-ready copy due: April 15, 1996 * ********************************************* Submission: Authors should submit eighteen copies of the complete paper (limit 10 pages, minimum point size 10), as well as a separate title sheet with the following: title of paper, abstract (100 words or less), names and affiliations of all authors, telephone, FAX, and email for corresponding author. Send submission to: Stephen Brown, Chair FPD'96 Dept. of Elec. and Computer Engineering, U. of Toronto 10 Kings College Road Toronto, CANADA M5S 1A4 brown@eecg.toronto.edu, phone: (416) 978-1647, FAX: (416) 971-2326 ************************************* Technical Program Committee Michael Alexander, U. Virginia Stephen Brown, U. Toronto (chair) Jacob Davidson, U. Quebec a Montreal Robert Francis, Xilinx (Canada) Dwight Hill, Synopsys Andrew Kahng, UCLA Sinan Kaptanoglu, Actel John Knight, Carleton U. Robert McLeod, U. Manitoba Michael Miller, U. Victoria Gabriel Robins, U. Virginia Jonathan Rose, U. Toronto Mohamad Sawan, E.P. Montreal Tim Southgate, Altera Steve Trimberger, Xilinx Laurence Turner, U. Calgary Martin Wong, U. Texas Nam-Sung Woo, AT&T *********************************************************** * See also URL http://www.cs.virginia.edu/~robins/fpd96/ * ***********************************************************Article: 2241
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F P L '96
S I X T H I N T E R N A T I O N A L W O R K S H O P
FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
_| _|
_| September 23 - 25, 1996 (Monday - Wednesday) _|
_| _|
_| Darmstadt, Germany _|
_| _|
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
C A L L F O R P A P E R S A N D P A R T I C I P A N T S
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_| Paper Deadline March 6, 1996 _|
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PLEASE DISTRIBUTE THIS CALL TO ALL INTERESTED COLLEAGUES AND PEOPLE
ACCORDING TO YOUR MAILING LIST, THANKS IN ADVANCE!
AIM
The aim of this workshop is to bring together workers from throughout
the world for a wide ranging discussion of all forms of field
programmable logic (but particularly field programmable gate arrays)
and their applications. It is intended to discuss the increasing range
of device types, industrial applications, advanced CAD developments,
research applications, novel systems architectures and educational
experiences. The workshop will include regular presentations, posters
and discussion sessions and it is expected that most of the delegates
will wish to make some contribution to one or more of these. The
workshop is to be considered as continuation of four already heldSE
international workshops in Oxford (1991 and 1993), Vienna (1992) and
Prague (1994).
CALL FOR CONTRIBUTIONS
Contributions are invited for regular presentation, poster and
discussion sessions. Prospective authors are invited to submit an
abstract of at least 500 words or a full paper by 6 March 1996 to the
Program Chairman. Please preface this by your full correspondence
address, including e-mail, and fax, a list of (at most) 5 one-line
statements that best encapsulate the essence of your proposed
contribution, and a note of your preferred presentation format. Please
mail 10 copies if possible, but submissions by e-mail
(abakus@informatik.uni-kl.de) or fax (+49 631 205-2640) will also be
accepted.
NOTIFICATION OF ACCEPTANCE will be posted by 8 May 1996 and final
papers must be received by 3 July 1996 to guarantee distribution at
the workshop. Accepted papers will be published in book form by
Springer before the workshop. Potential exhibitors and tutorial
presenters are also invited to contact the Program Chairman. The
official conference language as well as the language of submissions
and accepted papers will be English.
SCOPE
Field Programmable Logic has been available for a number of years, but
the increasing power and variety of devices now available is extending
its role from that of simply being a convenient way of implementing
the system glue logic to an increasing ability to implement mainstream
system functions. The speed with which devices can be programmed makes
them ideal for prototyping and education, the reprogrammable devices
are opening up sophisticated new applications and hardware/software
trade-offs. CAD is developed for automatic compilation of advanced
designs and routes to custom circuits are now available.
WORKSHOP TOPICS:
The topics should cover, but are not restricted to:
- New and future commercial devices
- Novel chip architectures
- New software and hardware development tools
- Bridges to other CAD and to custom circuits
- High-level design and compilation research
- Industrial applications and experiences
- Trade-offs betweendevices, architectures and technologies;
Benchmark comparisons
- Smartapplications
- Custom computers
- Hardware/Software Co-Designusing FPL
- Novel machine paradigms and system architectures
- ASIC emulators, hardware modellers and compiled accelerators
- Fault models, testability methods, reliability
- Educationalexperiences and opportunities
GENERAL CHAIRMAN:
Prof. Manfred Glesner
Darmstadt University of Technology
Karlstrasse 15
D-64283 Darmstadt
Germany
Phone: +49 6151 16-5136
Fax: +49 6151 16-4936
email: glesner@microelectronic.e-technik.th-darmstadt.de
PROGRAM CHAIRMAN:
Prof. Reiner W. Hartenstein
University of Kaiserslautern
P. O. Box 3049
D-67653 Kaiserslautern
Germany
Phone: +49 631 205-2606
Fax: +49 631 205-2640
email: hartenst@rhrk.uni-kl.de
PROGRAM COMMITTEE: Jeffrey Arnold, IDA CCS, USA
Peter Athanas, Virginia Tech, USA
Gaetano Borriello, U. of Washington, USA
Stephen Brown, U. of Toronto, CA
Klaus Buchenrieder, Siemens AG, FRG
Bernard Courtois, INPG, Grenoble, France
Keith Dimond, U. of Kent, UK
Patrick Foulk, Heriot-Watt U., UK
Norbert Fristacky, Slovak Technical U., SK
Manfred Glesner, TH Darmstadt, FRG
Daniel Gajski, UC Irvine, USA
John Gray, Xilinx, UK
Herbert Gruenbacher, Vienna U., Austria
Reiner Hartenstein, U. of Kaiserslautern, FRG
Udo Kebschull, U. of Tuebingen, FRG
Andres Keevallik, Tallinn Technical U., Estonia
Chong-Min Kyung, KAIST-Inst. of Techn., South Korea
Wayne Luk, Imperial College, UK
Patrick Lysaght, U. of Strathclyde, Scotland
Will Moore, Oxford U., UK
Klaus Mueller-Glaser, U. Karlsruhe, FRG
Wolfgang Nebel, U. of Oldenburg, FRG
Peter Noakes, U. of Essex, UK
Franco Pirri, U. of Firenze, Italy
Jonathan Rose, U. of Toronto, Canada
Zoran Salcic, U. of Auckland, New Zealand
Mariagiovanna Sami, Politechnico di Milano, Italy
Alberto Sangiovanni-Vincentelli, UC Berkeley, USA
Michal Servit, Czech T. U., Czech Republic
Mike Smith, U. of Hawaii, USA
Steve Trimberger, Xilinx, USA
LOCAL DETAILS
The workshop will be held at the Orangerie in Darmstadt, on 23rd -
25th September 1996. The Orangerie is an attractive old palace, which
contains rooms for congresses. A bus ticket for reaching the Orangerie
during the workshop is included in the registration fee. Darmstadt,
which is situated in the Rhein-Main-Area nearby Frankfurt, Wiesbaden,
Mainz and Heidelberg, has numerous cultural and tourist attractions as
well as plenty to interest accompanying partners. There are fast
connections to Frankfurt International Airport. All the latest
information about FPL'96 can be accessed via a WWW-page. The URL for
this document is:
http://www.microelectronic.e-technik.th-darmstadt.de/fpl96/fpl96.html
REPLY FORM FOR REGISTRATION FORM
We encourage you to reply via e-mail, giving us the information listed
below. If you do not have the possibility to use e-mail, please copy
the form below and send or fax it in advance to the General Chairman.
-------------------- FPL `96 - REGISTRATION FORM --------------------
Name: .........................................................
(Family Name) (First and Middle)
Affiliation:.........................................................
Address: .........................................................
.........................................................
Country: .........................................................
Phone: .........................................................
Fax: .........................................................
E-mail: .........................................................
Registration fees *)
_
| | Normal fee DM 490
- Includes attendance to all sessions, social program,
banquet, workshop proceedings and bus ticket.
_
| | Student fee DM 250
- Includes attendance to all sessions and bus ticket.
_
| | Spouse / Partner fee DM 200
- Includes social program, banquet and bus ticket.
TOTAL AMOUNT: DM ....
Payment should be made in advance, in DM. Please select method of
payment:
_
| | Transfer to our bank account
- Darmstaedter Volksbank e. G. (BLZ: 50890000)
Account No.: 1218611 (recipient: Prof. Manfred Glesner)
Please specify: "FPL'96 & delegate name"
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CREDIT CARD ONLY:
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arriving at our bank must not be less than the registration fee.
Please take care that any banking fees are settled.
Date and Signature:..................................................
---------------------------- End of form ----------------------------
----------------- FPL `96 - Hotel Reservation Form ------------------
*** DEADLINE: August 23rd, 1996 ***
Name: .........................................................
(Family Name) (First and Middle)
Affiliation:.........................................................
Address: .........................................................
.........................................................
Country: .........................................................
Phone: .........................................................
Fax: .........................................................
TYPE OF ROOM:
_
| | single room
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| | single room
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| | single room
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PREFERED CATEGORY:
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| | category I about DM 210
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| | category II about DM 130
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| | category III about DM 90
-
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(You will be informed about single / double room conditions)
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---------------------------- End of form ----------------------------
Please send or fax Hotel Reservation Form in advance
(until August 23rd 1996) to:
Magistrat der Stadt Darmstadt
Verkehrsamt
z.Hd. Frau Neubauer
Luisenplatz 5
D-64283 Darmstadt
Germany
Hotel accomodation is merely found for you. Therefore, we do not take
any responsibility.
Verkehrsamt der Stadt Darmstadt
Tourist-Information
am Hauptbahnhof
Tel.: (+49) 6151 - 13 27 82
Fax: (+49) 6151 - 13 27 83
Article: 2242Is it possible to configure a Xilinx 30xx IOB connected to RESET~ to successfully reset the chip? If so, how? tiaArticle: 2243
Everyone has to start somewhere, and we're just getting into the fpga/pla field as an upward migration from our usual 'pile of chips' designs. I've checked out the entry level software/programmer field, and would like to have your thoughts. I'm seriously considering a BP1148 or BP1200, and CUPL Total Designer (normally $2500, now on a 'Wescon special' for $1500). Anyone using these or others that'd like to help me feel good about this decision, or better with another? Cheers, Alan acooney@netcom.comArticle: 2244
In article <815844791snz@tile.demon.co.uk> Tim@tile.demon.co.uk writes: >But would it not be relatively straightforward for Xilinx to add a few bytes >of non-volatile public key memory (read/write) plus private key memory (write >only) and implement a small decryption engine. The configuration data rates >are so low that a serial arithmetic scheme should be possible. Unfortunately, while these encryption schemes are *conceptually* simple, the hardware needed to implement them, even at moderate bit rates, is not trivial. Jesus, I can't believe I'm *defending* Xilinx...! :-) Encryption is probably what they ought to do in the long run, but right now it's easier for them to just be secretive. Besides, they sell more software that way. -- The problem is, every time something goes wrong, | Henry Spencer the paperwork is found in order... -Walker on NASA | henry@zoo.toronto.eduArticle: 2245
In article <47oj1a$62i@news0.login.net> John McCluskey <jbm> writes: > X-Blox is OK if you are using schematics only, and you have the intention to > NEVER switch to another FPGA family, or switch to an HDL like VHDL or Verilog. > In 5 years, X-Blox will be dead, replaced by HDL's, I'm sure. However, for > the moment, it's better than flat schematics if you can't afford a compiler. If you are designing with HDL & Synopsys, then FPGA Compiler together with X-BLOX improves the utilization efficiency remarkably. In practice this co'operation means you have an infinite DesignWare library. Works well and I don't think X-BLOX will die very soon. qruArticle: 2246
CALL FOR PAPERS
JOURNAL OF REAL-TIME IMAGING
Academic Press
Special Issue on
Special-Purpose Architectures for Real-Time Imaging
Nowadays, a number of different problems are solved through image processing
techniques (e.g. industrial inspection, robot guidance, unmanned vehicles,...,
to cite only a few examples). The problem of processing images in real-time
has been generally addressed and solved through the use of high-performance
computer systems, developed ad-hoc to meet the specific requirements of the
applications. Serial or parallel architectures have been enhanced through the
addition of various bus systems, interprocessor communication networks, and
other features explicitly designed to face the hard constraints imposed by
real-time processing, such as I/O (data acquisition and output), data
communications among processors (in multi-processor systems),...
A number of different special-purpose architectures for image analysis have
been proposed and developed, but seldom the presentation focuses on the
discussion of both the hard real-time requirements (applications) and the
hardware solutions which have been chosen (computer architectures).
The TOPICS of this Special Issue include, but are not limited to:
* Design of application-specific VLSI architectures;
* Performance analysis and comparison among different architectural solutions;
* Hardware mapping of parallel algorithms;
* VLSI architectures for HDTV and image compression;
* Hardware support for multimedia systems;
* Vision-based real-time robot and vehicle navigation;
* Massively parallel architectures for low-level vision;
* Hardware neural solutions;
* Experience on highly demanding vision applications.
Prospective authors are encouraged to submit papers with a strong emphasis on
the match between the application requirements and the chosen architectural
solutions, detailing the ad-hoc hardware enhancements. Papers should describe
systems which have been designed for a specific target application or which
have proved to be particularly suited for a given task.
MANUSCRIPT SUBMISSION:
* Authors should send 5 copies of their full paper (about 15 double-spaced
pages) to:
Alberto BROGGI
Dip. di Ingegneria dell'Informazione
Viale delle Scienze
University of Parma
I-43100 Parma, Italy
indicating their full postal address and e-mail address. Electronic or fax
submissions will *NOT* be considered.
* The closing date for submission is *DECEMBER 10th, 1995*.
* Publication is tentatively expected to take place in MID 1996.
* The final call-for-papers and up-to-date information can be obtained via WWW
at:
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Article: 2247I am looking for info on the JTAG standard, mainly how it is used for testing fpga's etc. I would really like an FAQ on this if possible. Can anyone point me to the place where this info can be found? Thanks in advance for the information. Paul Brown.....Article: 2248
caleb@audiologic.com wrote: > >Is it possible to configure a Xilinx 30xx IOB connected to RESET~ >to successfully reset the chip? If so, how? >tia I've done this. You can implement a flip-flop in combinatorial logic and run your system clock to it to provide a full clock cycle's worth of a reset pulse.Article: 2249
TWColl (twcoll@aol.com) wrote: : Iv'e been told by my Xilinx Sales guy that I should be using X-Blox. : PLease comment on good and bad experiences. : Ted I've used XBlox together with ACEPlus (not many have, I understand) and I've used ACEPlus with ABEL-coded blocks (even fewer have). So far, two bugs have been discovered. First, ACEPlus makes the BUS_DEF definitions in the .xnf-file wrong, after running aptoudb and udb2xnf, it looks like this: "BUS_DEF" where it should be: "BUS_DEF, DEF=BLOX". Second, when I've compiled the ABEL-files (using Intergraph's PLDSyn) and merged them, the information about which compilers I've used for the ABEL-code aren't accepted by the xblox program which aborts. Thus, these lines (beginning with "PROG, Version" and "PROG, PLA2XNF") must be removed. This I cannot blame Xilinx for, since Intergraph's products aren't supported by Xilinx, but beware if you are using these tools. By the way, anyone else out there using the same products I do? Mail me: d0jef@dtek.chalmers.se Best regards /Per
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