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Matthew Carlson (carlson@rahul.net) wrote: : GDR Enterprises (102771.3337@CompuServe.COM) wrote: : : $$$ Change Your Life $$$ : I just got to flame this bastard. What does this have to do with : mathematics? Nothing you ass..... !!!!!!!!! I cannot stand this kind of : garbage. Get a life. : 102771.3337@compuserve.com : Hey! Compuserve charges like 10 cents for every internet email you : recieve. Lets send him hate mail. Unfortunately his box only hold 100 : letters but, that is still 10 dolars. If this guy has made 10,000 he can : afford it. : -- : Matthew Carlson <carlson@rahul.net> I already sent him his own message. Whenever I see this garbage I just send it back (kind of reflex - I can't help it).Article: 2101
Sudhir Wokhlu (sudhir@utdallas.edu) wrote: : My department needs to buy PC-based FPGA Design entry and Simulation : software for Actel FPGA's. As it is not possible to evaluate all the : major tools on the market an input from designers out in the industry : using FPGA's will be greatly helpful. : I would appreacite if designers could give their opinions on VIEWLOGIC/ : ORCAD/INTERGRAPH based on their experience with these tools. : We are a small research staff at a University and do not get to change : tools often for want of money (we are lucky if that happens once every : 10 years!!!). It is imperative that we make the best choice now. In view : of this, opinions of experienced designers will be very valuable. : Thanks in advance, : Sudhir Here is my own opinion based on my own experience: ORCAD The best schematic entry tool - simple, fast, convenient, cheap. The problem is that all the rest of it is not so good : simulation, HDL ( not sure it is already released ), synthesis , FPGA support ( if you need only Actel it is no problem but if you try to switch to another FPGA, say ORCA or ATMEL you will have to buy another tool). ViewLogic PRO: one of the few EDA systems providing all in one package ( schematic, VHDL for both simulation and synthesis, simulation tools etc.). Supports nearly every FPGA known to humanity. CONTRA: idiotic schematic editor (bad user interface which did not improve with Windows release); low software quality ( a lot of bugs and they are not that fast to fix them); very expensive ( PROexpert package for FPGA design costs about $15k). I don't know a lot about Synario ( DATA I/O) but you may want to take a look at this one . It is something closer to ViewLogic than to OrCad ( and probably with the same problems).Article: 2102
> >OK, Jan, since I've been accused of the most unforgivable crime of "Deceptive >Anologies", before the authorities come to take me away to serve hard time, >I'd like to ask: "Are you saying that the VHDL contestants were at a >disadvantage *because* they were brutally forced to use std_logic in >designing a simple 9-bit up/down counter instead of using 'integer' >and 'boolean' data types?" > Yes, in VHDL it is an important disadvantage if you don't get the freedom to make your own type choices. In contrast to Verilog it happens to be a strongly typed language. Consequently, choosing the "right" type has a big impact on code clarity and coding time. Regards, Jan =================================================================== Jan Decaluwe === Easics === Design Manager === VHDL-based ASIC design services === E-mail: jand@easics.be =================================== NEW! Tel: +32-16-298 400 NEW! Fax: +32-16-298 319 Kapeldreef 60, B-3001 Leuven, BELGIUMArticle: 2103
ekatjr@eua.ericsson.se (Robert Tjarnstrom) wrote: >Currently microprocessors perform about 5 times better than ASIC design, although >using comparable manufacturing technology. What is the poor process utilization >due to? > Maybe it's because increasing the clock frequency of a uP is one of only methods left to speed up the Von Neumann bottleneck (before more radical architectural changes, such as computing with programmable logic, become unavoidable), making it worthwhile to throw development money and power dissipation at it? Maybe uP designers have been unexpectedly succesful to do this, perhaps because they are increasingly applying ASIC design techniques such as timing-driven logic synthesis? >Will a move to "higher abstraction levels" increase or decrease the gap? The only significant influence should be on design time (otherwise such a move is not acceptable). Regards, Jan =================================================================== Jan Decaluwe === Easics === Design Manager === VHDL-based ASIC design services === E-mail: jand@easics.be =================================== NEW! Tel: +32-16-298 400 NEW! Fax: +32-16-298 319 Kapeldreef 60, B-3001 Leuven, BELGIUMArticle: 2104
I have used the Xilinx kits with SPARCstation 5s and SOlaris 2.3 with success. I have used the kit (not the XCHECKER cable, yet) under 2.4. I'm somewhat surprised you got the license manager to work :-) that was our problem for a long time until we revealed that we need the license server's name in /etc/hosts even if NIS+ is running... This is a NIS+ problem, it turns out, and many people I know are not using it. Anyway, I do not recall any strange things that we had to do to make the cables work with Solaris. I think the only think we might have done is explicitly specify the port on the command line of xchecker (and maybe the port speed, also). You might want to check that. Hope this helps... DaveArticle: 2105
Anyone seen a 90 degree 20 pin LCC socket? Not exactly fpga, but given the funky sockets/adapters used on things like the MACH445 (hint DIGIKEY- ARIES) one of you guys must have seen such a beast somewhere.Article: 2106
Sudhir Wokhlu (sudhir@utdallas.edu) wrote:
: My department needs to buy PC-based FPGA Design entry and Simulation
: software for Actel FPGA's. As it is not possible to evaluate all the
: major tools on the market an input from designers out in the industry
: using FPGA's will be greatly helpful.
:
If you just want to use Actel parts; you're better off getting their
own tools; they have VHDL or schematics entry at low cost but if you
want to be able to take your design abd may be retarget that to another
family say from Xilinx or Quicklogic you're better off getting a tool
like Exemplar or Synplicity. Integraph tool is based on At&t synthesis
tool based on Verilog they don't have architecture dependent optimiza-
tion and use LPMs this may be sufficient if the place and rout tools
can do a good job with LPMs. Viewlogic tool has schematic/VHDL although
their VHDL is not completely compatible with Synopsys or Mentor VHDL.
I wouldn't spend money on tools coming from a copmany that's not
in the synthesis business(like ORCAD).
Regards,
Kayvon Irani
Los Angeles, Ca
Article: 2107
Dear Sir
Who can give some answer ? I would very pleased
for some suggest
bit transistor gate
R3000 MIPS 115000 ?
SRAM 256k ? ?
SDRAM 256k ? ?
DRAM 4m ? ?
32-bit GaAs mp ? 10000
GaAs SRAM 16k ? ?
DEC 21064 5 mln ?
Article: 2108Right! Can you please post the address of your instructor, so that we can send the answers direct? In article <Pine.SOL.3.91.951012192708.17854A-100000@dcsun4.comp.brad.ac.uk>, Ian Harrison <irharris@comp.brad.ac.uk> wrote: > >Right. I've got a challenge for all you boffins out there. See if you can >get these questions correct: (Correct answers will be posted on 15/10/95) > ... -- Kenneth Sloan sloan@cis.uab.edu Computer and Information Sciences (205) 934-2213 University of Alabama at Birmingham FAX (205) 934-5473 Birmingham, AL 35294-1170 http://www.cis.uab.edu/info/faculty/sloan/Article: 2109
Does anyone have or know of a VHDL model or a utility to generate VHDL simulation model for Xilinx 4000 RAM modules? I can easily write a behavioral model for the RAM cell but I am looking for some proven models preferably with full timingcheck capability. Thanks in advance for your help. -- ---------------------------------------------------------------- Ivan Lee Voice: 214-991-3884 x320 Fax: 214-991-3887 Efficient Networks Inc. <<<<53 bytes>>>> ivan@efficient.com ----------------------------------------------------------------Article: 2110
In article <Pine.SOL.3.91.951012192708.17854A-100000@dcsun4.comp.brad.ac.uk>, Ian Harrison <irharris@comp.brad.ac.uk> wrote: > >Right. I've got a challenge for all you boffins out there. See if you can >get these questions correct: (Correct answers will be posted on 15/10/95) > >1. Give the IBM floating-point representations for decimal 55.4 and -53.4 It's been decades since I payed attention to that. As I recall, IBM used base 16. I'll guess that 1 is stored as .1h * 16^1, so 55.4 would be (55.4)/256 * 16^2. I think the sign was the msb of the exponent. I don't recall whether the mantissa was two's comp or abs + sign and don't recall the bias, but I will guess 64. I think the sign + exponent was one byte, with 3 bytes left for the mantissa in single precision. I think double precision had the same exponent format, but 7 bytes of mantissa. If you really want, I can look for my old IBM manuals. ;-) >2. Give the IEEE standard single-precision floating-point representations for +29 and -29 IEEE is binary so that would be mantissa = 29/16, giving a significand of 13/16. The exponent is excess 128, I think, giving 7E680000 and FE680000 with 1/8/23 bits for sign, exponent, significand. >3. Compare the ranges, accuracy, and other system design considerations >for the preceding two floating-point number systems. The IEEE-754 is more accurate than IBM single precision because it carries 24 bits, including the implied 1 for all normalized numbers. It has a range of approximately 10e-38 to 10e+38. It also has representation for infinity and indefinites (NaNs). It also has signed zero and high portability due to tightly-specified results. IEEE has explicit control of rounding modes. The IBM has a range, I think, of approximately 16^-64 to 16^+63, which would be about 10e-77 to 10e+76. I don't recall any representations for infinity or indefinites, nor control of rounding modes. >4. Write all 4-bit 2s compliment numbers (that is, sign plus 3-bit >numbers) and their decimal values. Show that negative numbers exceed >positive numbers by one. Consider 0 to be either -ve or +ve. Piece of cake. :-) 1000 = -8 0000 = 0 1001 = -7 0001 = 1 1010 = -6 0010 = 2 1011 = -5 0011 = 3 1100 = -4 0100 = 4 1101 = -3 0101 = 5 1110 = -2 0110 = 6 1111 = -1 0111 = 7 There are 8 negative numbers, 7 positive numbers, and one zero. I have no idea what you mean by -ve or +ve; zero is unsigned. >5. How many different numbers can be stored in a set of four switches, >each having three different positions (four three-position switches)? 3^4 = 81. Thad P.S. Answers are best recollection. If I were doing this on the job I would look it up.Article: 2111
alexk@dspis.co.il (Alex Koegel) wrote: > > Hello FPGA'ers, > > Does anybody know when the new announced Altera Flex10K will showup in samples > and production ? > > What will be the first member(s) of Flex10K family to be available ? > > Will an average Pentium PC (90Mhz, 32Mbyte DRAM) support the fitting power > needed for targetting designes into the new Flex10K ? > > Alex Koegel > HW Development Manager > DSPC Israel Alex: I hear that the FLEX EPF10K50 is available now, for sampling. Cost is somewhat prohibitive, our local distributor (Veltek) said around AUS$1200 each or so. Next devices to be released will be the EPF10K100 and the EPF10K10, due in a few months. I have no idea of pricing, but have been told that Altera plan to keep the price/gate the same as for FLEX 8000 parts, so they really won't be cheap. My understanding is that MAX PLUS II version 6 will have full support for these parts, and will run on a Windoze PC (Pentium or whatever). This software is due around Christmas. Cheers, Craig Jackson, Technical Officer, Orroral Geodetic Observatory.Article: 2112
1. Give the IBM floating-point representations for decimal 55.4 and -53.4
Normalized or not? *WHICH* IBM floating point format.
2. Give the IEEE standard single-precision floating-point representations
for +29 and -29
Um, uh, arrgh...
3. Compare the ranges, accuracy, and other system design considerations
for the preceding two floating-point number systems.
I do have an interesting story regarding this sort of thing. I was trying
to do my physics homework with a classmate on the university computers
(using APL as a programmable calculator, I think.) We had an IBM clone,
with its BCD mantissa and exponent, but it didn't have enough precision (I
forget what the actual problem was.) So we moved over the the DEC-10,
which has binary exponent and mantissa, but it didn't have the range
(couldn't even get h-bar squared!) A quick look a MACSYMA over the net at
MIT yielded info that there was infinite precision arithmetic available, if
only we could figure out how to use it. Sigh. I think we ended up on a
hand-held calculator. Actually running into the limitations of a computer
architecture sure teaches you a lot more than the architecture classes!
4. Write all 4-bit 2s compliment numbers (that is, sign plus 3-bit
numbers) and their decimal values. Show that negative numbers exceed
positive numbers by one. Consider 0 to be either -ve or +ve.
5. How many different numbers can be stored in a set of four switches,
each having three different positions (four three-position switches)?
These last two seem ridiculously easy compared to the first two, but
perhaps thats just because I remember my base 3 and twos-complement
formats, but not the IBM format, and I never learned the IEEE FP format.
BillW
Article: 2113In article <Pine.SOL.3.91.951012192708.17854A-100000@dcsun4.comp.brad.ac.uk>, Ian Harrison <irharris@comp.brad.ac.uk> wrote: > >Right. I've got a challenge for all you boffins out there. See if you can >get these questions correct: (Correct answers will be posted on 15/10/95) > <Questions Deleted> People like you don't need to have access to UseNet. It is not here for others to do your homework. If you have a REAL question, post it, otherwise let the rest of us exchange useful information. By the way, don't bother posting the answers - most of them can be found by reading any decent architecture book (or by doing your homework yourself.) **************************************************************************** Dan Bartram, Jr. Work: (404) 894-7107 Research Engineer FAX: (404) 894-7080 Georgia Institute of Technology Atlanta, GA 30318 Internet: dan.bartram@.gtri.gatech.edu ****************************************************************************Article: 2114
In <45gbik$ebk@diable.upc.es> <cha> writes: > >This is the third time XACT 5.1 fucks my Setup Configuration. Yes, the CMOS. >I think I'll never finish my work........ > > Of course, I use a PC with QEMM and I know they're not > compatible. Are you having problems with XACT tools per se, e.g. xdm, xde, ppr, etc., or, more likely, with WorkView/ViewLogic for DOS? It is quite likely that if you are experiencing that kind of corruption (as was I), that you do not have QEMM configured properly. Try editing the QEMM config line in your config.sys, to exclude more regions of the I/O address space. For instance, I use DEVICE=C:\QEMM\QEMM386.SYS x=a000-dfff frame=e000 which tells QEMM to keep its grubby hands off A0000 through DFFFF and to put its expanded memory frame at E0000. Further, my recollection is that Xilinx' 24-hr interactive support database at http://www.xilinx.com/support/ts_auto.htm had self-contradictory information on this problem. One article stated WorkView must not be run with any memory manager, another that it is OK, maybe, to use QEMM 6.x. My experience is that DOS WorkView only runs with QEMM 6.x (and not later versions) and only if QEMM is properly configured with respect to I/O space address exclusions. For what its worth, I am now able to use XACT 5.1 tools and WorkView, on my Win95 machine, after a fashion. The former run fine under Win95's HIMEM.SYS, and, as I said, the latter seems to need QEMM 6.x which is incompatible with Win95. Thus to use Workview I must hit F8 at Win95 startup and select option 8, boot to former DOS, with that DOS' config.sys set up to run QEMM 6.2 as the memory manager. (Thanks as usual to Philip Freidin for helping me work this out.) I have been surprised that (as far as I know) Xilinx has yet to publish a basic Win95 how-to for its customers who are still using DOS WorkView/ViewLogic and XACT 5.1. (On the other hand, booting down to DOS to get DOS WorkView is so cumbersome, and so unproductive (you lose multitasking with long running pprs), that I rarely use WorkView, and instead express my designs as C++ programs, building up designs from some net, gate, and 'XNF primitive' classes that I wrote.) (By the way, the XACT 5.1 tools also run under Windows NT, assuming you invest the time necessary to obtain, install, and configure the security key device driver.) Jan Gray Redmond, WAArticle: 2115
I need to programm "one" AMD MACH-435 and I would like to know if somebody have perform this task with a self build programmer. If so or if you know the algorithm which must be applied, please e-mail me. Guy LEONHARD e-mail: Guy.Leonhard@enst-bretagne.frArticle: 2116
I need to programm "one" AMD MACH-435 and I would like to know if somebody have perform this task with a self build programmer. If so or if you know the algorithm which must be applied, please e-mail me. Guy LEONHARD e-mail: Guy.Leonhard@enst-bretagne.frArticle: 2117
billw@puli.cisco.com (William ) wrote: >I do have an interesting story regarding this sort of thing. I was trying >to do my physics homework with a classmate on the university computers >(using APL as a programmable calculator, I think.) We had an IBM clone, >with its BCD mantissa and exponent, but it didn't have enough precision (I >forget what the actual problem was.) So we moved over the the DEC-10, >which has binary exponent and mantissa, but it didn't have the range >(couldn't even get h-bar squared!) A quick look a MACSYMA over the net at >MIT yielded info that there was infinite precision arithmetic available, if >only we could figure out how to use it. Sigh. I think we ended up on a >hand-held calculator. Actually running into the limitations of a computer >architecture sure teaches you a lot more than the architecture classes! > > In 1969 I took a frosh chem class that required we write a program to calculate the pH of a solution as 1 ml drops of a base are added to the solution. No brainer - done in an hour kind of assignment. Of a class of 200, only 2 of us got it. Both of us had to talk to the prof (separately). I was looking at a printout of my results as the prof was working on a fancy device called a HP programmable caculator. Very, very rare in those days! Our results went lock step up to a pH of about 6.9 and then we went different ways. My single precision variables dropped out and his 48 bit variables held on. It was my first year writing code and it was my first lesson in single versus double precision. I think it was the prof's as well. We both realized what the problem was at the same time. Instead of telling the class that they would need to use double precision variables to solve the problem, the problem was dropped as a requirement. Sigh - all those hours for nothing except a personal lesson in double precision variables. -- ____________________ This message has been spell checked. Any spell airs are do too editions two dictionary.Article: 2118
Can someone give me a pointer to a location describing the Library of Parametrized Modules format and design style? I am familiar with Xilinx XBLOX only. Also, is it possible to instantiate/generate new LPMs from within VHDL? Which vendors support LPMs in their P&R tools? Thanks in advance, Dimitris Phoukas VLSI Research Group, University of Windsor -- Dimitris Phoukas University of Windsor VLSI Research Group Windsor, ONT, N9B 3P4 CANADAArticle: 2119
In article <460a2b$vrg@melimelo.enst-bretagne.fr>, Guy LEONHARD <leonhard> wrote: >I need to programm "one" AMD MACH-435 and I would like to know if somebody have >perform this task with a self build programmer. If so or if you know the >algorithm which must be applied, please e-mail me. AMDs MachXL Software and Downloading cable are free, just call them and ask for it - Toll Free number in France is 0590-8621 (listed on back of AMDs MachXL data book. **************************************************************************** Dan Bartram, Jr. Work: (404) 894-7107 Research Engineer FAX: (404) 894-7080 Georgia Institute of Technology Atlanta, GA 30318 Internet: dan.bartram@.gtri.gatech.edu ****************************************************************************Article: 2120
irharris@comp.brad.ac.uk (Ian Harrison) writes: >Right. I've got a challenge for all you boffins out there. See if you can >get these questions correct: (Correct answers will be posted on 15/10/95) >1. Give the IBM floating-point representations for decimal 55.4 and -53.4 >2. Give the IEEE standard single-precision floating-point representations >for +29 and -29 >3. Compare the ranges, accuracy, and other system design considerations >for the preceding two floating-point number systems. >4. Write all 4-bit 2s compliment numbers (that is, sign plus 3-bit >numbers) and their decimal values. Show that negative numbers exceed >positive numbers by one. Consider 0 to be either -ve or +ve. >5. How many different numbers can be stored in a set of four switches, >each having three different positions (four three-position switches)? Do your own homework, boy. How are you supposed to learn if we feed you all the answers? -DaveArticle: 2121
Hi I'm trying to get a 480Khz ceramic resonator to work with the internal oscillator module of an xc3030APC44. I have gotten crystals to work (i.e. I know about the -S1 flag to makebits). Is 480Khz too low ? The module is spec'ed for 1-20Mhz. What values of R1 (1Mohm), R2 (0), C1/C2 (220pF) should I be using ? Any ideas ? Thanks, -ingo -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */Article: 2122
Dimitris Phoukas (dimitris@engn.uwindsor.ca) wrote: : Can someone give me a pointer to a location describing the Library of : Parametrized Modules format : and design style? I am familiar with Xilinx XBLOX only. : I attended the Altera Flex10K seminar and they talked a lot about LPM. They claim their tools MaxplusII is supporting LPM so you can instantiate modules from the library in your VHDL say on Mentor and still get optimized logic. They say they plan to migrate the LPM to VHDL in the future. Regards Kayvon Irani Los AngelesArticle: 2123
In article <45pkld$753@news.Belgium.EU.net>, jand says... > >ekatjr@eua.ericsson.se (Robert Tjarnstrom) wrote: > >>Currently microprocessors perform about 5 times better than ASIC design, although >>using comparable manufacturing technology. What is the poor process utilization >>due to? >> >Maybe it's because increasing the clock frequency of a uP is one of only >methods >left to speed up the Von Neumann bottleneck (before more radical architectural >changes, such as computing with programmable logic, become unavoidable), making >it worthwhile to throw development money and power dissipation at it? Maybe uP >designers have been unexpectedly succesful to do this, perhaps because they are >increasingly applying ASIC design techniques such as timing-driven logic >synthesis? > >>Will a move to "higher abstraction levels" increase or decrease the gap? >The only significant influence should be on design time (otherwise such >a move is not acceptable). > >Regards, Jan > The Von Neumann architecture, while historically the main architecture used for microprocessors, cannot really be attributed to processors like the PowerPC or the Pentium as their architectures go a little beyond this due to on chip memory cache, the reason that ASICs often perform better than microprocessors is because they are usually designed for specific applications, while microprocessors must be tailored for the application- not altogether possible in some cases as a result of their architecture which can involves pipelines which aren't always fully pipelined (depending on what instruction they are executing). Generally, while a microprocessor may have a faster clock speed what is achieves in 5 instructions an ASIC can be designed to achieve it in one, bang goes the speed considerations.Article: 2124
Hi all, is there anyone, who has tried to hack the internal configuration memory structure of Xilinx FPGA's? Thanks
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z