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Jeffrey LIU <liu57221@ms5.hinet.net> wrote in article <6vtb9s$fv7@netnews.hinet.net>... > Jeffrey G.S. LIU wrote : > Altera has source code about PCI controller (both master and target mode). > I've use the Altera CPLD to implement PCI master and target. How big was this CPLD? What part did you use? The only PCI interface they list for a CPLD (which would the MAX devices) at this URL: http://www.altera.com/html/mega/mega_pci-function.html And if you follow the ONLY MAX link to a 32 bit PCI implementation, they don't list the MAX there, they say to contact the 'partner', and it's not by Altera...so you'd have to pay for it. I can't find the one you reference you used... Would you please elaborate on this? Thank you, Austin Franklin darkroom@ix.netcom.comArticle: 12576
Help! I have used Altera's "genmem" to create a RAM. The output files were: 1. syn_ram_8x14_irou.v which contains the Verilog simulation model and the RAM instantiation for Synopsys synthesis. 2. syn_ram_8x14_irou.lib which is to be (somehow) inserted to the flex10k-2.db library. I tried doing a read_lib syn_ram_8x14_irou.lib unsuccesfully. Aparently it needs a library header to be able to load. I could not find an app-note for this in the Altera web site. Thanks in advance for your help...Article: 12577
Have you set all the o/ps as Fast ? It might be an idea to limit the slew rate if you haven't done so already. channing-wen@usa.net wrote in message <70690b$jk7$1@nnrp1.dejanews.com>... >I move a design to the Xilinx XC95144-TQ100, but I cannot bear the current >when it work, its about 220mA, could anybody tell me if somewhere is wrong >and how to deal with this? > >Thanks. > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12578
leslie.yip@asmpt.com wrote:
> if ADDR >= x"D4000" and ADDR <= x"D47FF" then
> DPRA <= '1';
> elsif ADDR >= x"D4800" and ADDR <= x"D4FFF" then
> RAMCE <= '1';
> elsif ADDR >= x"DB000" and ADDR <= x"DB7FF" then
> DPRB <= '1';
> end if;
If I may add my two cents worth and possibly learn something from
someone else...
I would guess (since I have not tried it) that by constructing your
comparisons with arithmetic operators you will produce hardware using
adder type circuits. In each case above you could simplify the test to
an equivalence between the upper ranges of bits in the address.
For example (also correcting for the difference in bit widths)...
if ADDR = x"1A8" then
DPRA <= '1';
elsif ADDR = x"1A9" then
RAMCE <= '1';
elsif ADDR = x"1B6" then
DPRB <= '1';
end if;
Does anyone know if the use of the arithmetic operator will actually
produce adder type circuits in this case? Or will a synthesizer be able
to figure out that this is the same as the equivalence operator using
only the upper bits?
--
Rick Collins
redsp@XYusa.net
remove the XY to email me.
Article: 12579Your VHDL code is alright and would compile nicely under Active-VHDL (from Aldec). I am pretty sure that Aurora doesn't know to interpret constant bit_vectors in the format x"D400". I've already encountered some compiliers/synthesizers which can only accept binary based constant vectors such as "1101010000000000".. Try removing that x prefix and changing the radix of the comparison. -- Yours, - Ido Kleinman. kleinn@REMOVETHIS.mail.biu.ac.il ** Please delete the "REMOVETHIS." ** substring to EMail me. leslie.yip@asmpt.com wrote in message <706oci$9uo$1@nnrp1.dejanews.com>... >Hello Everybody, > >I would like to know what is worng with the ViewLogic's Synthesizer "Aurora" >to interpret the following code. > >The error message is as follows: > >The following is a list of the navigable error/warning messages in the >preceding run. Double clicking on a message will bring up the Viewer with the >cursor positioned at the offending line of code. VHDL: Error: >d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 28: impossible to determine the type >of this parameter VHDL: Error: d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 30: > impossible to determine the type of this parameter VHDL: Error: >d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 32: impossible to determine the >type of this parameter End navigable error/warning messages. >Article: 12580
Hi, I am also looking for a PCI implementation for free or cheap. I am using Xilinx devices. I can tweak any ABEL or HDL code to make it work on my device. I just don't want to re-invent the wheel by starting from scratch. Any help would be greatly appreciated. -- Jason CaulkinsArticle: 12581
Hello to all experienced designers ! I work as a teacher in a so called "technical highschool" - it's difficult to translate as i believe that this kind of school is specific in our country (Austria). Our Students start in the age of 15 and when they leave at 20, they can go to Univerity or directly start with a job as an electronics engeneer or service technician. Now my question to the group. I started with PLDs 4 years ago: 22V10, XC3020 and now XC9500. I found it very simple (and cheap) to work with easyABEL, XABEL or Foundation Base. We do all kind of decoders, arithmetics, uC-interfaces, counters (eg. the gray example - recently discussed here), timers, shift registers, fsm (traffic light, key lock) and so on: We do the design and verify it by "hands on" hardware tests. At the moment, the emphasis is mostly on the methods of logic thesign, less than on optimization and timing analysis, as we have only 8 ... 12 hours time to spend in the lab for that item. For that needs, ABEL and the above tools seemed sufficient to me - but: when i follow the discussions in this group, i hear only about VHDL. I had a look at VHDL, but it seemed me to complex to do it in that short time with 18...19 old boys. I believe that ABEL can give them a rough idea, what logic design looks like - but the real work starts at their jobs. We have sometime controversial discussions about that and so i would appreciate much, to learn some opinions of people "at work": ABEL versa VHDL / Verilog ? More Simulation, Timing anlysis ? CPLD versa FPGA ? A lot of questions - i know ... Thanks for your help, Bertram -- Bertram Geiger, bgeiger@EUnet.at HTL Bulme Graz-Goesting - AUSTRIAArticle: 12582
Hello, The Lucent ORCA3 FPGAs implement two on-chip PLLs that can be programmed thru a parallel port to multiply(up to 64 times) or divide clocks. Hope this will help. Regards FBArticle: 12583
Ido Kleinman schrieb in Nachricht <70abgn$d38$1@news.inter.net.il>... >Your VHDL code is alright and would compile nicely under Active-VHDL (from >Aldec). >I am pretty sure that Aurora doesn't know to interpret constant bit_vectors >in the format x"D400". I've already encountered some compiliers/synthesizers >which can only accept binary based constant vectors such as >"1101010000000000".. Try removing that x prefix and changing the radix of >the comparison. > >-- > >Yours, > > - Ido Kleinman. > kleinn@REMOVETHIS.mail.biu.ac.il > Hi, I'm just not find the original message, but I think main problem is how to get the compiler detect "D400" als Hex-value. Well here's a solution that works fine with ALTERA Max+PlusII: 16#D400# This determines that the value between ## is Base 16. Work's fine with comparisons like if Vector = 16#D400# then.... What does not work is Vector <= 16#D400#. This must be formulated (AFAIK) as Vector <= CONV_STD_LOGIC_VECTOR(16#D400#,16). Well above line is not quite shorter than assigning "1101010000000000" but more readable =8-) Tschuessing, CarlhermannArticle: 12584
Bertram Geiger wrote: > ABEL versa VHDL / Verilog ? In my opinion, your intent is to introduce logic design. ABEL is more than good enough for this. ABEL is probably easier to teach than VHDL/Verilog. Once the students have the basics of ABEL, learning VHDL and/or Verilog will be easier. > More Simulation, Timing anlysis ? Keep it simple and hands on. Once the students have seen a device function correctly or not, simulation and timing analysis will make more sense. Perhaps more if the device did not function as planned. > CPLD versa FPGA ? What is the easiest to set up in the lab? Socketed DIP 22V10, perhaps, in-circuit programable CPLDs or FPGAs, maybe, anything that requires fine pitch parts or anything easy to break, no. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 12585
I have a high end logic/cpu lab at
http://www.tefbbs.com/spacetime/index.htm
the price is right in my opinion but check it out and decide for
yourself.
There are links to other FPGA boards at the above site.
Simon
===========================================================
Bertram Geiger <bgeiger@EUnet.at> wrote:
>Hello to all experienced designers !
>
>I work as a teacher in a so called "technical highschool" - it's
>difficult to translate as i believe that this kind of school is specific
>in our country (Austria). Our Students start in the age of 15 and when
>they leave at 20, they can go to Univerity or directly start with a job
>as an electronics engeneer or service technician.
>
>Now my question to the group. I started with PLDs 4 years ago: 22V10,
>XC3020 and now XC9500. I found it very simple (and cheap) to work with
>easyABEL, XABEL or Foundation Base. We do all kind of decoders,
>arithmetics, uC-interfaces, counters (eg. the gray example - recently
>discussed here), timers, shift registers, fsm (traffic light, key lock)
>and so on: We do the design and verify it by "hands on" hardware tests.
>
>At the moment, the emphasis is mostly on the methods of logic thesign,
>less than on optimization and timing analysis, as we have only 8 ... 12
>hours time to spend in the lab for that item.
>
>For that needs, ABEL and the above tools seemed sufficient to me - but:
>when i follow the discussions in this group, i hear only about VHDL.
>I had a look at VHDL, but it seemed me to complex to do it in that short
>time with 18...19 old boys.
>I believe that ABEL can give them a rough idea, what logic design looks
>like - but the real work starts at their jobs. We have sometime
>controversial discussions about that and so i would appreciate much, to
>learn some opinions of people "at work":
>ABEL versa VHDL / Verilog ?
>More Simulation, Timing anlysis ?
>CPLD versa FPGA ?
>
>A lot of questions - i know ...
>
>
>Thanks for your help, Bertram
>
>
>--
>Bertram Geiger, bgeiger@EUnet.at
>HTL Bulme Graz-Goesting - AUSTRIA
>
Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12586This is a multi-part message in MIME format. --------------963C854F5D2116E7F2CD0D5B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dan Kuechle wrote: > Many thanks to all who responded. For my application, a fast carry binary > counter followed by a registered xor array to convert binary to gray code > will work beautifully. I didn't realize the conversion from binary to gray > code was so simple: sorry i came into this thread late. yes it is simple to convert binary to gray. it is not simple to go the other way (as others have mentioned) because the conversion takes a chain of XORs. also, it is not trivial to do arithmetic (add/sub/mult/div) on gray coded numbers because it involves TWO carry chains. however, back to the original question, i previously posted a gray code counter written in AHDL (Altera's language) which uses the carry chain. i'll include the code below again.... conversion to xilinx should be simple. the reason this design is better than a binary counter converted to gray code was already mentioned: you don't want the outputs to glitch too much (eg in building FIFO pointers). --------------963C854F5D2116E7F2CD0D5B Content-Type: text/plain; charset=us-ascii; name="graycnt.tdf" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="graycnt.tdf" % Gray Code Counter ----------------- a gray code counter % PARAMETERS ( L = 16 ); SUBDESIGN graycnt ( clk : INPUT; cnt_en : INPUT; aclr : INPUT = GND; sclr : INPUT = GND; q[L-1..0] : OUTPUT; ) VARIABLE P : TFFE; G[L-1..0] : TFFE; tin[L-1..0] : NODE; cin[L-1..0] : CARRY; BEGIN P.clk = clk; P.clrn = !aclr; G[].clk = clk; G[].clrn = !aclr; P.t = !sclr # (sclr & P.q); P.ena = cnt_en # sclr; cin[0] = P.q; tin[0] = !P.q; FOR I IN 0 TO L-2 GENERATE G[I].t = (!sclr & tin[I]) # (sclr & G[I].q); G[I].ena = cnt_en # sclr; cin[I+1] = cin[I] & !G[I].q; tin[I+1] = cin[I] & G[I].q; END GENERATE; G[L-1].t = (!sclr & (tin[L-1] # cin[L-1])) # (sclr & G[L-1].q); G[L-1].ena = cnt_en # sclr; q[] = G[].q; END; --------------963C854F5D2116E7F2CD0D5B--Article: 12587
ems@nospam.riverside-machines.com wrote: > there's no need to shout. i said in my original post, in another > thread, that i wasn't a viewsim expert. if you want to correct some of > the fine details of my understanding, then i'm grateful for it. > however, it seems to me that the only difference between my scripts > and yours is that you call other scripts from your script. however, > without parameter passing, this is of little use. > But viewsim does support parameter passing, and I use that feature extensively. > the issue is simulation. you've mis-quoted me, more than once, and > you're going off topic. the web site says nothing about not being able > to *design* virtexes with schematics; philip also specifically states, > or implies, that you can do it. You can in fact capture the design for virtex using a schematic, but the current release has only the schematic symbols with no simulation models except for the unified library components. This means that the schematic users effectively either have to avoid using those components or must write their own sim models for them. Neither of these options are palatable. I, and others have voiced our complaints to Xilinx. Please, if this issue pisses you off as much as it does me, let Xilinx know LOUDLY. The fact of the matter, is that by eliminating the simulation models, a useful design tool that is a crucial part of some people's very successful methodology is also eliminated. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12588
In those cases where I know exactly what the circuit topology needs to be for the best performance or area, I find it is considerably quicker to enter exactly what I want on a schematic than to coerce the synthesis engine into producing the logic I desire. The worst part is that the results are compiler dependent, even between different revs of the same compiler! This may be fine if you are not pushing the performance or density of you part, but in many of the cases I am working with I don't have that option. Unfortunately, the tools are not always smart enough to choose the right design without an inordinate amount of code and constraint tweaking. > Constraints help it understand the designers intent. And if the synthesis > tool is smart enough, it is able to see what the timing constraints are and > choose its topology (say, for your counter example) that'll meet that > constraint. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12589
Bruno Fierens wrote: > > We are developing a high bandwidth switch architecture and we need to > >test each switch interface at maximum speed of 100MB/s, which with an > >8-bit interface requires a clock of 100MHz. Is there any FPGA out > >there that would be able to sustain pumping data at this rate? I > >thought of using a slower clock and a 32-bit interface from the FPGA > >and then probably use a CPLD to multiplex the data to the switch 8-bit > >interface. But there are problems associated with this. Any > >suggestions? > > If you do the design(s) carefully with regard to the FPGA architecture, this is possible to do even 8 bit arithmetic stuff in an XC40xxE-2 part at 100Mhz, but you will probably not get there with synthesis. If you are going to use synthesis without low level structural coding, expect to have to use one of the fastest speed grades (-08 or -09) and perhaps a larger part. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12590
Le mer Michel wrote: > I have a 600 logic cell design with many bound test of counter done in > parallel. I use VHDL tools. The > design reaches only 30 MHz. How could I optimize the fpga? (I have > already tried to use the maximum > of Vendor's function for the target). > > Michel. You need to understand the device architecture and how your desired logic should fit into that architecture to obtain a more efficient implementation. Once that is understood, you need to massage the code so that it generates the logic you already know would be an efficient implementation. FWIW, I usually use schematics in cases like this, since I already know what the circuit needs to look like to obtain the desired performance. Some of the specific items to do are level compression, pipelining, rearranging your algorithms, registering I/Os, applying timing constraints, and hand-placing the design. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12591
Note that the conversion from gray to binary involves a reverse carry. This can be restated in the form of a merged tree with a delay of o(log(n)) instead of o(n). -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12592
Hello Everybody
I think that this is technology-declining that ViewLogic can't know how to
synthesize the code. In the past time, (ten or more years ago) the CUPL can
synthesize it into P22V10 or 16V8 PAL/GAL devices. I can't understand how
ViewLogic can't know that.
The synthesized result should be similar to that as follows:
-- Mem_dec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity MEM_DEC is
port( ADDR: in std_logic_vector(19 downto 11);
NMEMR,NMEMW: in std_logic;
-- NRST: in std_logic;
RAMCE: out std_logic;
DPRA,DPRB: out std_logic);
end MEM_DEC;
architecture MEM_DEC_ARCH of MEM_DEC is
-- signal dint,ddint: std_logic;
-- signal rint,fint: std_logic;
begin
process(ADDR, NMEMR, NMEMW)
begin
DPRA <= '0';
DPRB <= '0';
RAMCE <= '0';
if NMEMR='0' or NMEMW='0' then
if ADDR = "110101000" then
DPRA <= '1';
elsif ADDR = "110101001" then
RAMCE <= '1';
elsif ADDR = "110110110" then
DPRB <= '1';
end if;
end if;
end process;
end MEM_DEC_ARCH;
----------------------------------------------------------------
In article <70abgn$d38$1@news.inter.net.il>,
"Ido Kleinman" <kleinn@REMOVETHIS.mail.biu.ac.il> wrote:
> Your VHDL code is alright and would compile nicely under Active-VHDL (from
> Aldec).
> I am pretty sure that Aurora doesn't know to interpret constant bit_vectors
> in the format x"D400". I've already encountered some compiliers/synthesizers
> which can only accept binary based constant vectors such as
> "1101010000000000".. Try removing that x prefix and changing the radix of
> the comparison.
>
> --
>
> Yours,
>
> - Ido Kleinman.
> kleinn@REMOVETHIS.mail.biu.ac.il
>
> ** Please delete the "REMOVETHIS."
> ** substring to EMail me.
>
> leslie.yip@asmpt.com wrote in message <706oci$9uo$1@nnrp1.dejanews.com>...
> >Hello Everybody,
> >
> >I would like to know what is worng with the ViewLogic's Synthesizer
> "Aurora"
> >to interpret the following code.
> >
> >The error message is as follows:
> >
> >The following is a list of the navigable error/warning messages in the
> >preceding run. Double clicking on a message will bring up the Viewer with
> the
> >cursor positioned at the offending line of code. VHDL: Error:
> >d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 28: impossible to determine the
> type
> >of this parameter VHDL: Error: d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 30:
> > impossible to determine the type of this parameter VHDL: Error:
> >d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 32: impossible to determine the
> >type of this parameter End navigable error/warning messages.
> >
>
>
The code:
--------
-- Leslie Yip, ASM; Jun, 8, 1998
-- Mem_dec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity MEM_DEC is
port( ADDR: in std_logic_vector(19 downto 11);
NMEMR,NMEMW: in std_logic;
-- NRST: in std_logic;
RAMCE: out std_logic;
DPRA,DPRB: out std_logic);
end MEM_DEC;
architecture MEM_DEC_ARCH of MEM_DEC is
-- signal dint,ddint: std_logic;
-- signal rint,fint: std_logic;
begin
process(ADDR, NMEMR, NMEMW)
begin
DPRA <= '0';
DPRB <= '0';
RAMCE <= '0';
if NMEMR='0' or NMEMW='0' then
if ADDR >= x"D4000" and ADDR <= x"D47FF" then
DPRA <= '1';
elsif ADDR >= x"D4800" and ADDR <= x"D4FFF" then
RAMCE <= '1';
elsif ADDR >= x"DB000" and ADDR <= x"DB7FF" then
DPRB <= '1';
end if;
end if;
end process;
end MEM_DEC_ARCH;
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 12593Nobody's stopping your move up here. We certainly do not have the equivalent to the anti yankee stuff you find in Texas. You know the "freeze a Yankee drive 95" bumper stickers, and the yankee with a U-Haul jokes etc! :-). I think I'll pass on the beer flavored ice cream. Wallace V Rose wrote: > Ah all you guys on the east cost have all the luck. You get all the brains, > all the money and the best places to live. In Texas, we have the > greatest.......................man made brown water lakes and wide open > spaces. As for the "ice-cream and hamburgers", the best I can do from here > is give you the recipe for beer flavored ice-cream. It's a redneck tradition > to share it with your friends. Its one part vanilla and a 6 pack of colt-45. > Dont make the mistake of putting a 45 revolver in the ice-cream (it a common > mistake down here). > Well, " Yippee Yi Yo " and "Howdy Dookie" to you and thanks for the > help. > jungleman -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12594
the tools simply are not smart enough for many tasks. and by looking at the output of the synthesis engines for many of the manufacturers, make sure to check the revision, and make sure to check the exact compiler options, you will find a lack of consistency and a lot of stupid circuits. if you have plenty of gates, time, and power, for many cases HDL's are a better design option. for pushing speed, density, or power, it is simply, with today's technology, easier to draw a schematic. while constraints help guide a tool, they can not replace circuit architectural decisions, currently still a domain where the humans have the edge over the synthesizer. rk ======================================================= Ray Andraka wrote: > In those cases where I know exactly what the circuit topology needs to be for > the best performance or area, I find it is considerably quicker to enter exactly > what I want on a schematic than to coerce the synthesis engine into producing > the logic I desire. The worst part is that the results are compiler dependent, > even between different revs of the same compiler! This may be fine if you are > not pushing the performance or density of you part, but in many of the cases I > am working with I don't have that option. Unfortunately, the tools are not > always smart enough to choose the right design without an inordinate amount of > code and constraint tweaking. > > > Constraints help it understand the designers intent. And if the synthesis > > tool is smart enough, it is able to see what the timing constraints are and > > choose its topology (say, for your counter example) that'll meet that > > constraint.Article: 12595
rk <stellare@NOSPAMerols.com> writes: > many cases HDL's are a better design option. for pushing speed, > density, or power, it is simply, with today's technology, easier to > draw a schematic. I don't know about density or speed, but I am absolutely certain that doing things like clock gating with schematics is enormously (sp?) inefficient. Power Compiler is smart enough to do this for me. > while constraints help guide a tool, they can not replace circuit > architectural decisions, currently still a domain where the humans > have the edge over the synthesizer. If you have not put your architectural decisions into your VHDL code, it probably won't be synthesizable. If it is, then you have not written it right. If you mean what kinds of adders to use to minimize power, Synopsys has something called Designware. You can put your low-power carry save adders in there. Power Compiler will then help choose the implementation with the lowest power usage that still meets timing. Better yet: Just say which adders you prefer to Design Compiler. Works as a charm. GeirArticle: 12596
Hi.
I have no experience with Altera rams, but from question i can guess
that the command you should try in order to read the ram is:
update_lib <altera library name> syn_ram_8x14_irou.lib
You can find out the library name using 'list -libraries' command.
Doron.
SFCFM Volunteer wrote:
> Help!
>
> I have used Altera's "genmem" to create a RAM.
> The output files were:
>
> 1. syn_ram_8x14_irou.v which contains the Verilog
> simulation model and the RAM instantiation for
> Synopsys synthesis.
>
> 2. syn_ram_8x14_irou.lib which is to be (somehow)
> inserted to the flex10k-2.db library.
>
> I tried doing a read_lib syn_ram_8x14_irou.lib
> unsuccesfully. Aparently it needs a library header
> to be able to load. I could not find an app-note for
> this in the Altera web site.
>
> Thanks in advance for your help...
--
-----------------------------------------------------------------------------
Doron Nisenbaum
_/_/_/ _/_/_/_/ _/
_/ _/ _/
_/ _/_/_/ _/ Chip Express (Israel) LTD.
_/ _/ _/ P.O.Box 2401
_/_/_/ _/_/_/_/ _/_/_/_/ Advanced Technology Center
Haifa , Israel 31024
Chip Express Israel Tel: +972-4855-0011 Ext. 240
-------------------------------- Fax: +972-4855-1122
The ASIC Time-to-Market Solution E-Mail: doron@chipx.co.il
http://www.chipexpress.com
-----------------------------------------------------------------------------
Article: 12597
Leslie,
For decoding I like to use concurrent statements(instead of a process) for a number
of reasons
including, 1)don't have to worry about sensitivity lists and 2)decoding is more
readable(IMHO) using concurrent statements...
eg...
constant DPRA_SEL:std_logic_vector(8 downto 0):="110101000";
constant DPRB_SEL:std_logic_vector(8 downto 0):="110110110";
constant RAM_SEL:std_logic_vector(8 downto 0):="110101001";
DPRA <= '1' when ((NMEMR = '0') or (NMEMW = '0')) and (ADDR = DPRA_SEL) else
'0';
DPRB <= '1' when ((NMEMR = '0') or (NMEMW = '0')) and (ADDR = DPRB_SEL) else
'0';
RAMCE <= '1' when ((NMEMR = '0') or (NMEMW = '0')) and (ADDR = RAM_SEL) else
'0';
Just a matter of style...
leslie.yip@asmpt.com wrote:
> Hello Everybody
>
> I think that this is technology-declining that ViewLogic can't know how to
> synthesize the code. In the past time, (ten or more years ago) the CUPL can
> synthesize it into P22V10 or 16V8 PAL/GAL devices. I can't understand how
> ViewLogic can't know that.
>
> The synthesized result should be similar to that as follows:
>
> -- Mem_dec.vhd
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> Entity MEM_DEC is
> port( ADDR: in std_logic_vector(19 downto 11);
> NMEMR,NMEMW: in std_logic;
> -- NRST: in std_logic;
> RAMCE: out std_logic;
> DPRA,DPRB: out std_logic);
> end MEM_DEC;
>
> architecture MEM_DEC_ARCH of MEM_DEC is
> -- signal dint,ddint: std_logic;
> -- signal rint,fint: std_logic;
>
> begin
>
> process(ADDR, NMEMR, NMEMW)
> begin
> DPRA <= '0';
> DPRB <= '0';
> RAMCE <= '0';
> if NMEMR='0' or NMEMW='0' then
> if ADDR = "110101000" then
> DPRA <= '1';
> elsif ADDR = "110101001" then
> RAMCE <= '1';
> elsif ADDR = "110110110" then
> DPRB <= '1';
> end if;
> end if;
> end process;
>
> end MEM_DEC_ARCH;
>
Article: 12598Could it be that ADDR is defined to be only 9 bits and you are comparing it against 20 bits. leslie.yip@asmpt.com wrote: > Hello Everybody > > I think that this is technology-declining that ViewLogic can't know how to > synthesize the code. In the past time, (ten or more years ago) the CUPL can > synthesize it into P22V10 or 16V8 PAL/GAL devices. I can't understand how > ViewLogic can't know that. > > The synthesized result should be similar to that as follows: > > -- Mem_dec.vhd > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > > Entity MEM_DEC is > port( ADDR: in std_logic_vector(19 downto 11); > NMEMR,NMEMW: in std_logic; > -- NRST: in std_logic; > RAMCE: out std_logic; > DPRA,DPRB: out std_logic); > end MEM_DEC; > > architecture MEM_DEC_ARCH of MEM_DEC is > -- signal dint,ddint: std_logic; > -- signal rint,fint: std_logic; > > begin > > process(ADDR, NMEMR, NMEMW) > begin > DPRA <= '0'; > DPRB <= '0'; > RAMCE <= '0'; > if NMEMR='0' or NMEMW='0' then > if ADDR = "110101000" then > DPRA <= '1'; > elsif ADDR = "110101001" then > RAMCE <= '1'; > elsif ADDR = "110110110" then > DPRB <= '1'; > end if; > end if; > end process; > > end MEM_DEC_ARCH; > > ---------------------------------------------------------------- > In article <70abgn$d38$1@news.inter.net.il>, > "Ido Kleinman" <kleinn@REMOVETHIS.mail.biu.ac.il> wrote: > > Your VHDL code is alright and would compile nicely under Active-VHDL (from > > Aldec). > > I am pretty sure that Aurora doesn't know to interpret constant bit_vectors > > in the format x"D400". I've already encountered some compiliers/synthesizers > > which can only accept binary based constant vectors such as > > "1101010000000000".. Try removing that x prefix and changing the radix of > > the comparison. > > > > -- > > > > Yours, > > > > - Ido Kleinman. > > kleinn@REMOVETHIS.mail.biu.ac.il > > > > ** Please delete the "REMOVETHIS." > > ** substring to EMail me. > > > > leslie.yip@asmpt.com wrote in message <706oci$9uo$1@nnrp1.dejanews.com>... > > >Hello Everybody, > > > > > >I would like to know what is worng with the ViewLogic's Synthesizer > > "Aurora" > > >to interpret the following code. > > > > > >The error message is as follows: > > > > > >The following is a list of the navigable error/warning messages in the > > >preceding run. Double clicking on a message will bring up the Viewer with > > the > > >cursor positioned at the offending line of code. VHDL: Error: > > >d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 28: impossible to determine the > > type > > >of this parameter VHDL: Error: d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 30: > > > impossible to determine the type of this parameter VHDL: Error: > > >d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 32: impossible to determine the > > >type of this parameter End navigable error/warning messages. > > > > > > > > > The code: > -------- > > -- Leslie Yip, ASM; Jun, 8, 1998 > -- Mem_dec.vhd > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > > Entity MEM_DEC is > port( ADDR: in std_logic_vector(19 downto 11); > NMEMR,NMEMW: in std_logic; > -- NRST: in std_logic; > RAMCE: out std_logic; > DPRA,DPRB: out std_logic); > end MEM_DEC; > > architecture MEM_DEC_ARCH of MEM_DEC is > -- signal dint,ddint: std_logic; > -- signal rint,fint: std_logic; > > begin > > process(ADDR, NMEMR, NMEMW) > begin > DPRA <= '0'; > DPRB <= '0'; > RAMCE <= '0'; > if NMEMR='0' or NMEMW='0' then > if ADDR >= x"D4000" and ADDR <= x"D47FF" then > DPRA <= '1'; > elsif ADDR >= x"D4800" and ADDR <= x"D4FFF" then > RAMCE <= '1'; > elsif ADDR >= x"DB000" and ADDR <= x"DB7FF" then > DPRB <= '1'; > end if; > end if; > end process; > > end MEM_DEC_ARCH; > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12599
Carlhermann Schlehaus wrote in message <70b0b1$rla$1@news01.btx.dtag.de>...
>
>Ido Kleinman schrieb in Nachricht <70abgn$d38$1@news.inter.net.il>...
>>Your VHDL code is alright and would compile nicely under Active-VHDL (from
>>Aldec).
>>I am pretty sure that Aurora doesn't know to interpret constant
bit_vectors
>>in the format x"D400". I've already encountered some
>compiliers/synthesizers
>>which can only accept binary based constant vectors such as
>>"1101010000000000".. Try removing that x prefix and changing the radix of
>>the comparison.
>>
>>--
>>
>>Yours,
>>
>> - Ido Kleinman.
>> kleinn@REMOVETHIS.mail.biu.ac.il
>>
>
>Hi,
>
>I'm just not find the original message, but I think main problem is how to
>get the compiler detect "D400" als Hex-value.
>Well here's a solution that works fine with ALTERA Max+PlusII:
>16#D400#
>This determines that the value between ## is Base 16.
>Work's fine with comparisons like
>if Vector = 16#D400# then....
>
>What does not work is Vector <= 16#D400#. This must be formulated (AFAIK)
as
>Vector <= CONV_STD_LOGIC_VECTOR(16#D400#,16).
>Well above line is not quite shorter than assigning "1101010000000000" but
>more readable =8-)
If you define your signal Vector as an integer, then
Vector <= 16#D400#;
will work just fine.
If Vector is a STD_LOGIC_VECTOR() then you have to convert the integer
representation 16#D400# to a SLV by using the CONV_ function.
-a
--
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520-318-8191
apeters@noao.edu
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