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You may find that the 12ns SRAM is somewhat harder to get. I suggest using a SSRAM. If you need fast larger mememory, don't use DRAM it is way to slow. Even the frame memory is pretty slow. You could use SDRAM, it is very cheap and fast. Also, the controller is as complex as the DRAM. The SDRAM is avaliable in speed greater than 100MHz. I've coded several design in a FLEX10k50 which runs at 65MHz.Article: 8001
Cristiano Miani wrote: > > Hi out there, > I'm sorry to bother you with such a silly question, but I've tried many > times to download the entry level software from Lattice semiconductor to > program the simplest Lattice PLD's (Es. 1032), but I didn't succeed and > I'd like to ask you if you can give me sone address or some way to > download them from somewhere else. Sine I'm in europe, I think that the > connection to the Lattice site is so slow that it's not reliable. > > Thanks in advance > Cristiano Miani they give away this, along with a stripped down version of data io's synario and abel, along with data sheets,ap notes ect.... just get hold of their nearest distributor and ask for one... bob engle embedded solutions rengle@ix.netcom.comArticle: 8002
Consider this excerpt from a running design. I believe that it will do
what you want.
First, declare the state machine, and some labels that will allow you
to easily refer to the various states.
"state assignments
state_reg = [q3,q2,q1,q0];
idle = [ 0, 0, 0, 0];
decode = [ 0, 0, 0, 1];
fs_0 = [ 0, 0, 1, 0];
fs_1 = [ 0, 0, 1, 1];
fs_2 = [ 0, 1, 0, 0];
fs_3 = [ 0, 1, 0, 1];
fs_4 = [ 0, 1, 1, 0];
sram = [ 0, 1, 1, 1];
ps_0 = [ 1, 0, 0, 0];
ps_1 = [ 1, 0, 0, 1];
ps_2 = [ 1, 0, 1, 0];
idle_ = state_reg == idle;
fs_0_ = state_reg == fs_0;
decode_ = state_reg == decode;
fs_1_ = state_reg == fs_1;
fs_2_ = state_reg == fs_2;
fs_3_ = state_reg == fs_3;
fs_4_ = state_reg == fs_4;
sram_ = state_reg == sram;
ps_0_ = state_reg == ps_0;
ps_1_ = state_reg == ps_1;
ps_2_ = state_reg == ps_2;
Then write your output equations in terms of decoded states and other
signals, or just decode the state to generate the output.
equations
state_reg.clk = clock;
!ack = (sram_ # fs_4_ # ps_2_);
!cycle = (idle_);
!pio_rd = ((fs_0_ & pio_read)
# (fs_1_ * pio_read)
# (fs_2_ & pio_read)
# (fs_3_ & pio_read)
# (fs_4_ & pio_read));
!pio_wr = ((fs_0_ & pio_write)
# (fs_1_ & pio_write)
# (fs_2_ & pio_write)
# (fs_3_ & pio_write)
# (fs_4_ & pio_write));
!sio_rd = ((fs_0_ & sio_read)
# (fs_1_ & sio_read)
# (fs_2_ & sio_read)
# (fs_3_ & sio_read)
# (fs_4_ & sio_read));
!sio_wr = ((fs_0_ & sio_write)
# (fs_1_ & sio_write)
# (fs_2_ & sio_write)
# (fs_3_ & sio_write)
# (fs_4_ & sio_write));
Then, your state diagram is pure logic. Don't try to decode outputs
inside the state diagram.
state_diagram state_reg
state idle: if start then decode " begining of a bus cycle
else idle;
state decode: if sram_block then sram " is access for sram?
else if psram_block & speed0 then ps_2 " how about
psram?
else if psram_block & speed1 then ps_2 " how about
psram?
else if speed3 then fs_3
else fs_1; " all other devices use slow
timing
state fs_0: goto fs_1; " first transition
unconditional
state fs_1: if speed3 then fs_4 " for high speed skip next
two states
else fs_2;
state fs_2: if speed1 then fs_4 " for medium speed skip next
state
else fs_3;
state fs_3: goto fs_4; " finish up for slow devices
state fs_4: if !blast then idle " terminate xfer if blast is
active
else fs_0;
state sram: if !blast then idle " sram is always single cycle
else sram;
state ps_0: if speed3 then ps_1
else ps_2;
state ps_1: goto ps_2;
state ps_2: if !blast then idle
else ps_0;
Hope this helps.
Tim Olmstead
webmaster of the CP/M Unofficial web page
email : timolmst@cyberramp.net
http://cdl.uta.edu/cpm
Article: 8003Darxus wrote in message ... | |I know very little about FPGAs, and I wish to remedy this. | |I believe this technology may be within my price range, in fact, it may be |possible for me to be able to get a setup with a number of these chips. | [snip] I would recommend visiting The Programmable Logic Jump Station at http://www.optimagic.com . It has a comprehensive set of links to most sites related to programmable logic including the device vendors, design software, on-going academic and industrial research, newsgroups, books, boards, consultants, etc. | | |From what I have found, it seems that Xilinx makes good chips, but I do |not know if there are commercially available PCI cards available with |these chips. If not, I am willing to get some schematics an learn to |build a PCI card of my own. You can find a variety of FPGA boards, including PCI cards, listed at http://www.optimagic.com/boards.html . | [snip] | |I like what I've heard of this technology, and it blows my mind that it is |not much more commonplace. I agree wholeheartedly! |Any and all information you can give me on where I can get this stuff, how |much this technology will cost me, how much power I can get for this cost |(I'm looking for around $500 ?), and what I can do with it -- and how I |can learn how to do what I can do with it, will be most greatly |appreciated. | Most of the available design software will cost you between $1,000 and $5,000 and is available on Windows and UNIX on various platforms (the specifics depend a lot on the vendor). A list of available software is at http://www.optimagic.com/software.html . Specifics about the platforms supported are at http://www.optimagic.com/cae_a_m.html . Some vendors also provide free or low-cost versions of the software for evaluation purposes. See http://www.optimagic.com/lowcost.html for more information. ----------------------------------------------------------------------- Steven K. Knapp 'Great designs happen "OptiMagic"-ally' OptiMagic, Inc. E-mail: sknapp@optimagic.com Web: http://www.optimagic.com Phone: 1-408-454-1811Article: 8004
Zhi Ye wrote in message <345E2DA1.7FD8@ece.nwu.edu>... |Hi, | I'm going to work on some compiler, the goal is to make a C program |run on a FPGA integrated system. You may want to study or extend one of the various 'C' compilers already available for FPGAs. See: GigaOps XL Compiler (XC): http://www.reconfig.com/giga/xc_ic.htm Embedded Solutions' Handel-C: http://www.embedded-solutions.ltd.uk/ProdApp/handelc.htm The Handel Language: http://www.comlab.ox.ac.uk/oucl/users/ian.page/handel/handel.html Transmogrifier C: http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc/ | As I see it,I have some questions: | 1. What is going on with FPGA integrated system now? Is there any |product ? | (What I mean by 'FPGA integrated system', is some computer with a |CPU and a FPGA, the CPU can dynamicly change the FPGA's function, |ie:when CPU tries to run a MPEG program, the FPGA can be a MPEG |card;when CPU tries to run a JPEG program, the FPGA can then be a JPEG |card.) I believe that what you mean by 'FPGA integrated system' is something generically called 'reconfigurable computers.' There are a few listed on The Programmable Logic Jump Station at http://www.optimagic.com/boards.html . You can also review some of the university and industry research at http://www.optimagic.com/research.html . In specific, there are reconfigurable computing boards/systems available from: GigaOps: http://www.reconfig.com/giga/gigahmpg.htm Virtual Computer Corp.: http://www.vcc.com/ Annapolis Microsystems: http://www.annapmicro.com/ Embedded Solutions: http://www.embedded-solutions.ltd.uk/ List of FPGA-Based Computing Machines: http://www.io.com/~guccione/HW_list.html |2. How to change the function of a FPGA? How long does it take? Is |there a standard among all the products from different companies? For SRAM-based devices, the function can be dynamically downloaded into the device via a serial data stream or a parallel data stream. Each vendor has slight differences in the interface. The downloading process takes anywhere from about 100 usec to a few hundred msec depending on the vendor and the device family. The Xilinx XC6200 FPGA family has a high-speed parallel interface that looks much like a microprocess/memory interface. See http://pw1.netcom.com/~optmagic/reconfigure/madeeasy.html . |Assume there is a function library, containing the pre-designed FPGA |configuration file for the functions. | 3. What language can I use to generate a FPGA design? There seems to |be several choices:VHDL,X-BLOX ? The preferred format is somewhat dependent on the family that you choose. Most vendors accept VHDL, Verilog, and EDIF. | 4. How can I know some more about FPGA? There is a fairly comprehensive list of related links on The Programmable Logic Jump Station at http://www.optimagic.com .Article: 8005
IIRC Xilinx have a FIFO design on their website. >Hello, can anybody make any suggestions on how best to implement a small >(5 level max.) 'psuedo' asynchronous FIFO in a Xilinx 9500 series CPLD? >I realise the FPGA architecture is better suited to this but it is to be >fitted into an existing CPLD design as a patch. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8006
The reason for this >|I like what I've heard of this technology, and it blows my mind that it >is not much more commonplace. is mainly this: >Most of the available design software will cost you between $1,000 and >$5,000 Not to mention the learning curve involved in FPGA design. To do *reliable* designs using normal logic design methods, one has to know so much about the particular device architecture. For example, in Xilinx devices one should use the global clock nets to clock everything, and use clock enables to select what actually gets clocked. This is a weird way to design logic, until you get used to it. Which is probably why so many people now use VHDL for this stuff, but that has other problems... Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8007
z80@ds.com (Peter) writes:
>The reason for this
>>|I like what I've heard of this technology, and it blows my mind that it
>>is not much more commonplace.
>is mainly this:
>>Most of the available design software will cost you between $1,000 and
>>$5,000
>Peter.
>Return address is invalid to help stop junk mail.
>E-mail replies to z80@digiXYZserve.com but
>remove the XYZ.
I agree with this... I use FPGAs and CPLD and such on a daily
basis here at school. We have several projects going on which use
Xilinx FPGAs, Altera FLEX parts, and Cypress CPLDs. Unfortunately,
once I leave school, I probably won't do much with them at all
because I can't afford the development tools. The cheap/free stuff
has such severe limitations that it isn't worth it.
The Cypress ISP FLASH CPLDs (373i, etc.) are the only ones which
have reasonably priced tool support. Warp itself isn't even all
that good as a VHDL compiler. You can almost change the organization
of concurrent processes and it compiles differently...
Anyhow, tool vendors: lower your prices!
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 8008In article <Pine.LNX.3.96.971105140201.12293A-100000@ascu.unian.it>, Massimo Baleani <mass@ascu.unian.it> writes: > We are about to design a digital reverberator on the Altera's FPGAs. > The main problem is the big amount of memory requirement (about 50K for a > stereo reverberator with a max sample rate of 48Khz). > Is there anyone who can suggest us a possible solution? External RAM?Article: 8009
On Thu, 06 Nov 1997 07:04:51 -0500, Brad Ree <NOrbreeSPAM@mindspring.com> wrote: >You may find that the 12ns SRAM is somewhat harder to get. I suggest >using a SSRAM. If you need fast larger mememory, don't use DRAM it is >way to slow. Even the frame memory is pretty slow. You could use >SDRAM, it is very cheap and fast. Also, the controller is as complex as What is SSRAM, SDRAM ? RK For EMAIL remove DELETE from the adress !Article: 8010
Reinhard Kopka <kopka@sbox.tu-graz.ac.DELETE.at> wrote in article
<346223d2.41331721@news.tu-graz.ac.at>...
> On Thu, 06 Nov 1997 07:04:51 -0500, Brad Ree
> <NOrbreeSPAM@mindspring.com> wrote:
>
> >You may find that the 12ns SRAM is somewhat harder to get. I suggest
> >using a SSRAM. If you need fast larger mememory, don't use DRAM it is
> >way to slow. Even the frame memory is pretty slow. You could use
> >SDRAM, it is very cheap and fast. Also, the controller is as complex as
>
> What is SSRAM, SDRAM ?
>
> RK
> For EMAIL remove DELETE from the adress !
>
SSRAM : Synchronous SRAM
Expensive in comparision to async SRAM.
SDRAM : Synchronous DRAM
Similar in price to standard DRAM.
Hope this helps,
Erik
Article: 8011Marc, Why not just declare ifoobar (for internal foobar) and foobar. Set foobar = !ifoobar (NOT ifoobar). This basically inverts foobar, so you only need to set foobar to 1 in state 3 (mismarked below as second state 2..but you get the idea?). That should be about the simplest way to do it. Austin Franklin darkroom@ix.netcom.com Marc Heuler <marc@aargh.mayn.de> wrote in article <TbclB*xte@aargh.mayn.de>... > I'm defining a state machine in ABEL HDL. > > Some nodes are LOW only during 1 state of 16. I have assigned the logic > level to the node during each state: > > state 0: > foobar = 1; > > state 1: > foobar = 1; > > state 2: > foobar = 1; > > state 2: > foobar = 0; > > state 4: > foobar = 1; > > state 5: > foobar = 1; > > ... > > This is very tiring and invites to forget it once, especially when adding > new nodes to the design. I have 20 or so nodes and clks that I have to > repeat all over. > > How can I tell Synario that I want foobar to be 1 anytime I don't > explicitly say otherwise? >Article: 8012
Robert E. Engle Jr. wrote: > > Cristiano Miani wrote: > > > > Hi out there, > > I'm sorry to bother you with such a silly question, but I've tried many > > times to download the entry level software from Lattice semiconductor to > > program the simplest Lattice PLD's (Es. 1032), but I didn't succeed and > > I'd like to ask you if you can give me sone address or some way to > > download them from somewhere else. Sine I'm in europe, I think that the > > connection to the Lattice site is so slow that it's not reliable. > > > > Thanks in advance > > Cristiano Miani > > they give away this, along with a stripped down version of data io's > synario and abel, along with data sheets,ap notes ect.... > just get hold of their nearest distributor and ask for one... > > bob engle > embedded solutions > rengle@ix.netcom.com Bob's talking about a CD-ROM. I got it. It's great! We're seriously looking into porting a few designs over to Lattice from Xilinx, since we can afford to keep up with the tools at this rate!Article: 8013
Brad Ree wrote: > > You may find that the 12ns SRAM is somewhat harder to get. I suggest > using a SSRAM. If you need fast larger mememory, don't use DRAM it is > way to slow. Even the frame memory is pretty slow. You could use > SDRAM, it is very cheap and fast. Also, the controller is as complex as > the DRAM. The SDRAM is avaliable in speed greater than 100MHz. I've > coded several design in a FLEX10k50 which runs at 65MHz. I mentioned the 12ns Static RAM for the sake of others who may be doing things requiring more bandwidth out of the memory. For the case discussed here, the data rate was 48KHz. Even a cheap 128K x 8 70ns SRAM would give him over 200 memory accesses per sample, including the delays to get on and off the FPGA. Use 2 successive accesses to get the 16 bits. You get a depth of 64K then, using 29 pins of the FPGA. Even with an 84 pin PLCC, you still have well over half the I/O available for other things. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8014
z80@ds.com (Peter) writes: > Not to mention the learning curve involved in FPGA design. To do > *reliable* designs using normal logic design methods, one has to know > so much about the particular device architecture. For example, in > Xilinx devices one should use the global clock nets to clock > everything, and use clock enables to select what actually gets > clocked. This is a weird way to design logic, until you get used to > it. Which is probably why so many people now use VHDL for this stuff, > but that has other problems... > If you are familiar with C programming, you might be interested in having a look at our WWW site. We have developed a language, called Handel-C, which allows to write programs that run on FPGAs. A Handel-C program is compiled and optimised into a FPGA netlist. This netlist (e.g. Xilinx XNF) can be mapped on the FPGA using the vendor's P&R tools. It is certainly a different style of FPGA development but if you are interested in Rapid Prototyping and HW/SW Codesign it's worth looking at http://www.comlab.ox.ac.uk/oucl/hwcomp.html Cheers, Matthias -- Matthias Sauer Tel +44-1865-283549 Oxford University Computing Laboratory Fax +44-1865-273839 Wolfson Bldg., Parks Road email masa @ comlab . ox . ac . uk Oxford OX1 3QD, U.K. URL: http://www.comlab.ox.ac.uk/oucl/users/matthias.sauer/Article: 8015
Hello, I'm now using Fundation design entry and M1implementation tools on XILINX XC4000 series. Where can I find any document talking about the keywords or parameters I can use in the UCF file? JackArticle: 8016
Ray Andraka wrote: > > Brad Ree wrote: > > > > You may find that the 12ns SRAM is somewhat harder to get. I suggest > > using a SSRAM. If you need fast larger mememory, don't use DRAM it is > > way to slow. Even the frame memory is pretty slow. You could use > > SDRAM, it is very cheap and fast. Also, the controller is as complex as > > the DRAM. The SDRAM is avaliable in speed greater than 100MHz. I've > > coded several design in a FLEX10k50 which runs at 65MHz. > > I mentioned the 12ns Static RAM for the sake of others who may be doing > things requiring more bandwidth out of the memory. For the case > discussed here, the data rate was 48KHz. Even a cheap 128K x 8 70ns > SRAM would give him over 200 memory accesses per sample, including the > delays to get on and off the FPGA. Use 2 successive accesses to get the > 16 bits. You get a depth of 64K then, using 29 pins of the FPGA. Even > with an 84 pin PLCC, you still have well over half the I/O available for > other things. the video frame buffer memories have 25 ns access times, plus fewer pins are needed, as its a large > 256KB fifo bob engle embedded solutions rengle@ix.netcom.comArticle: 8017
Hello all, I want to use the Altera EPC1213 serial configuration prom for other purposes than configuring an Altera EPLD. Unfortunately the programmer only takes a POF files for input. The data I want to put in the EPC1213 is in .HEX or BIN file format. How can I translate the .HEX (or .BIN) files into .POF files? Has anyone a translation program or does anyone know how to make one? I cannot get information about the .POF file format (Altera's secret?) The only thing I've got is a short description from the DataIO manual which describes the different packet types in the .POF file but not it's contents. Thanks. Frank Kneepkens - the Netherlands Please change 'DOT' in my E-mail address into a real dot (anti spam)Article: 8018
Jacob W Janovetz wrote: > > z80@ds.com (Peter) writes: > > >The reason for this > > >>|I like what I've heard of this technology, and it blows my mind that it > >>is not much more commonplace. > > >is mainly this: > > >>Most of the available design software will cost you between $1,000 and > >>$5,000 > > >Peter. > > >Return address is invalid to help stop junk mail. > >E-mail replies to z80@digiXYZserve.com but > >remove the XYZ. > > I agree with this... I use FPGAs and CPLD and such on a daily > basis here at school. We have several projects going on which use > Xilinx FPGAs, Altera FLEX parts, and Cypress CPLDs. Unfortunately, > once I leave school, I probably won't do much with them at all > because I can't afford the development tools. The cheap/free stuff > has such severe limitations that it isn't worth it. > > The Cypress ISP FLASH CPLDs (373i, etc.) are the only ones which > have reasonably priced tool support. Warp itself isn't even all > that good as a VHDL compiler. You can almost change the organization > of concurrent processes and it compiles differently... > > Anyhow, tool vendors: lower your prices! > > Cheers, > Jake > > -- > janovetz@uiuc.edu | Once you have flown, you will walk the earth with > University of Illinois | your eyes turned skyward, for there you have been, > | there you long to return. -- da Vinci > PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html call lattice or one of their distributers and get one of their free cdroms which has software on it (synario/abel). it only does the smaller versions but they are in-circuit programmable. bob engle embedded solutions rengle@ix.netcom.comArticle: 8019
Jack Huang wrote: > > Hello, > > I'm now using Fundation design entry and M1implementation tools on XILINX > XC4000 series. Where can I find any document talking about the keywords or > parameters > I can use in the UCF file? > > Jack You can find this information in the online M1 documentation (dynatext). The documentation is on a different CD from the M1 tools and has to be installed seperately. Look at chapter 3 of the "Development System Reference Guide". It's called "The User Constraints (UCF) File". -- Terry L. Graessle Lockheed Martin - Space Mission Systems NASA Code 521/ Microelectronics Systems Branch graessle@vlsi.gsfc.nasa.gov (301) 286-9698Article: 8020
Reetinder P. S. Sidhu wrote: > > Hi all > > Could anyone provide info on design techniques used to > implement arithmetic division on FPGAs (both LUT and sea-of-gates)? > > Thanks in advance. > > Reetinder Sidhu Division is not trivial as you've probably realized by now. If you are dealing with a limited set of divisors, the best approach is probably to multiply using canned reciprocals. If you can accept the pipeline delay, a CORDIC rotator used in linear vectoring mode will perform division with the result being an integer quotient and an integer remainder. Other iterative techniques would use a lookup to perform one of the many forms of successive approximation. Sorry I can't give you more specific info on these (I haven't had the need to find a slick solution yet). -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8021
Hi, I am using PALASM 1.5. The Fitter V1.7 delivered with the programm has a bug. It doesn't report error by equations using more than 8 PT's for one macrocell (GAL16V8, 20V8). The old one V1.67 from PALASM 1.4 does it well. Thanks in advance for any help. -------- Jaroslaw Cichorski Jr. e-mail amart@pol.JUNKMAILPROTECTION.pl E-mail address is invalid due to stop junk mail. Please r_e_m_o_v_e JUNK MAIL PROTECTION. This message was not tested on animals.Article: 8022
Anyone know of a SCSI-1 host adapter for the PC ISA buss for which a listing of the control & data ports and their functions is available? This would seem a simple quest but the opposite appears true. Adaptec & Data Technology won't disclose details. Must be others who will, though - if you know of a source for a simple 8/8 bit (polling only is fine) adapter (with a listing of the ports) in single units, do let me know. I'd sure hate to spend 3 or 4 days wrapping a few 20v8's together for this! Thanks -- Hul @@htytus@iglou.com@@Article: 8023
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 8024
Hul Tytus <htytus@iglou1.iglou.com> wrote in article <EJB0yA.CDD@iglou.com>... > > Anyone know of a SCSI-1 host adapter for the PC ISA buss for which a > listing of the control & data ports and their functions is available? This > would seem a simple quest but the opposite appears true. > Adaptec & Data Technology won't disclose details. Must be others who > will, though - if you know of a source for a simple 8/8 bit (polling only is > fine) adapter (with a listing of the ports) in single units, do let me know. > I'd sure hate to spend 3 or 4 days wrapping a few 20v8's together for > this! Go to the Adaptec web site (www.adaptec.com) and poke around a bit. The 7880 is their PCI based SCSI chip: http://www.adaptec.com/scsichip/d_sheets/980236-011.html But you have to call them to get a data sheet, I don't believe one is available on line. Austin Franklin darkroom@ix.netcom.com
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