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In article <aa5d502.0108161654.146ee3ec@posting.google.com>, Jonathan
Wilson <jonwil@tpgi.com.au> writes
>I am trying to get a datasheet on a 18P8 PAL.
A great part - but times have moved on!
>If anyone can help that would be good.
Let me have a Fax number and I'll see what I can do. I certainly have
a data sheet somewhere in the paper archive that litters my office :-)
--
Jonathan Bromley
DOULOS Ltd.
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Article: 34251Marc, But what about the IBIS simulation? What is the A/D you are trying to interface? I will run the IBIS for you if you can't just as an exercise to show everyone why this is so useful. Thanks, Austin Marc Battyani wrote: > "Rick Filipkiewicz" <rick@algor.co.uk> wrote > > > > There are a bunch of parts one can use to bridge the 5V <--> 3.3V gap. > > > Basically, they're the usual sort of buffer types: '245, '541, '573, > > > '573, '823. They're in various logic families: LPT, FCT, etc. See the > > > Pericom or IDT web sites for examples. Look for devices that have 3.3V > > > power rails and are 5V tolerant. > > > > > or, if you are not worried about wanting active drive, you could the > > QuickSwitch style devices [originally from Quality semiconductor, now > owned by > > IDT] which are basically a bunch of pass transistors. Their impedance is > near 0 > > until the driving side gets to within 0.7V of VCC and from there it rises > > rapidly. Our practice is to use '245 pin compatible nominal 5V QS3245 with > its > > VCC taken down to 3V9 via a zener (they still work with VCC = 3V3). > Pericom/TI > > do an equivalent part. > > > Be careful with the 3V ``QS'' parts though since they come in 2 flavours - > > clamping & full-swing. > > Very interesting. I will use this for fast signals. > > Thanks > > MarcArticle: 34252
Tim, It is being video'd so that it can be seen on the web. The Extreme DSP forum ran until yesterday on the web with many 'attendees.' Austin Tim wrote: > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3B7BDCF2.91B16A95@xilinx.com... > > Dave, > > > > There is a whole range of designs/cores in process. > > > > See the TNF announcement: > > > > http://www.xilinx.com/terabit/index.htm > > > > Every single interface to all of those company's logos (parts) are DDR. > > > > Austin > > Pity the TNF isn't playing in Europe/Asia/Australasia/Antarctica...Article: 34253
M Pedley wrote: > > Is it possible to convert a JEDEC file for an Atmel 15xx CPLD back to > ABEL or any other CPLD language? possible, but not really practical... If the JED has vectors appended, these provide a functional target, and can be used as a basis for coding, and for checking. However, created at the same time as the JED, is the .FIT report file, and this has all the equations, in a very portable form, and most option settings. So just grab that :-) -jgArticle: 34254
Pierre de Vos schrieb: > > Hi, > > I need to to generate a synthesised frequency of Fin * 65536 where 45Hz < > Fin < 65Hz. Does anybody know of a VHDL core that can do this. I have > FLEX6016, reference CLK=50MHz. I have a VHDL description of the more or less famous 74HC297. Its a digital PLL. It is tested and works nice. Drop me a email if you are interested in. -- MFG FalkArticle: 34255
Joey Oravec schrieb: Go for a PCI interface IC. (PLX 9030) They are very cheap and mak a clean, simple interface to the PCI. On the local bus side, you can run the bus as slow as you want. -- MFG FalkArticle: 34256
"Andrew" <adpearson@optushome.com.au.nospam> wrote in message news:pt9nntsvrs34gu8305c1nimlsp3dcft8qb@4ax.com... > I like this guys jet powered beer cooler!!! > > http://www.asciimation.co.nz/beer I like the way he has the jet exhaust aimed straight at the control panel.Article: 34257
Jamie Sanderson schrieb: > > I don't know how to "schrieb"... ;) So go for it and learn it. Yesterday I couldnt spell "educated". Now I are it. ;-) > > Makes sense to me. I was hoping the software would do better than assume > zero skew introduced by the DLL. Peter Alfke emailed me with similar advice. > I think what I'll do is use the CLK2X180 output, instead of CLK2X. I think This is possible too. You can also drive your 2x Clock with falling edges (in the HDL description) Or drive it on the same edge and just insert a synchronizer (running on the falling edge). Ok, this will increase latency but is required for highest speeds anyway. -- MFG FalkArticle: 34258
What Order wrote: > Peter and Ray, > > what order of the skew is, if it is still~200 ps i don't see where the problem > can happend sinc FlipFlop Clk-Out~1ns > > any comments I had actally posted that 200 ps should not pose a problem. But don't forget, the 1 ns delay is a worst-case number, at hot and low Vcc and slow processing. A fast chip at cold and high Vcc has less than 40% of that delay. Of course, you can be lucky even when you roll dice with the devil, but just don't count on it! Peter AlfkeArticle: 34259
I was looking at something like what they are doing at Genobyte(http://www.genobyte.com), but on a grander scale, something on the order of 144 FPGA RPU's. walder@tik.ee.ethz.ch (Herbi) wrote in message news:<3b7b86aa$1@pfaff.ethz.ch>... > In article <97fd5b24.0108150319.36203c19@posting.google.com>, jhmorris47@hotmail.com (Jason) wrote: > >I'm just a newbie here and would like to know which FPGA would be best > >suited for reconfigurable computing in terms of logic units, speed of > >reconfigurability, etc. Any help would be appreciated. > > > >Thanks > >Jason H. Morris > > Hi Jason > > Of course, it depends on what exactly you plan to do with your FPGA. > I've some experiences with XILINX FPGAs Vertex Series. As you mentioned, you > would like to do reconfiguration, these devices will be suitable for you. It's > possible to dynamically and paritaly reconfigure, readback (verify and > capture) etc. > For more information, check out www.xilinx.com > There are also some "cool" prototyping boards from XESS (www.xess.com) > available. > > Hope this helps... :-) > > cu > HerbiArticle: 34260
Jamie Sanderson wrote: > > > It doesn't help that I've also heard claims from certain Xilinx personnel > that their internal flip-flops are virtually metastable-proof... I really hope that nobody has said it that way. Metastability will be forever with us, like death and taxes. But, the recovery from a metastable situation has become much faster, now that we have a much higher gain-bandwidth product in the master latch. So we can count on metastability being resolved earlier, but the timing is still statistical, non-deterministic.... Peter Alfke > >Article: 34261
"Matthias Fuchs" <matthias.fuchs@esd-electronics.com> wrote in message news:3B7D15D8.C973E013@esd-electronics.com... > Hi, > > it seems that I have a different problem. That's my situation: > > I am using a SpartanII device "between" a PCI bridge and some ZBT RAMs. > The bridge interface uses a 33MHz > clock. The Xtal is connected directly to the bridge and FPGA. Inside the > FPGA I have two clock domains: 33MHz and 66MHz doubled by a DLL. > > Below you can see the DLL part of my design. In most cases it is > working, but some memory locations generate read/write errors when I try > to access the RAMs through the pci bridge. Since only some (without a > sheme) memory location make problems, I think that this might be a > timing problem, that could have something to do with my DLL stuff. > <cut> You should be timing your RAM I/O using the DLL with MEM_CLK5 (zbt_fb_clk) as its feedback, not the net you've called clkdouble. Then, when you cross from that domain to clklocal, you will need metastability protection. Since the doubled clock is leaving the chip, there is potentially significant skew between it and clklocal. Cheers, JamieArticle: 34262
Hi All, I'm just curious how the DLL actually works in the FPGA. I've read all the Xilinx stuff but keep thinking that if it is delay based there maybe some limitation. Can anyone enlighten me? Cheers DaveArticle: 34263
If you want to follow the PCI specification strictly, all PCI devices
have to respond to Configuration Cycle and implement Configuration
Address Space.
PCI Local Bus Specification Revision 2.2, 3.2.2.3. Configuration Space
Decoding (Page 30) states, "Every device, other than host bus bridges,
must implement Configuration Address Space. Host bus bridges may
optionally implement Configuration Address Space."
When I previously mentioned "legacy device" what I meant, and the PCI
specification meant was I/O devices which IBM already decided the I/O
and memory address back in the '80s like VGA and IDE which uses fixed
I/O and memory address.
So, if you have an ISA card (legacy or PnP), and want to convert it to
a PCI card, and assuming that the card doesn't use the I/O or memory
address IBM defined, then it seems to me that you should implement
Configuration Address Space (and implement Base Address Register
inside the Configuration Address Space), so that BIOS or Windows can
assign I/O or memory address automatically.
Since you are using interrupt, that makes it a requirement to
implement Configuration Address Space because interrupt handlers of
PCI devices use Configuration Register 3CH (Interrupt Line) and 3DH
(Interrupt Pin).
You will likely have to rewrite your device driver to accommodate the
I/O or memory address that can get assigned to any location, and also
IRQ can get assigned to any IRQ (Configuration Register 3CH will hold
the IRQ number assign by BIOS or Windows).
If your device maps to the memory space (which seems like it doesn't),
you may have to do major rewrite to the device driver because BIOS or
Windows assigns memory mapped devices starting from near the top of
the 4GB memory address, and moves downwards.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
czhou1949@home.com wrote in message news:<og6dntk8c4qkpjjmgpjaeb14dbdo4fpu7b@4ax.com>...
> Is it required to implement Configuration? I guess the only problem
> without configurarion is that the system won't be able to tell if
> there is a PCI device on the bus.
>
> Now,I am converting a lagacy ISA I/O card to PCI card (no need for
> plug-n-play). But It uses Interrupt. Do I have to implement
> Configurarion and let the system to assign a ramdon interupt or I can
> assign it myself? It would be great if I can fix #INTA to a specific
> IRQ. Because I would like to keep the exsiting software driver
> untouched and let it handle the interrupt. Is there a way of doing so.
>
>
> > Even though it might seem like implementing Configuration
> >Cycle is not needed, it is a requirement according to the PCI standard
> >to implement it.
> >However, because it is a legacy device, you don't have to implement
> >BAR (Base Address Register, Configuration Register 10H through 24H).
> >Most Configuration Registers can be hardwired to zero (except some of
> >them like Vendor ID, Device ID, Class Code, etc.).
> > Although all PCI devices are suppose to implement a parity
> >checker, I don't think it is that important to implement it, so you
> >can omit that, but you are still required to implement a parity
> >generator for read cycle.
> >
> >
> >
> >
> >Regards,
> >
> >
> >
> >Kevin Brace (don't respond to me directly, respond within the
> >newsgroup)
> >
> >
> >
> >
> >Entwicklung <entw@madex.com> wrote in message news:<3B711BD4.D0A8F7E3@madex.com>...
> >> Hi All,
> >> i'm looking for a Description how i can build a Display Card for showing
> >> the Postcode from Bios on the PCI Bus.
> >> The Card must look for an I/O Write Access on Adress 80H and then
> >> display's the data on 2 7seg Display's as HEX.
> >> Thank You for any Idea.
Article: 34264Yes, there is a min frequency limitation, about 25 MHz. That's because the DLL "eliminates" delay by actually adding delay, so that the following clock edge seems to have zero delay. And - worst case - the multi-tapped delay line ( cascaded buffers ) may have only 40 ns of total delay. Peter Alfke Speedy Zero Two wrote: > Hi All, > > I'm just curious how the DLL actually works in the FPGA. > I've read all the Xilinx stuff but keep thinking that if it is delay based > there maybe some limitation. > > Can anyone enlighten me? > > Cheers > DaveArticle: 34265
"Austin Lesea" <austin.lesea@xilinx.com> wrote > But what about the IBIS simulation? What is the A/D you are trying to > interface? I don't have an IBIS simulator. On this board, I will have fast (12 bits @ 105 MHz) and slow (14 bits @ 400KHz) A/Ds. The fast A/Ds (AD9432) are 5V devices but they have a separate digital IO supply that can be set at 3.3V so no pb. The slow A/Ds(LTC1417) are 5V device and they have only a 5V output, but as these are rather slow devices (20MHz serial data clock) and the output current seems low: Voh min=4V for Iout = 200ľA. I also have 52Mbps RS485 receivers (LTC1518) that have Voh min=4.6V for Iout = 4mA. (BTW if there is a way to use the LVDS receivers of the Virtex-II to interface with RS422/RS485 level that would be great.) These 2 parts have very different output drive so I think it could be interesting to see if the resistor to use is the same. I'm not sure Linear Technology gives IBIS model though. > I will run the IBIS for you if you can't just as an exercise to show everyone > why this is so useful. Great! That would be very interesting. MarcArticle: 34267
Phil Hays wrote: > Rick Filipkiewicz wrote: > > > > Phil Hays wrote: > > > > <snip of perfectly reasonable paranoia, possibly not enough even> > > Oh my. What did I miss? Now I'm really paranoid! ;-) > > -- > Phil Hays Hi Phil, You could always run the perl script listed in Answer Record 3813 that I wrote to detect the problem. I really don't think it would find anything after your other safeguards though. One comment on #2. If you used BLKNM to constrain the register pairs, you won't be tied down to a specific site as you are when using the LOC constraint. I've added this work around to the Answer Record. BTW, PAR does no FF replication in Virtex and Virtex-II devices. Regards, Bret Wade Xilinx Product ApplicationsArticle: 34268
Marc, Tough. No IBIS models from LTC. I have put in a request, we will see if anything happens. From the Ioh (min) it seems that the driver is pretty weak, but this may not be a measured result, but a reprint of the classic TTL output source current, and is guaranteed by design, and may be much, much higher in actual practive (no max is specified). Assuming it is >>10 mA, then the 100 ohm to 120 ohm series resistor is the only safe solution. If I get an IBIS model back, I will report it here. By the way, the Hyperlynx (Innoveda) IBIS modeling tool demo is free from the web, and may convince you to buy a copy. The cost of one copy is less than the amount you will save re-making ONE pcb from a mistake that could have been avoided. There are other SI tools available, that are more (from Mentor, Cadence, Avanti, etc.) but I find Hyperlynx to be completely adequate for a lot of designs. It has a spice extraction mode to extract spice models from the pcb layout that is particularly useful, too. Maybe I just like its user interface. Any SI tool is a worthwhile investment. Austin Marc Battyani wrote: > "Austin Lesea" <austin.lesea@xilinx.com> wrote > > > But what about the IBIS simulation? What is the A/D you are trying to > > interface? > > I don't have an IBIS simulator. > > On this board, I will have fast (12 bits @ 105 MHz) and slow (14 bits @ > 400KHz) A/Ds. > > The fast A/Ds (AD9432) are 5V devices but they have a separate digital IO > supply that can be set at 3.3V so no pb. > > The slow A/Ds(LTC1417) are 5V device and they have only a 5V output, but as > these are rather slow devices (20MHz serial data clock) and the output > current seems low: Voh min=4V for Iout = 200ľA. > > I also have 52Mbps RS485 receivers (LTC1518) that have Voh min=4.6V for Iout > = 4mA. > (BTW if there is a way to use the LVDS receivers of the Virtex-II to > interface with RS422/RS485 level that would be great.) > > These 2 parts have very different output drive so I think it could be > interesting to see if the resistor to use is the same. > > I'm not sure Linear Technology gives IBIS model though. > > > I will run the IBIS for you if you can't just as an exercise to show > everyone > > why this is so useful. > > Great! That would be very interesting. > > MarcArticle: 34269
Reinoud <dus@wanabe.nl> writes: > A circuit like you have drawn above will oscillate at a fairly high > frequency. If there are many loops, or if a lot of logic is driven > at high frequency by such loops, this may draw a lot of power. Many > boards out there with large FPGAs were not designed to handle such > power. This is not a flaw of Virtex (actually, Xilinx documents > power issues quite clearly), it's more a board/system design issue > with current generation (high power density) chips. I appreciate the insight. However, I'm still curious as to whether such things are likely to damage the chip. I suppose the answer may depend on how many such circuits one manages to configure.Article: 34271
Thats the intake !.. "Tom Del Rosso" <no.spam.please-t.delrosso@att.net> wrote in message news:4ubf7.49363$gj1.4574384@bgtnsc05-news.ops.worldnet.att.net... > "Andrew" <adpearson@optushome.com.au.nospam> wrote in message > news:pt9nntsvrs34gu8305c1nimlsp3dcft8qb@4ax.com... > > I like this guys jet powered beer cooler!!! > > > > http://www.asciimation.co.nz/beer > > I like the way he has the jet exhaust aimed straight at the control > panel. > >
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