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Dear Antonio System Generator (Xilinx's plugin to the Matlab/Simulink Software) has a demo that comes with the tools that implements a 2-D Convolution in parallel. The structure is designed for Virtex-2 and can process 494 frames/sec for a 256x256 image. It is 858 slices, 21 blockRAM, 11 dedicated Mults. This maybe a little overfill for you requirements but tailoring the design to specific needs is quite straightforward. Go to this link for more information on System Generator. http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=system_generator Thanks Niall Battson Xilinx DSP Apps Antonio Martínez Álvarez wrote: > Hello. > > I'm using Handel-C and VHDL to make a 2D filter. (DOG (Diference of > Gaussians) filter indeed). > I'm more interested in Handel-C. (DK-1.1) > > I'm doing it secuentially. For every pixel I read the pixels which are > below the mask and multiply... > > Well. I'm using a RAM that I've defined for a Virtex-E. The filter > works... but it's very slow. (12 frames per second). > > Any ideas for make more paralel the convolution? > Multiport RAMS... ?? > > Thank you. > > -- > Antonio Martínez ÁlvarezArticle: 45401
In comp.arch.embedded Everett M. Greene <mojaveg@iwvisp.com> wrote: > Amazing! An architecture that imposes both a time > /and/ space penalty for using tables! Right. I predict this so-called "TMS 1000" will be a miserable failure in the marketplace with such shoddy design. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com 9-11 United we StandArticle: 45402
mcginnis@remove_this.ieee.org (Jim McGinnis) writes: > On Mon, 22 Jul 2002 09:25:42 +1200, Jim Granville > <jim.granville@designtools.co.nz> wrote: > > Wow - and not so silly, when you think more about it : > > The 'linker' can manage code shuffles, and a LFSR is both > >silicon frugal and fast. > > Relative jumps would be out, but long jumps would load instead > >of shift, and a skip could 'double clock'. > > Look up tables would need to be in separate space. > > > > Logically, the opcode size would equal the PC, but the concept of > > scalable compilers is emerging. > > > > Could have good scope in TinyCore.fpga 'state engine' applications ? > > It was rumored that the LFSR avoided having to propagate the carry > through the 6 bits of the PC corresponding to a 64 byte page within > the 25 microsecond clock period. The assembler - there wasn't a linker > - invisibly shuffled the code for you, so mostly you weren't bothered > by the LFSR. > > The flaw with this scheme was the grief it caused with table lookups. > While it was easy to index into RAM, it was very hard to index into > ROM. IIRC TI provided a special instruction to decrement a regiater > and if the result was zero, load a 4-bit immediate value into another > register (or something like that). You'd execute a series of these > decrement-conditional-load-immediate instructions, and at the end the > proper value would have been loaded. Since instructions were 8 bits, > this method doubled the size of ROM tables. Amazing! An architecture that imposes both a time /and/ space penalty for using tables!Article: 45403
Those hardwired multipliers are about as fast as you're going to get for a single cycle multiply that wide, in that process technology. If you can stand the latency, you could probably get a faster pipelined multiplier using the logic and hand placement. What speed do you need? Are both factors really 16 bits wide and every bit can vary every clock? Regards HUA QIAN <qianhua@ece.gatech.edu> wrote in message news:<3D39828F.189F00AB@ece.gatech.edu>... > Hello, all, > > I noticed that Xilinx Vertex-II provide 18*18 multipliers, which > introduce a lot of delays. Can I generate a more efficient 16*16 > multiplier, which is my target, and give me a shorter delay? > > Another question is how to determine the clock speed for the Vertex-II > embedded multiplier? > > Any advice or help is greatly appreciated! > > HuaArticle: 45404
If you want it to work, you probably have to rewrite the source. The only time you can gate a clock in a Xilinx if if you are using the BUFGMUX in the Virtex2. "Jason Crawford" <jace@cisco.com> wrote in message news:3D3BAC69.A03017A@cisco.com... > Hi, > > Apart from using clock-enables, does anyone know of any > way to use clock-gating in Virtex-E parts? > > We have a design that is partially written for an ASIC > target and expects to see a gated clock. Rather than have > to get the designers to pour throught the code and add > clock enables to all flip flops (I can hear teeth gnashing > already) I am hoping against hope that someone has an > alternate answer to this rather difficult problem. > > yours in hope, > Jason.Article: 45405
Don't use # like that. If you want a previous value, store it in a register on the clock event. In fact, if you're just learning, pretend that there is no such thing as # (with the except of your clock generation). A lot of people get in trouble with that # sign. And you use "assign" with wires and ports, not registers. Regards "B?ge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in message news:<1027337497.858240@halvan.trd.sintef.no>... > Hi, I have a Verilog question that I hope is fairly basic. I'm running > through a tutorial and thought about testing a serial adder. The thing works > just fine, but then I try to reduce the number of registers in my code. > > What I want to do is generate a new sum and carry (temp) based on the > current inputs (a and b) and the previous carry (temp[1]). The syntax > checker parses the lines with "dummy" in them, but does not parse the one > performing the addition. Is that right? > > Best regards, > Břrge Strand > > Here's my code: > > module serialadder (clock, a, b, sum); // sum is the serial addition of a > and b > input clock, a, b; > output sum; > reg [1:0] temp; > reg dummy; > > assign sum=temp[0]; // syntax checks when sum is not a reg > > initial > begin > temp=2'b00; // start with no sum yet calculated > dummy=0; > end > > always @(negedge clock) > begin > temp = a + b + #5 temp[1]; // new sum is a + b + previous carry // parse > error in Xilinx WebPack > dummy = #5 dummy; // parses OK > end > endmoduleArticle: 45406
We've been developing with Virtex II for several months now, using ISE 4.1. We just upgrade to 4.2, and haven't been able to compile our FPGA design now for a week. We've had a host of problems, including the tools having trouble parsing the same Verilog that worked perfectly fine with 4.1, and trouble dealing with our previously working DLLs and clock trees. ISE 4.2 seems like a big step backwards. What happened? Are others having troubles with 4.2? To get around ISE bugs, we've had to move tasks from the bottom of modules to the top, and rearrange array indeces that had equations in them. This is very lame. We are now struggle with the DLLs (NuHorizons is telling us to try DCMs instead) and our clock tree. ISE 4.2 seems to be a big step backwards. All my Xilinx contacts are unavailable, and my engineers are continuing to struggle. I am very disappointed in Xilinx and in ISE 4.2. Are we doing something wrong, or is a 4.2 a step backwards??? --KenArticle: 45407
Is there any way to specify the -sd (search directory) option for NGDBuild from the Project Navigator for Xilinx 4.2i software? Or am I limited to only being able to do this at the command line? Thanks, DaveArticle: 45408
In comp.arch.fpga anon7864 <anon7864@hushmail.com> wrote: > I have a question about implementing a VHDL logic equation. I am > trying to pass signal B to A when address lines X, Y or Z are > exclusively high. > > A <= B when (X xor Y xor Z) else '0'; > > My .rpt file shows it compiles to: > > A = X & Y & Z & B > # !X & !Y & Z & B > # !X & Y & !Z & B > # X & !Y & !Z & B > > I would expect the last three lines, not the first one. I have tried > re-writing the logic, but it always seems to come out the same. > Well, here's an example: A xor B xor C, A B C = 1 (1 xor 1) xor (1) 1 xor 1 = 0 0 xor 1 = 1 So that's where the first line is coming from. Isn't there an operator for a three operator xor? xor3 or something? (Followups to comp.lang.vhdl) --buddyArticle: 45409
Hi, I was wondering if it's possible to buy licenses for Xilinx softwares? I am trying to play around with porting some of my algorithms to Virtex devices, and I need softwares like Xilix ISE 4.2, System Generator, Matlab etc.. and ofcourse since this a personal project I can't afford to pay 2K-3K $$'s for it. any idea anyone?? cheers, Auto.Article: 45410
Verification patterns (like in E) and formal verification patterns seem like
an obvious copying
of well-established and studied programming patterns. Project management and
versioning
is pretty much the same, too.
Although debugging is quite different, I believe that we will see more
shifts in digital design
towards standard programming techniques. Any comments on this ?
--
Domagoj Babic
domagoj (et) engineer.com
"Abernathey Family" <family2@aracnet.com> wrote in message
news:3D39A4B4.84124C4B@aracnet.com...
> Phil Hays wrote:
> --snip--
> > Why is there widespread hostility to learning from the
> > software design world?
> >
> --snip--
>
> Just an opinion of course. I believe the "hostility" is due to the fact
> that software methodology advances way, way, WAY too slow to keep pace
> with chip design complexity. So I believe you'll see a pick & choose
> approach in HDLs an HVLs, keeping only the stuff that actually adds
> value to the chip development process.
>
> For the longest time the most exciting thing in software development was
> a new version of Emacs :)
>
> -Don
Article: 45411
You might try student editions. The matlab needed to run with system
generator alone will set you back considerably more than that $2-3K
(matlab + simulink + dsptoolbox + dsp blockset). I'm not sure if the DSP
toolbox and block set are actually required, but without them you don't
have access to most of the DSP prowess of matlab.
Autofuzz wrote:
> Hi,
> I was wondering if it's possible to buy licenses for Xilinx softwares?
> I am trying to play around with porting some of my algorithms to
> Virtex devices, and I need softwares like Xilix ISE 4.2, System
> Generator, Matlab etc.. and ofcourse since this a personal project I
> can't afford to pay 2K-3K $$'s for it.
>
> any idea anyone??
> cheers,
> Auto.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45412The Synplify 7.1 implementation is a bit better. We detect when generics affect the port declarations and only build differently named black boxes for those cases. So it is actually quite useful for xilinx components like rams. Ray Andraka wrote: > While this mechanism is in place, it serves little use in xilinx because the xilinx tools > expect to find a netlist with the same name as the black box. The Altera LPMs use a program > inside the Altera tools to generate the macro, so putting a property on the black box is > sufficient. For xilinx, the black box 's netlist is passed in through edif. Edif does not > support a run time parameterization of the netlist, so the mechanism will not work in the > xilinx tools. > > Ken McElvain wrote: > > >>Synplify 7.1 supports generics and attributes on a black box. >>For different values of generics, Synplify will automatically >>create differently named cells to make instantiations of. >>In the case of LPM components for Altera, the cell names >>don't matter, the lpm_type attribute does, so this works >>pretty well. >> >>Johan Ditmar wrote: >> >> >>>Thanks Ray, this is helpful information. However, when you say "you >>>can't pass generics/attributes to a black box", is this true for black >>>boxes in general, or only when using Synplify? >>> >>>I know you can pass parameters to black boxes with Leonardo Spectrum, >>>see for example: >>> >>>http://www.altera.com/support/solutions/how_do_i/rd12231998_6350.html >>> >>>These parameters then appear as properties in the synthesized EDIF. >>> >>>However, I haven't been able to find such information on Synplify. >>> >>>Regards, >>> >>>Johan >>> >>>Ray Andraka <ray@andraka.com> wrote in message news:<3D383933.70DEAEAE@andraka.com>... >>> >>> >>>>In order to do that, you need a unique black box for each variation in the >>>>parameters. You can't pass generics/attributes to a black box. Think of >>>>it as a pre-compiled widget that you just plug in a socket. DIfferent >>>>flavor means different 'part number'. >>>> >>>>Johan Ditmar wrote: >>>> >>>> >>>> >>>>>Hello, >>>>> >>>>>I am trying to use black box components with parameters in Verilog >>>>>using Synplify. One way of doing this is: >>>>> >>>>>module MyModule(....) >>>>>/* synthesis syn_black_box >>>>> MyParameter = 3 >>>>>*/; >>>>> >>>>>input ... >>>>>output ... >>>>> >>>>>endmodule >>>>> >>>>>In this case however, the parameters are the same for all instances of >>>>>MyModule, which is not what I want. I was wondering if it is allowed >>>>>to do the following: >>>>> >>>>>module MyModule(....) >>>>>/* synthesis syn_black_box */; >>>>> >>>>>parameter MyParameter = 3; >>>>> >>>>>input ... >>>>>output ... >>>>> >>>>>endmodule >>>>> >>>>>such that the parameter can be defined when instantiating the >>>>>component? Does Synplify still regards the component (including the >>>>>parameter) as a black box? >>>>> >>>>>Any help appreciated, >>>>> >>>>>Regards, >>>>> >>>>>Johan >>>>> >>>>> >>>>-- >>>>--Ray Andraka, P.E. >>>>President, the Andraka Consulting Group, Inc. >>>>401/884-7930 Fax 401/884-7950 >>>>email ray@andraka.com >>>>http://www.andraka.com >>>> >>>>"They that give up essential liberty to obtain a little >>>> temporary safety deserve neither liberty nor safety." >>>> -Benjamin Franklin, 1759 >>>> >>>> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 45413
How well does it handle cases where generics affect internal construction of a xilinx black box,
for example the number of pipeline stages or perhaps a reset to value? These cases require the
black box to have a unique construction for different generics, but from a port declarations are
indistinguishable. Much of our placed library has generics to set some of the structural things,
and unconstrained vectors to set up the port widths. Anyway, that may explain some of the
problems one of my employees has been running into this week with 7.1 and black-boxed components.
I'll forward him a copy of this.
Ken McElvain wrote:
> The Synplify 7.1 implementation is a bit better. We detect
> when generics affect the port declarations and only build
> differently named black boxes for those cases. So it is
> actually quite useful for xilinx components like rams.
>
> Ray Andraka wrote:
>
> > While this mechanism is in place, it serves little use in xilinx because the xilinx tools
> > expect to find a netlist with the same name as the black box. The Altera LPMs use a program
> > inside the Altera tools to generate the macro, so putting a property on the black box is
> > sufficient. For xilinx, the black box 's netlist is passed in through edif. Edif does not
> > support a run time parameterization of the netlist, so the mechanism will not work in the
> > xilinx tools.
> >
> > Ken McElvain wrote:
> >
> >
> >>Synplify 7.1 supports generics and attributes on a black box.
> >>For different values of generics, Synplify will automatically
> >>create differently named cells to make instantiations of.
> >>In the case of LPM components for Altera, the cell names
> >>don't matter, the lpm_type attribute does, so this works
> >>pretty well.
> >>
> >>Johan Ditmar wrote:
> >>
> >>
> >>>Thanks Ray, this is helpful information. However, when you say "you
> >>>can't pass generics/attributes to a black box", is this true for black
> >>>boxes in general, or only when using Synplify?
> >>>
> >>>I know you can pass parameters to black boxes with Leonardo Spectrum,
> >>>see for example:
> >>>
> >>>http://www.altera.com/support/solutions/how_do_i/rd12231998_6350.html
> >>>
> >>>These parameters then appear as properties in the synthesized EDIF.
> >>>
> >>>However, I haven't been able to find such information on Synplify.
> >>>
> >>>Regards,
> >>>
> >>>Johan
> >>>
> >>>Ray Andraka <ray@andraka.com> wrote in message news:<3D383933.70DEAEAE@andraka.com>...
> >>>
> >>>
> >>>>In order to do that, you need a unique black box for each variation in the
> >>>>parameters. You can't pass generics/attributes to a black box. Think of
> >>>>it as a pre-compiled widget that you just plug in a socket. DIfferent
> >>>>flavor means different 'part number'.
> >>>>
> >>>>Johan Ditmar wrote:
> >>>>
> >>>>
> >>>>
> >>>>>Hello,
> >>>>>
> >>>>>I am trying to use black box components with parameters in Verilog
> >>>>>using Synplify. One way of doing this is:
> >>>>>
> >>>>>module MyModule(....)
> >>>>>/* synthesis syn_black_box
> >>>>> MyParameter = 3
> >>>>>*/;
> >>>>>
> >>>>>input ...
> >>>>>output ...
> >>>>>
> >>>>>endmodule
> >>>>>
> >>>>>In this case however, the parameters are the same for all instances of
> >>>>>MyModule, which is not what I want. I was wondering if it is allowed
> >>>>>to do the following:
> >>>>>
> >>>>>module MyModule(....)
> >>>>>/* synthesis syn_black_box */;
> >>>>>
> >>>>>parameter MyParameter = 3;
> >>>>>
> >>>>>input ...
> >>>>>output ...
> >>>>>
> >>>>>endmodule
> >>>>>
> >>>>>such that the parameter can be defined when instantiating the
> >>>>>component? Does Synplify still regards the component (including the
> >>>>>parameter) as a black box?
> >>>>>
> >>>>>Any help appreciated,
> >>>>>
> >>>>>Regards,
> >>>>>
> >>>>>Johan
> >>>>>
> >>>>>
> >>>>--
> >>>>--Ray Andraka, P.E.
> >>>>President, the Andraka Consulting Group, Inc.
> >>>>401/884-7930 Fax 401/884-7950
> >>>>email ray@andraka.com
> >>>>http://www.andraka.com
> >>>>
> >>>>"They that give up essential liberty to obtain a little
> >>>> temporary safety deserve neither liberty nor safety."
> >>>> -Benjamin Franklin, 1759
> >>>>
> >>>>
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45414Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:<agj71n$6mp$1@newsreader.mailgate.org>... > Guy Schlacter wrote: > > > > I am looking for employment (permanent or otherwise) and really wanted to > > bounce it off the group on this forum. > > > > -guy > > > > > I thought you had your own consulting business? > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) Kevin- To clarify, though I do have a consulting business, I am in the market for time employment. -GuyArticle: 45415
The generics (like reset values) are passed as properties on the instance. We obviously don't know what is going on inside of the black box itself. It is possible that you were relying on the pre 7.1 generated cell names that would have had generic values as part of the cell name. Ray Andraka wrote: > How well does it handle cases where generics affect internal construction of a xilinx black box, > for example the number of pipeline stages or perhaps a reset to value? These cases require the > black box to have a unique construction for different generics, but from a port declarations are > indistinguishable. Much of our placed library has generics to set some of the structural things, > and unconstrained vectors to set up the port widths. Anyway, that may explain some of the > problems one of my employees has been running into this week with 7.1 and black-boxed components. > I'll forward him a copy of this. > > Ken McElvain wrote: > > >>The Synplify 7.1 implementation is a bit better. We detect >>when generics affect the port declarations and only build >>differently named black boxes for those cases. So it is >>actually quite useful for xilinx components like rams. >> >>Ray Andraka wrote: >> >> >>>While this mechanism is in place, it serves little use in xilinx because the xilinx tools >>>expect to find a netlist with the same name as the black box. The Altera LPMs use a program >>>inside the Altera tools to generate the macro, so putting a property on the black box is >>>sufficient. For xilinx, the black box 's netlist is passed in through edif. Edif does not >>>support a run time parameterization of the netlist, so the mechanism will not work in the >>>xilinx tools. >>> >>>Ken McElvain wrote: >>> >>> >>> >>>>Synplify 7.1 supports generics and attributes on a black box. >>>>For different values of generics, Synplify will automatically >>>>create differently named cells to make instantiations of. >>>>In the case of LPM components for Altera, the cell names >>>>don't matter, the lpm_type attribute does, so this works >>>>pretty well. >>>> >>>>Johan Ditmar wrote: >>>> >>>> >>>> >>>>>Thanks Ray, this is helpful information. However, when you say "you >>>>>can't pass generics/attributes to a black box", is this true for black >>>>>boxes in general, or only when using Synplify? >>>>> >>>>>I know you can pass parameters to black boxes with Leonardo Spectrum, >>>>>see for example: >>>>> >>>>>http://www.altera.com/support/solutions/how_do_i/rd12231998_6350.html >>>>> >>>>>These parameters then appear as properties in the synthesized EDIF. >>>>> >>>>>However, I haven't been able to find such information on Synplify. >>>>> >>>>>Regards, >>>>> >>>>>Johan >>>>> >>>>>Ray Andraka <ray@andraka.com> wrote in message news:<3D383933.70DEAEAE@andraka.com>... >>>>> >>>>> >>>>> >>>>>>In order to do that, you need a unique black box for each variation in the >>>>>>parameters. You can't pass generics/attributes to a black box. Think of >>>>>>it as a pre-compiled widget that you just plug in a socket. DIfferent >>>>>>flavor means different 'part number'. >>>>>> >>>>>>Johan Ditmar wrote: >>>>>> >>>>>> >>>>>> >>>>>> >>>>>>>Hello, >>>>>>> >>>>>>>I am trying to use black box components with parameters in Verilog >>>>>>>using Synplify. One way of doing this is: >>>>>>> >>>>>>>module MyModule(....) >>>>>>>/* synthesis syn_black_box >>>>>>> MyParameter = 3 >>>>>>>*/; >>>>>>> >>>>>>>input ... >>>>>>>output ... >>>>>>> >>>>>>>endmodule >>>>>>> >>>>>>>In this case however, the parameters are the same for all instances of >>>>>>>MyModule, which is not what I want. I was wondering if it is allowed >>>>>>>to do the following: >>>>>>> >>>>>>>module MyModule(....) >>>>>>>/* synthesis syn_black_box */; >>>>>>> >>>>>>>parameter MyParameter = 3; >>>>>>> >>>>>>>input ... >>>>>>>output ... >>>>>>> >>>>>>>endmodule >>>>>>> >>>>>>>such that the parameter can be defined when instantiating the >>>>>>>component? Does Synplify still regards the component (including the >>>>>>>parameter) as a black box? >>>>>>> >>>>>>>Any help appreciated, >>>>>>> >>>>>>>Regards, >>>>>>> >>>>>>>Johan >>>>>>> >>>>>>> >>>>>>> >>>>>>-- >>>>>>--Ray Andraka, P.E. >>>>>>President, the Andraka Consulting Group, Inc. >>>>>>401/884-7930 Fax 401/884-7950 >>>>>>email ray@andraka.com >>>>>>http://www.andraka.com >>>>>> >>>>>>"They that give up essential liberty to obtain a little >>>>>>temporary safety deserve neither liberty nor safety." >>>>>> -Benjamin Franklin, 1759 >>>>>> >>>>>> >>>>>> >>>-- >>>--Ray Andraka, P.E. >>>President, the Andraka Consulting Group, Inc. >>>401/884-7930 Fax 401/884-7950 >>>email ray@andraka.com >>>http://www.andraka.com >>> >>> "They that give up essential liberty to obtain a little >>> temporary safety deserve neither liberty nor safety." >>> -Benjamin Franklin, 1759 >>> >>> >>> >>> > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 45416
Hi, I have a question is that : if I design a circuit by verilog. Then, I synthesis this and implement by FPGA. Assuming the design is work in FPGA, then, I want to make it a custom IC. Can I know the netlist in gate level of the design after synthesis? Otherwise, how can i translate the design from FPGA to IC? Thanks a lot. ^_^ RealaArticle: 45417
Synthesize it for an ASIC. Mostly the libraries are different. You will have some "problems", yes, but it is a well traveled path. On Tue, 23 Jul 2002 10:40:18 +0800, "Reala" <manfield.chow@scoreconcept.com> wrote: >Hi, > >I have a question is that : if I design a circuit by verilog. Then, I >synthesis this and implement by FPGA. >Assuming the design is work in FPGA, then, I want to make it a custom IC. >Can I know the netlist in gate level of the design after synthesis? >Otherwise, how can i translate the design from FPGA to IC? > >Thanks a lot. ^_^ >Reala > >Article: 45418
Ray, Thanks for that observation about the carry chains. I thought I might be crazy because I was getting worse response from the adders on the V2 than I was on the Virtex Es. I posted a question about this but never got a response. I think there is a value called Tciny(?) that deals with getting data on the carry chain that's a lot bigger for V2 than it was for VE. It's depressing looking at the paths, because the carry chains are so fast, but getting data to the chain and on it is so slow. How much faster are the enhanced multipliers going to be? I've been disappointed with the fact that with each service pack the multipliers get slower and that the pipelined multiplier doesn't yield very much benefit, but I have to say that I'm still very glad Xilinx put these in. In the design I'm doing right now I'm using about 25 for halfband interpolators, mixers, linear interpolators, gain stages, etc. I would never have the gates to do this with fabric-based multipliers. In many cases the multipliers weren't fast enough for my needs and I had to double up and operate in parallel, but since I have 40 multipliers in the part this isn't a problem. Hua: I'd recommed this technique over using pipelined fabric multipliers. A fabric multiplier can get you over 200MHz if you pipeline every stage, but this will eat up a lot of gates. Using two embedded multipliers will also get you over 200MHz in fewer cycles if you demux the data stream into two multicycle paths and use two multipliers and then remux. (You have to set the constraints and clock enables properly.) Then you haven't burned up nearly as many of the valuable fabric gates. This might not work in every application, but works in most DSP applications. -Kevin "Ray Andraka" <ray@andraka.com> wrote in message news:3D3CAE7C.9325F62F@andraka.com... > This depends on which silicon. Silicon produced before this spring has slow multipliers that are > pretty easy to beat with a pipelined multiplier in the fabric. The silicon with the fixed > multipliers is difficult to match the speeds of the multipliers with a pipelined multiplier in > the fabric because it takes a pretty long time getting on and off the carry chains, in fact from > what I've seen so far the carry chains are no faster than, and perhaps a little slower than the > virtexE carry chains :-(. > > Jay wrote: > > > Those hardwired multipliers are about as fast as you're going to get > > for a single cycle multiply that wide, in that process technology. If > > you can stand the latency, you could probably get a faster pipelined > > multiplier using the logic and hand placement. What speed do you > > need? Are both factors really 16 bits wide and every bit can vary > > every clock? > > > > Regards > > > > HUA QIAN <qianhua@ece.gatech.edu> wrote in message news:<3D39828F.189F00AB@ece.gatech.edu>... > > > Hello, all, > > > > > > I noticed that Xilinx Vertex-II provide 18*18 multipliers, which > > > introduce a lot of delays. Can I generate a more efficient 16*16 > > > multiplier, which is my target, and give me a shorter delay? > > > > > > Another question is how to determine the clock speed for the Vertex-II > > > embedded multiplier? > > > > > > Any advice or help is greatly appreciated! > > > > > > Hua > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 45419
Dear all, I would like to design of 16 X 16 multiplier with single clock cycle. I try to search internet but fail. Any free design and hint to design this kind of multiplier? Size reduction is need for the design. Thank a lot. RealaArticle: 45420
hello friends i am programming cpld's for the first time. i have a jtag cable from insight. i have prepared a simple regulated power supply using 12v 500mA transformer bridge rectifier of 4007 and two lm 317 to extract two supplies of 3.3v and 5 v needed for cpld and jtag cable respectively. but when ever i connect the jtag supply my supply voltage drops..... i have checked all the connection but didnot find any short circuit or wrong connection ..... can any one tell me where might be the problem and how to check if the jtag cable is intact i have webpack and am suing the impact software for programming.Article: 45421
Kevin Neilson wrote: > > If you want it to work, you probably have to rewrite the source. The only > time you can gate a clock in a Xilinx if if you are using the BUFGMUX in the > Virtex2. > > "Jason Crawford" <jace@cisco.com> wrote in message > news:3D3BAC69.A03017A@cisco.com... > > Hi, > > > > Apart from using clock-enables, does anyone know of any > > way to use clock-gating in Virtex-E parts? > > > > We have a design that is partially written for an ASIC > > target and expects to see a gated clock. Rather than have > > to get the designers to pour throught the code and add > > clock enables to all flip flops (I can hear teeth gnashing > > already) I am hoping against hope that someone has an > > alternate answer to this rather difficult problem. > > > > yours in hope, > > Jason. Why shouldn't you be able to do clock gating in virtexE, just use standard logic to do the gating and then buffer the resulting clock, just as you would in the asic. The problems start when you want to get gated clocks that are balanced -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 45422
Dear Kevin, Thank you for your detailed reply. Actually, I work in a IC design company. My boss want to develop a low-end DSP chip. However, we are less experience in this. We think that one of the important building block is 16X16 small size, single cycle multiplier. I write simple verilog and synthesis by Xilinx Web pack tools. It seems that work. Assuming it is work, I want to open some output files to see what "circuit" is synthesised, because I will design a DSP chip. But i do not know which output files mention the netlist of the "systhesised design" in gate level. I guess that the verilog code will be synthesised by synthesis according to synthesis tool's library. Am I correct? Can i force the synthesis tool to synthesis the verilog code without using library? (I means the design is systhesis in gate level ...AND OR XOR.....) Then, can i see the netlist in gate level such that I can study the design synthesised by the synsthesis tool? You say that: >To make sure the synthesized design was synthesized correctly, >do a gate-level simulation of the synthesized design. >You should be able to run the same testbench code you used for an RTL simulation. I am not really understand because I am a beginner of IC design. what is the meaning of gate-level simulation? by what kind of tools? Modelsim? Xilinx? or other? What is RTL (Register Tran...Logic) I know the name but not really know the meaning? What tools for RTL synthesis? Thank again ^_^ Reala "Kevin Brace" <killspam4kevinbraceusenet@killspam4hotmail.com> wrote in message news:ahip0o$rea$1@newsreader.mailgate.org... > You will want to avoid using vendor specific features (vendor > specific primitives) as much as possible if your goal is to do an FPGA > to ASIC conversion. > Also, you will need to have sufficient volume to justify the NRE (Non > Recurring Engineering) fee you will have to pay upfront. > There are firms like AMI Semiconductor, Chip Express, Lightspeed > Semiconductor, and NEC (And a few more I cannot think of right now.) > that do an FPGA to ASIC conversion if you submit them the EDIF netlists > generated from your FPGA synthesis tool. > To make sure the synthesized design was synthesized correctly, > do a gate-level simulation of the synthesized design. > You should be able to run the same testbench code you used for an RTL > simulation. > Also, before firing up your FPGA, it is probably a good idea to do a > post P&R simulation of your P&Red design. > I always do a post P&R simulation before firing up an FPGA board I got. > When I made sure the design worked fine in a post P&R simulation, my > design always worked fine in a real system. > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > > > > Reala wrote: > > > > Hi, > > > > I have a question is that : if I design a circuit by verilog. Then, I > > synthesis this and implement by FPGA. > > Assuming the design is work in FPGA, then, I want to make it a custom IC. > > Can I know the netlist in gate level of the design after synthesis? > > Otherwise, how can i translate the design from FPGA to IC? > > > > Thanks a lot. ^_^ > > RealaArticle: 45424
thanks to all. I've just forgoten to set GUEST directive in pci_user_constants. Now, it work fine. Best regards, BROTO Laurent
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