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Bob Perlman wrote: > Hi - > > I just have to know--what is Long Island Verilog? Is it to Verilog > what Long Island iced tea is to iced tea, i.e., vaguely similar in > appearance but more intoxicating? Is there a reference manual ? Reference manual becomes progressively more blurred as the code is written.Article: 26201
> In fact it would be easy enough to get the programmer to check the .bit > file to see if the JTAG clock had been selected for start-up. If you are programming the SPROM (via JTAG), you need to set the startup to CCLK, since the FPGA will be loading from the SPROM via the DIN/CCLK etc. pins... So, the JTAG programmer would have to check if you are sending it to the SPROM or the FPGA...Article: 26202
> Ok, I've tried to get this discussion going a time or two... > What about HDL generated floor-planning? I'm specificly looking > for *real* information about Synplicity's Amplify. I can read > their Power-Point-Ware and I'm impressed. Anyone that has > actually used it would be very helpful. Before I write the check > for this widget ($30K + 20% forever) I'd like to be sure it does > what I need. For $30k, call me and I'll do your floorplanning by hand ;-)Article: 26203
> I agree, but there must be a lot of people (myself included) who havn't > got the time for relative placement It doesn't take THAT much time, if you do your designs with this in mind from the start. Not doing it, you will spend more time fussing with the design, and re-running the tools.Article: 26204
Hello, Perhaps someone can help clear up my confusion. I have installed Foundation iSE 3.2.03i along with Coregen 3.2.03i. I want to target a device big enough and fast enough to prototype our next ASIC, thinking XCV2600E. It will contain memory in fifo and single port forms. The Coregen provides a family selection of are XC4000, Spartan, Virtex, Spartan 2 and Virtex 2. The foundation tool provides a selection of Spartan 2, Spartan XL, Virtex, Virtex E and 3 different CPLDs. The overlap is Spartan 2 and Virtex of which neither one will be able to perform as required to prototype our ASIC. Does somebody know how to work around this limitation in the Xilinx tools and is willing to share the knowledge? The idea of hand rolling the memory is not all that appealing, since I have other fish to fry. regards Jerry EnglishArticle: 26205
Hi I was wondering : what is the point of the analogue FPGAs available from Lattice and others, in the case where the signal processing finally involves an ADC ? Bearing in mind the narrow frequency range (Filter corner frequency from 50 kHz to 500 kHz for Lattice) is it not as easy to have a 1 to 10 MHz ADC and do all your processing inside a general digital FPGA that can be clocked at 100 MHz ? I know that there may be niche applications for these devices, but does anyone out there see them ever making a big impact on the market ? Of course, the analogue die-hards will say that an analogue FPGA has existed for over 25 years. It's called a quad op-amp and it's programmed with those funny things called resistors and capacitors ;-) Cheers -- Steve Dewey steve at s-dewey dot demon dot co dot ukArticle: 26206
For the XC2000 devices, you need the old Viewlogic 4 software, plus XACT6 place & route tools. I vaguely recall there was a bootleg CD from Russia containing all this stuff, with a dongle crack included. However you are wasting your time doing any new development with 2k devices, they are long obsolete. >I'm a rather "advanced" hobbyist, looking to get into some FPGA design (for >starters, as some glue logic for an ISA PC Card). I recently stripped an >old videoconferencing system and it had about 50 XC2018-P84C chips on it >(also some XC3042's and a pair of XC3090's). It also has a lot of GALs, >57C291's, 57C45's, and some various Altera stuff. In short, it is a >reprogrammable logic goldmine. > >But, many of the parts are out of production and finding development support >for them is difficult. I have Protel 99 SE and have a simple design input >into it (schematic). But, when I compile it, I get a message about missing >PLA2XNF.EXE. I'm assuming this is part of the Xilinx XACT tools? > >The problem I have is that nothing currently available from Xilinx seems to >support my XC2018 chips. I prefer to use the Xilinx stuff at this point, >because I can store the programming in an EPROM (I have a burner) rather >than having to program the actual chip (I don't have a burner capable of >doing any programmable logic burning). > >Does anyone have some pointers as to where I can find support for these >devices? (It appears that the student [and even professional] editions of >Xilinx' stuff are geared toward their newer parts). Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26207
rickman <spamgoeshere4@yahoo.com> writes: > Don't tell me! Tell Xilinx! Well, I was actually telling the news group, which includes two Xilinx employees amoung the regulars and a few lurkers from other vendors. > policies. Try contacting them. Any email address which will read such mails? > But we are all just shouting into the wind > until Xilinx allows the bitstream info out. Sure. > This is not without precedent. A startup company called NeoCad > originially started by reverse engineering the bitstream. After some > sucess at selling third party tools, Xilinx cooperated and gave them the > bitstream and support. A couple years later Xilinx bought Neocad. Interesting. > Who knows what Xilinx will do if they are asked nicely enough? What did they say to the umpteen people who have already asked? > Or you > could reverse engineer the bitstream yourself and be the pioneer of > GVHDL! Now how does one do that? > Oh, by the way, Xilinx has announced that they are releasing a set of > free tools later this month... Free as in free beer [1] or as on free talk [2]? [1] no financial cost to get it [2] sorce available to dissect and compile -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26208
rickman <spamgoeshere4@yahoo.com> writes: > The bitstream can be reverse engineered, or actually there is no need > for a bitstream format just to translate VHDL to a FPGA. The > intermediate format is EDIF What is that? I have not seen that mentioned yet. FPGA newbie, as I said :-). Is there a good web page that details the various tools, steps, intermediate files used in FPGA development? > and the back end tools are supplied by the > chip vendor. But most likely not as source that I can compile on this box :-(. > So where are all the open source VHDL compilers? Lack of people who know they can be made? Need to have the vendors back end, so why not just use their VHDL compiler? > If GPL'd tools are so good, why aren't there more of them in the FPGA > world? Lack of the info needed to make the stuff? -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26209
Neil Franklin wrote: > > Oh, by the way, Xilinx has announced that they are releasing a set of > > free tools later this month... > > Free as in free beer [1] or as on free talk [2]? > > [1] no financial cost to get it > [2] sorce available to dissect and compile What exactly do you do with FPGAs? Are you currently using any of the low cost tools available? What background do you have with digital hardware? I am asking because you don't seem to be very familiar with what is available. The currently available tools consist of a few open source VHDL (and maybe Verilog) compilers and multiple free (beer) toolsets from different chip vendors. My comment above was about the free (beer) tools that Xilinx has announced. Xilinx is what many people think of when the talk about FPGAs. If you want to see open source tools, then the only way that will happen is if you write them directly! It should be plain to anyone that unless something major happens at Xilinx, you will not see them supporting open source tools. There is no point in posting here or anywhere else. Xilinx may read this newsgroup, but I don't think these types of posts make much of a dent. There has been much more call here for a supported toolset under Linux and we still don't have that yet. People even run the tools using WINE, but still no formal support from Xilinx. I don't agree that the bitstream is required to have opensource tools for the front end. Before anyone starts duplicating the many, many man years (decades) that Xilinx has invested in backend tools, shouldn't there be good, open source front end tools? If you want to reverse engineer the bitstream, it will be somewhat tedious, but certainly doable. You first have to get one of the low cost or the soon to be free (beer) toolsets. Then use the chip editor to select a specific feature. Select the same feature in multiple cooresponding locations. Generate a bit file. See which bits are set. Generate a bit file with no features. Compare. You should see a pattern in the bits. If you repeat this for a few different locations, you should be able to figure out the repeat unit for the physical structure within the bitstream. Then select a different feature and repeat. You will have to do this many times, but depending on your luck, the regular structure of the chip will allow a lot of information to fall in place once you crack the basic pattern. This won't be easy, or a lot of fun. But if the open source tool community is half as supportive as you say, they should be able to do this in short order by a SETI type approach. Hey, the same approach was used to crack "unbreakable" crypto codes. A simple Xilinx bitstream should not be hard at all. BTW, does anyone know if there is a specific prohibition in the tool license to reverse engineering the bitstream? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26210
Neil Franklin wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > > The bitstream can be reverse engineered, or actually there is no need > > for a bitstream format just to translate VHDL to a FPGA. The > > intermediate format is EDIF > > What is that? I have not seen that mentioned yet. FPGA newbie, as I said :-). I understand now. Every month or two or three, there is a post about open source tools. I would suggest that you search the archives, but I think the signal to noise ratio is rather high in those threads. EDIF is a standard file format for describing chip/board designs. The format is limited to components and interconnects, to the best of my knowledge. I believe some vendors add certain property information, but I don't know how much of that is per the standard and how much is vendor specific. It may be both, with a slot allowed by the standard, but with vendor specific information, don't know for sure. You can try searching the web for information. I have no URLs on this. I can read it without having a spec. I don't need to write it on my own. The tools do that. > Is there a good web page that details the various tools, steps, > intermediate files used in FPGA development? Unfortuately, this information is hard to get even from the tool vendors. In a nutshell, you have two main parts, the front end and the back end. The front end is used to capture a design either in schematic form or in an HDL. A tool is used to generate FFs and gates in the intermediate format, either a vendor specific format such as XNF (Xilinx) or EDIF. The back end tools accept the gate level design and figure out how to put that into the vendor's FPGA. This is by definition, vendor specific. But you may be able to develop a vendor independant tool that can be configured for the chip. Then the programming file or bitstream has to be generated from the device specific routed design. This is the only step that you don't have info on. BTW, a tool like this will probably be used for many different chips including CPLDs. I beleive many of those have published formats for the programming data. A tool might want to start with that rather than the largest FPGAs. > > and the back end tools are supplied by the > > chip vendor. > > But most likely not as source that I can compile on this box :-(. > > So where are all the open source VHDL compilers? > > Lack of people who know they can be made? Need to have the vendors > back end, so why not just use their VHDL compiler? You tell me. Why do you want open source tools? Are you saying that an open source compiler is no good without an open souce back end? > > If GPL'd tools are so good, why aren't there more of them in the FPGA > > world? > > Lack of the info needed to make the stuff? We are going in circles now. All the info you need to make an open source compiler is in the VHDL LRM. That is the place to start regardless of the status of the back end tools. An open source back end is of no value with out the front end. The vendor's back end tools are free (beer) or nearly so. The front end tools can be very expensive at $5,000 and up! That's a lot of beer!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26211
rickman wrote: > > This issue was covered a month or two ago and Peter Alfke indicated that > pinout text files would be provided. I think he even made these files > available for the Spartan II series. > > Now if he could do something about the high startup current of the > parts. I've noted the high startup current in the Virtex parts. What is the mechanism for the high current? rkArticle: 26212
On Wed, 4 Oct 2000 04:33:21, Phil Hays <spampostmaster@sprynet.com> wrote: > "Keith R. Williams" wrote: > > > I've gone through the Amplify PowerPoint-Ware. ...well, mostly. > > I have many questions, which I really should talk to their FAEs > > about. ...though since you've volunteered! ;-) > > > - I've looked through the flow and it seems that my Synplify > > license is useless, given that I wanted to stay with Virtex (I'm > > still fighting with a SpartanXL, so this isn't a biggie). > > Yes, but you can't lose by asking "If I buy Amplify and turn in my Synplify > license will you give me a credit for it?" Good point. However, I still have a SpartanXL widget. Yes, they told me to go to Spartan-II. Damned good thing I didn't, given the angst in this group. > > - Given the above, and Synplicities wish to move me to -Pro, why? > > Sure, I see some use for -Pro for higher speed designs, but > > doesn't Amplify trump -Pro here. I don't see the cross. > > Amplify is "Synplicity Pro with Amplify". I've heard several people express the > opinion that -Pro isn't a good choice: if you want a good push-button flow, > non-Pro is good enough. If you need more go all the way to Amplify. That is *exactly* what I wanted to know. The tool-flow indicated this, but I'm always uncertain with PowerPointWare. > > - How hard is Amplify to learn. Can I pick it up (they did send > > me the manual) or should I take a *valuable* week off to go to > > their new training? > > I think Amplify is fairly easy to pick up. I've used it since the first Beta > release, so I would hope your learning would be quicker than mine (little > documentation and I sent the first bug report after trying the tool for a less > than a hour) On the other hand, I've been building Xilinx parts for a decade, > using schematics and hand written placements at first, so it's not like I'm a > newbie. As you are still thinking about buying it, you sure could ask for some > FAE time to help you get started as part of the deal. A few hours with a good > FAE should take days off your learning time. Excellent point! I'll do exactly that. I still consider myself a newbie, but will climb over the hump. ...it is a biggie! Phil, thanks a lot! ---- KeithArticle: 26213
On Sun, 8 Oct 2000 15:36:13, "Austin Franklin" <austin@darkroo99.com> wrote: > > Ok, I've tried to get this discussion going a time or two... > > What about HDL generated floor-planning? I'm specificly looking > > for *real* information about Synplicity's Amplify. I can read > > their Power-Point-Ware and I'm impressed. Anyone that has > > actually used it would be very helpful. Before I write the check > > for this widget ($30K + 20% forever) I'd like to be sure it does > > what I need. > > For $30k, call me and I'll do your floorplanning by hand ;-) Well, there are bucket$ for this, and bucket$ for that. I'm trying to get a high-powered Laptop to do my work in the lab or office. The $4K laptop is a problem, but $60K worth of node-locked software doen't seem to phase bean-counters. I always ask, wanna buy another copy of the tools for the lab? For $30K are you willing to support the tool for the next five years? Ok, I'm not either, but I get slipped some bananas under the door too. ;-) ---- KeithArticle: 26214
rk wrote: > > rickman wrote: > > > > This issue was covered a month or two ago and Peter Alfke indicated that > > pinout text files would be provided. I think he even made these files > > available for the Spartan II series. > > > > Now if he could do something about the high startup current of the > > parts. > > I've noted the high startup current in the Virtex parts. What is the > mechanism for the high current? > > rk This is still a mystery to me. I have asked, here is the answer I got... *************************************** The current is a consequence of the race to power the memory cells that are used for the pass gate muxes vs. the memory cells used for everything else, so there is no way to affect it. It all happens internally. A slower ramp (e.g. 10 ms vs 1 ms) has lower startup I. Smaller parts can actually have worse turn on current that the largest parts (by 3:1, i.e. 500 mA worst case was for the smallest Virtex, not the largest). *************************************** I guess the pass gates are turned on until the memory is reset. Don't know... The part that bothers me is the higher current for the smaller parts! This is very counter intuitive. But since I don't understand the mechanism, I can't say anything about the effects. It just makes the parts very hard to use in small, power limted designs. I have to design my power supply for 500 mA per chip when I only expect to use half that power (or less) in normal operation. I wonder why Xilinx thinks this is not a problem? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26215
rickman <spamgoeshere4@yahoo.com> writes: > Oh, by the way, Xilinx has announced that they are releasing a set of > free tools later this month... On Linux too ? Open source would solve that issue, wouldn't it. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 26216
How many signals can one signal drives at most? In common sense, there must be an upper limit of the signal's drive capacity, (right?), but why the Foundation don't give any warnning information about it? ( I had tried to drive 40 signals with one signal, and still get passed), If I generate a 32 bit mux, the 's' input should drive at least 32 signals, whether is there an error for the lack of drive capacity?( though it can be passed by the timing simulator) Should I divide the mux into some smaller ones? Anybody can help me? many thanks!Article: 26217
"Keith R. Williams" wrote: >"Phil Hays" wrote: PH> Amplify is "Synplicity Pro with Amplify". I've heard several people express the PH> opinion that -Pro isn't a good choice: if you want a good push-button flow, PH> non-Pro is good enough. If you need more go all the way to Amplify. I'm not happy leaving the above as a blanket statement. There are good reasons to go with just -PRO: 1) The next release (6.1) is supposed to support mixed design inputs (both Verilog and VHDL in the same design). This is a yawner for everyone that doesn't need it, but is a key issue for those that do. 2) -Pro produces better results than the regular Synplify. If that's enough good enough, it's good enough. 3) Amplify only supports (at least currently) the big devices from Altera and Xilinx. If you use a device not on the list, there is no point buying more than -Pro. > I still consider myself a > newbie, but will climb over the hump. ...it is a biggie! Best of luck, Keith, and keep in touch. -- Phil HaysArticle: 26218
"yihua xu" <xuyihua@263.net> wrote in message news:ee6e3c2.-1@WebX.sUN8CHnE... > How many signals can one signal drives at most? Lots. Hundreds, certainly, maybe even thousands, under the right conditions (keep reading). > In common sense, there must be an upper limit of the signal's drive capacity, (right?), but why the Foundation don't give any warnning information about it? ( I had tried to drive 40 signals with one signal, and still get passed), It'll just degrade timing. If you have your design constrained, the tool will most definitely tell you when you get to the point that the drive capacity slows down the signals' propagation so much that it can no longer meet timing. A fanout of 40 is not necessarily unreasonable, depending on how fast and how far you're trying to push your signals. > If I generate a 32 bit mux, the 's' input should drive at least 32 signals, whether is there an error for the lack of drive capacity?( though it can be passed by the timing simulator) Should I divide the mux into some smaller ones? If it's meeting timing, don't bother, unless you're just looking for some good experience. Note that synthesis tools generally have a "maximum fanout" setting where, if the fanout on the signal is exceeded, and the source is something like a register (e.g., you have a registered select signal 's' to your mux) it'll go back and replicate that register to reduce the fanout. We have a design with a bunch of 128 bit wide FIFOs implemented using select RAM, and the counters that drive the address lines of the RAMs get replicated something like 4 or 5 times in order to meet performance requirements. ---Joel KolstadArticle: 26219
Hi, Thanks for all the input on this thread. Once it had been established that the DLL was unlocking (even though the "locked" output was high), the rest was easy. In this case it was due to crosstalk on the pcb between data lines and the hstl_i vref line. Yes, there was a cap on the vref line, but it was a few too many mm away from where it should have been. And yes, I know I said that line was clean. I hadn't looked at it for long enough to see the glitch that stopped the DLL. Another small cap soldered as close as possible to the balls fixed it. (Sounds painful, but you know what I mean.) Regards, Allan.Article: 26220
Can anybody tell me, what I have to do to activate the JTAG startup-clock? I'm using the Foundation Express 3.1 GUI. Sorry, but I didn't find this option anywhere. I've tried to change the bitgen.ut file - but after rerunning the last step of the flow engine it was set back to "startupclock:cclk" // seems to be just a report. So I know what to do now but I didn't catch the point how to do this. (Sorry) Marc ReinertArticle: 26221
In article <39E18046.B544E977@tu-harburg.de>, Marc Reinert <reinert@tu-harburg.de> wrote: > Can anybody tell me, what I have to do to activate the JTAG startup- clock? > > I'm using the Foundation Express 3.1 GUI. Sorry, but I didn't find this > option anywhere. > > I've tried to change the bitgen.ut file - but after rerunning the last step > of the flow engine it was set back to "startupclock:cclk" // seems to be > just a report. > > So I know what to do now but I didn't catch the point how to do this. > (Sorry) > > Marc Reinert > > After changing the line in the UT file to: "-g StartUpClk:JTAGCLK" You should run bitgen again. for example: "bitgen design_name.ncd -l -f ut_file_name.ut design_name_jtag.bit" Good luck !, Rotem Gazit. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26222
rotemg@mysticom.com schrieb: > After changing the line in the UT file to: > > "-g StartUpClk:JTAGCLK" > > You should run bitgen again. > for example: > "bitgen design_name.ncd -l -f ut_file_name.ut design_name_jtag.bit" > I get the following errormessage: "ERROR:Bitgen:42 - Unknown setting "JTAGCLOCK" for option "StartupClk". Please consult the "BitGen" Section in Chapter Twelve of the Development System Reference Guide for the appropriate command-line options to create a bitstream file or consult the "Implementation Options" Section of the Design Manager/Flow Engine Reference/User Guide for Configuration Template Settings. ERROR:Bitgen:112 - OutputsActive must be UserClk 2, DI, DI+1, or DI+2 when StartupClk is UserClk and SyncToDone is Yes. ERROR:Bitgen:113 - GSRInactive must be UserClk 2, DI, DI+1, or DI+2 when StartupClk is UserClk and SyncToDone is Yes. ERROR:Bitgen:157 - Bitgen will terminate because of the above errors." The same for "JTAGCLK"! MarcArticle: 26223
Hi there, sorry for being maybe off-topic to FPGAs, but there is a good chance for an answer in this group as far as I prize the contents of the posted messages. I posted this message already to comp.arch. Unfortunately without response. Does anyone know a good online source for information about RAM-BIST algorithms and their impact on the different fault classes? What I want to know is for example what k-coupling faults or linked idempotent coupling faults are. Any help appreciated. Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 26224
Marc, For families prior to the Virtex family, there is no StartupClk option in bitgen. Only Virtex architectures (and this includes Spartan-II) require this option to be set. For configuration 4k devices via JTAG, I would recommend checking out the 4k Boundary Scan app note, here: http://support.xilinx.com/xapp/xapp017.pdf HTH, Mike In article <39E18046.B544E977@tu-harburg.de>, Marc Reinert <reinert@tu-harburg.de> wrote: > Can anybody tell me, what I have to do to activate the JTAG startup-clock? > > I'm using the Foundation Express 3.1 GUI. Sorry, but I didn't find this > option anywhere. > > I've tried to change the bitgen.ut file - but after rerunning the last step > of the flow engine it was set back to "startupclock:cclk" // seems to be > just a report. > > So I know what to do now but I didn't catch the point how to do this. > (Sorry) > > Marc Reinert > > Sent via Deja.com http://www.deja.com/ Before you buy.
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