Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@googlemail.c= om" <antti.luk...@googlemail.com> wrote: > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@googlema= il.com" > > > <antti.luk...@googlemail.com> wrote: > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@goog= lemail.com" > > > > > <antti.luk...@googlemail.com> wrote: > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > who have the available wrapper? > > > > > > wau do you think its only the wrapper you need? > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > then think how likely is to get a free IP > > > > > > Antti > > > > > asics.ws also has usb 3.0 solutions i think > > > > > i only need this wrapper. > > > > 1) contact PLDA > > > 2) contact asics.ws > > > 3) write yourself > > > > Antti > > > PS look at your rating: > > > you have been rated 20 times, and the rating score is 1 out 5, > > > means that.. [insert here....] > > > > there is no need for wrapper if you dont have the USB 3.0 IP > > > but if you have the IP, you would also have the wrapper.. > > > I have designed usb3.0 host controller sucessfully. but i need verify > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.- Hid= e quoted text - > > > - Show quoted text - > > try using 1GbE setting for MGT wrapper, if you test with your own test > IP it should work already > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - it doesn't work with PCIE GEN2 template. Can it work with 1GbE template? why?Article: 142776
On Sep 1, 6:56 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@googlemail= .com" > > > > <antti.luk...@googlemail.com> wrote: > > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@google= mail.com" > > > > <antti.luk...@googlemail.com> wrote: > > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wrote= : > > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@go= oglemail.com" > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > > who have the available wrapper? > > > > > > > wau do you think its only the wrapper you need? > > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > > then think how likely is to get a free IP > > > > > > > Antti > > > > > > asics.ws also has usb 3.0 solutions i think > > > > > > i only need this wrapper. > > > > > 1) contact PLDA > > > > 2) contact asics.ws > > > > 3) write yourself > > > > > Antti > > > > PS look at your rating: > > > > you have been rated 20 times, and the rating score is 1 out 5, > > > > means that.. [insert here....] > > > > > there is no need for wrapper if you dont have the USB 3.0 IP > > > > but if you have the IP, you would also have the wrapper.. > > > > I have designed usb3.0 host controller sucessfully. but i need verify > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.- H= ide quoted text - > > > > - Show quoted text - > > > try using 1GbE setting for MGT wrapper, if you test with your own test > > IP it should work already > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > it doesn't work with PCIE GEN2 template. > > Can it work with 1GbE template? why? writing a IP core is 10% of the work sim testbench, verification ,FPGA testing, test software, compliance testing, documentation make up the 90% are you asking i do that 90% for you? for 50% share of your potential profits, I might..:) or if you plan to open-source it, i also would help you but if you want to cash-in i will not do your work hm.. but u are welcome to contact me in private, still AnttiArticle: 142777
Nicholas If you have spare pins then it is worth having spare clock inputs. I'm a bit rusty on Cyclone-II but I think they need to go on specific pins for optimal use with PLLs etc.. One of the things you will see on our development boards is a spare 8 pin DIL socket for clock oscillators. That usually has a 3.3V power pin, avoiding overvoltage signal input to the FPGA on a 3.3V bank, and is a good way to leave your options open for other frequecies if you have the pins and board space. The 3.3V oscillators are not as common as the 5V varieties in the same package but still a good option. John Adair Enterpoint Ltd. - Home of Mulldonnoch2. The industrial processing board. On 31 Aug, 15:58, Nicholas Kinar <n.ki...@usask.ca> wrote: > > Forgot this - I would suggest a system clock in the area of 20-30MHz > > to start with. You can probably build a base system, with no PLLs, to > > get going with. > > Sounds good, John. =A0What I will do is select a 30MHz oscillator to star= t > off with, and I'll also leave space on my PCB to add other clocks to > clock input pins. =A0This will provide for situations when I think that > more clocks are required. > > Thanks, John.Article: 142778
Hi, I have one analog signal input. I want to apply at analog signal a transfer function of the type : y = a0 + a1 * x + a2 * x^2 + a3 * x^3 + a4 * x^4 + a5 * x^5 + a6 * x^6 + a7 * x^7 + a8 * x^8 + a9 * x^9 Polynomial semplification : y = a0 + x * (a1 + x * (a2 + x * (a3 + x * (a4 + x * (a5 + x (a6 + x * (a7 + x * (a8 + x * a9)))))))) There are specific techniques and/or optimization for building this polynomial on FPGA ? Kappa.Article: 142779
On Tue, 1 Sep 2009 00:38:54 -0700 (PDT), Kappa wrote: >I have one analog signal input. I want to apply at analog signal a >transfer function of the type : > >y = a0 + a1 * x + a2 * x^2 + a3 * x^3 + a4 * x^4 + a5 * x^5 + a6 * x^6 >+ a7 * x^7 + a8 * x^8 + a9 * x^9 > >Polynomial semplification : > >y = a0 + x * (a1 + x * (a2 + x * (a3 + x * (a4 + x * (a5 + x (a6 + x * >(a7 + x * (a8 + x * a9)))))))) > >There are specific techniques and/or optimization for building this >polynomial on FPGA ? The second form can very easily be pipelined. For streaming data such as your analog signal, and on an FPGA, pipelining is usually almost free. However, digitized analog input inevitably has a limited number of bits and it may be better to use a lookup table. You don't need the full resolution in your table; instead, store the function and its first difference, and use linear interpolation. Your function then becomes one lookup, one multiply and one add - instead of your nine multiply-add operations. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 142780
Hi Jonathan Bromley, > The second form can very easily be pipelined. =A0For streaming > data such as your analog signal, and on an FPGA, pipelining > is usually almost free. In fact, the realization is not difficult. > However, digitized analog input inevitably has a limited > number of bits and it may be better to use a lookup table. > You don't need the full resolution in your table; instead, > store the function and its first difference, and use linear > interpolation. =A0Your function then becomes one lookup, one > multiply and one add - instead of your nine multiply-add > operations. But this technique preserves the resolution of the classical technique, the old one ? Consider input of signed 18 bit with 15 binary point (in/out of function) and signed 32 bit with 15 binary point "a" coefficient. Thanks. Kappa.Article: 142781
Kappa wrote: > Hi Jonathan Bromley, > >> The second form can very easily be pipelined. For streaming >> data such as your analog signal, and on an FPGA, pipelining >> is usually almost free. > > In fact, the realization is not difficult. > >> However, digitized analog input inevitably has a limited >> number of bits and it may be better to use a lookup table. >> You don't need the full resolution in your table; instead, >> store the function and its first difference, and use linear >> interpolation. Your function then becomes one lookup, one >> multiply and one add - instead of your nine multiply-add >> operations. > > But this technique preserves the resolution of the classical > technique, the old one ? > > Consider input of signed 18 bit with 15 binary point (in/out of > function) and signed 32 bit with 15 binary point "a" coefficient. > The trouble with a large polynomial like this is that the higher power parts are very sensitive to the resolution. For polynomials expressed in this form, you'll want a great deal more binary point bits for the later a_n coefficients, or to use floating point (which makes things much more complicated). With care and enough bits, and different placement of the binary points depending on the values of a_n, you might make it work well enough. A lookup table with linear interpolation much easier to make accurately than a large polynomial like this. You could also compromise and use a lookup table and quadratic or cubic interpolation to get more accuracy from a smaller table. Another idea, if your maths is up to it, is to use Chebyshev polynomials instead of powers of x. You would need more multipliers (18 for a ninth power polynomial, if I've done my sums right) and more adders, but all your partial calculations and coefficients are on the same scale making it much easier. http://en.wikipedia.org/wiki/Chebyshev_polynomialsArticle: 142782
On Tue, 1 Sep 2009 01:48:15 -0700 (PDT), Kappa wrote: >> You don't need the full resolution in your table; instead, >> store the function and its first difference, and use linear >> interpolation. Your function then becomes one lookup, one >> multiply and one add - instead of your nine multiply-add >> operations. > >But this technique preserves the resolution of the classical >technique, the old one ? Well.... as the saying goes, "go figure". Linear interpolation (or any interpolation) can always give sufficiently good resolution, if the table points are sufficiently closely spaced. The details obviously depend on the values of your higher-order coefficients. >Consider input of signed 18 bit with 15 binary point (in/out of >function) and signed 32 bit with 15 binary point "a" coefficient. With an 18-bit input, you have only 128K different input values. It would be easy to write a small program to calculate all the result values, and then compare them with the values obtained by interpolation (or any other method). You can then decide whether the errors are small enough to be insignificant. Consider this, though. Suppose you make a 1024-entry table. Use the top 10 bits of your 18-bit data to address into the table. Use the lower 8 bits for linear interpolation. Now, the error introduced by ignoring the x^2 term is less than one part in 1,000,000. Assuming the x^2 coefficient (a2) is no more than 4 times bigger than the linear coefficient (a0), that means the error will disappear in your 18-bit result. The same argument applies, even more strongly, for the x^3 and higher terms. You will see significant errors in your 18-bit result only when you have a2, a3, ... coefficients that are much larger than a0, a1. I'm intrigued to know why you are applying a 9th order polynomial transfer function to your signal. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 142783
On Tue, 1 Sep 2009 00:38:54 -0700 (PDT), Kappa <secureasm@gmail.com> wrote: >Hi, > >I have one analog signal input. I want to apply at analog signal a >transfer function of the type : > >y = a0 + a1 * x + a2 * x^2 + a3 * x^3 + a4 * x^4 + a5 * x^5 + a6 * x^6 >+ a7 * x^7 + a8 * x^8 + a9 * x^9 > >Polynomial semplification : > >y = a0 + x * (a1 + x * (a2 + x * (a3 + x * (a4 + x * (a5 + x (a6 + x * >(a7 + x * (a8 + x * a9)))))))) > >There are specific techniques and/or optimization for building this >polynomial on FPGA ? > >Kappa. There are any number of ways to implement it; as Jonathan said your pipelined implementation is easy and cheap (though you will inevitably lose resolution through the successive multiplications; see below) His suggestion of interpolation is good, though I tend to add a quadratic term to guarantee accuracy (this requires three multiplications rather than one; but is accurate enough for single precision floating point; i.e. 24-bit or better accuracy, on square root, reciprocal, etc) Or if you prefer a direct implementation, consider the range of coefficient values for your higher order terms; they are typically small. Consider the rounding error imposed by truncating the product of x and the largest coefficient; you can reduce the resolution of the smaller multiplications until they introduce a similar (preferably still smaller) error with economic benefits (reduced resources) Or if latency is important, note that the slowest path, a9 * x^9 = (a9 * x) * ((x*x) * (x*x)) * (ditto) which takes 4 cycles to compute; plus a fifth to add it to the (parallel computed) sum of the faster paths. (Implementation issues may require additional cycles to move data between multipliers) Only you can determine if the loss of resolution due to e.g. truncating multiplier outputs,or economising on word widths is acceptable; i.e. within your error budget. This can be exhaustively tested in simulation (for a single variable input as here) by a testbench implementing comparison with an exact solution, and logging the magnitude and spread of errors. For a single-precision FP square root unit (quadratic interpolator) I tested all 2^24 input values in simulation in about an hour; you can afford to do this after any major design change if accuracy is important; normally I only re-tested the most sensitive region. But for prototyping the algorithm and testing e.g. the accuracy of an interpolated LUT, I suggest starting with a simple spreadsheet! You can truncate values to 16 (or 19) bits and quickly investigate tradeoffs to get a pretty good idea of what you are doing before moving to VHDL. - BrianArticle: 142784
Could anybody please show me a list of popular FPGA development
IDE/toolchains and their approximate costs? For GCC compilers we can put
the costs as 0.
It will be even better if you can give me your opinion about the
followings performance with 1-10 mark (10 the best, 1 the worst).
code density,
Speed of execution
targets and hosts supported
Other tools that work with it.
Support from vendor (et al)
Thank you!
Article: 142785On Tue, 01 Sep 2009 09:30:58 -0600 Johnson <gpsabove@yahoo.com> wrote: > Could anybody please show me a list of popular FPGA development > IDE/toolchains and their approximate costs? For GCC compilers we can > put the costs as 0. > > It will be even better if you can give me your opinion about the > followings performance with 1-10 mark (10 the best, 1 the worst). > code density, > Speed of execution > targets and hosts supported > Other tools that work with it. > Support from vendor (et al) > > > Thank you! Are you just posting one of these in every newsgroup there is? If I went and checked comp.lang.cobol would you have posted the same question, while putting the cost of the GCC COBOL compiler at 0? And I'd hate to see what you're asking in some of the alt.* groups. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 142786
On Sep 1, 6:30=A0pm, Johnson <gpsab...@yahoo.com> wrote: > Could anybody please show me a list of popular FPGA development > IDE/toolchains and their approximate costs? For GCC compilers we can put > the costs as 0. > > It will be even better if you can give me your opinion about the > followings performance with 1-10 mark (10 the best, 1 the worst). > =A0 =A0 code density, > =A0 =A0 Speed of execution > =A0 =A0 targets =A0and hosts supported > =A0 =A0 Other tools that work with it. > =A0 =A0 Support from vendor (et al) > > Thank you! its all matter of taste the baselevel tools cost 0.0 for the full packages need to pay code density: n/a (not applicable) FPGA do not execute compiled code, they implement a designed hardware function targets: all current FPGA's hosts: win/linux other: many support: depends AnttiArticle: 142787
Rob Gaddi wrote: > On Tue, 01 Sep 2009 09:30:58 -0600 > Johnson <gpsabove@yahoo.com> wrote: > >> Could anybody please show me a list of popular FPGA development >> IDE/toolchains and their approximate costs? For GCC compilers we can >> put the costs as 0. >> >> It will be even better if you can give me your opinion about the >> followings performance with 1-10 mark (10 the best, 1 the worst). >> code density, >> Speed of execution >> targets and hosts supported >> Other tools that work with it. >> Support from vendor (et al) >> >> >> Thank you! > > Are you just posting one of these in every newsgroup there is? If I > went and checked comp.lang.cobol would you have posted the same > question, while putting the cost of the GCC COBOL compiler at 0? And > I'd hate to see what you're asking in some of the alt.* groups. > Hi Rob, Take a deep breath before you yell out. I posted a question at comp.arch.embedded, and the other at comp.arch.fpga. They are different questions, aren't they? At comp.arch.embedded, I asked about toolchains about ARM, while at comp.arch.fpga I asked about toolchains about FPGA. I personally thought the toolchains for ARM and FPGA are different. However, I just started to learn about ARM and FPGA stuff recently, so I could be wrong. If you have different opinion, and are willing to help and share, please post. Thanks! JohnsonArticle: 142788
On Sep 1, 8:50=A0pm, Johnson <gpsab...@yahoo.com> wrote: > Rob Gaddi wrote: > > On Tue, 01 Sep 2009 09:30:58 -0600 > > Johnson <gpsab...@yahoo.com> wrote: > > >> Could anybody please show me a list of popular FPGA development > >> IDE/toolchains and their approximate costs? For GCC compilers we can > >> put the costs as 0. > > >> It will be even better if you can give me your opinion about the > >> followings performance with 1-10 mark (10 the best, 1 the worst). > >> =A0 =A0 code density, > >> =A0 =A0 Speed of execution > >> =A0 =A0 targets =A0and hosts supported > >> =A0 =A0 Other tools that work with it. > >> =A0 =A0 Support from vendor (et al) > > >> Thank you! > > > Are you just posting one of these in every newsgroup there is? =A0If I > > went and checked comp.lang.cobol would you have posted the same > > question, while putting the cost of the GCC COBOL compiler at 0? =A0And > > I'd hate to see what you're asking in some of the alt.* groups. > > Hi Rob, > > Take a deep breath before you yell out. > > I posted a question at comp.arch.embedded, and the other at > comp.arch.fpga. They are different questions, aren't they? At > comp.arch.embedded, I asked about toolchains about ARM, while at > comp.arch.fpga I asked about toolchains about FPGA. I personally thought > the toolchains for ARM and FPGA are different. However, I just started > to learn about ARM and FPGA stuff recently, so I could be wrong. If you > have different opinion, and are willing to help and share, please post. > > Thanks! > > Johnson lesson 1: FPGA's are NOT processors. they do not have "toolchain" as you have it for processor FPGA's are not programmed in they way you write programs for processor you dont write a program for FPGA, you DESCRIBE what hardware you need.. AnttiArticle: 142789
On Sep 1, 12:00=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 1, 6:30=A0pm, Johnson <gpsab...@yahoo.com> wrote: > > > Could anybody please show me a list of popular FPGA development > > IDE/toolchains and their approximate costs? For GCC compilers we can pu= t > > the costs as 0. > > > It will be even better if you can give me your opinion about the > > followings performance with 1-10 mark (10 the best, 1 the worst). > > =A0 =A0 code density, > > =A0 =A0 Speed of execution > > =A0 =A0 targets =A0and hosts supported > > =A0 =A0 Other tools that work with it. > > =A0 =A0 Support from vendor (et al) > > > Thank you! > > its all matter of taste > the baselevel tools cost 0.0 > for the full packages need to pay > code density: n/a (not applicable) FPGA do not execute compiled code, > they implement a designed hardware function > targets: all current FPGA's > hosts: win/linux > other: many > support: depends > > Antti You could convert "code density" to synthesis efficiency and possibly design size limits. Efficiency of synthesis is only partly covered by the tool vendor and partly by the chip manufacturer who makes the back-end for their highly proprietary internal structure. Regardless of whose tools you work with, the lowest level is provided by the chip maker. Zero-cost tools from the chip makers usually have the same features and efficiency as the paid tools from the chip makers, but they usually have fewer third-party add-ons and may not support all sizes of chips. That being said the chips they don't support generally cost as much as a full set of tools from the chip makers, i.e. even the paid versions are not really big bucks. Third party add-ons like ModelSim simulation are generally restricted in performance and design size. Modelsim uses these partnerships to attract paying customers when they get fed up waiting for a simulation to finish. Paid tools from third parties generally have some advantage in efficiency or ability to control your outcome, in addition to multiple chip-vendor support. They typically run big bucks compared to chip-maker versions. Many people justify the too expense by saying it makes them independent of the chip maker, but then proceed to use it only with a single chip vendor they get comfortable with. In recent years, the internal tool chains of the chip makers have narrowed the efficiency gap considerably with these third-party tools. Some tool makers to look at: 3rd party: Synplicity Aldec Mentor Chip vendors: Altera Xilinx Lattice Actel Have fun, GaborArticle: 142790
Antti.Lukats@googlemail.com wrote: > lesson 1: > > FPGA's are NOT processors. > they do not have "toolchain" as you have it for processor There are some advanced people in this newsgroup who writes their own makefiles to use the FPGA toolchain programs, which are really a set of tools, glued together with some Tcl/Tk hacks :-) But usually you just use the proprietary IDEs of the vendors. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142791
On Sep 1, 9:20=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Antti.Luk...@googlemail.com wrote: > > lesson 1: > > > FPGA's are NOT processors. > > they do not have "toolchain" as you have it for processor > > There are some advanced people in this newsgroup who writes their own > makefiles to use the FPGA toolchain programs, which are really a set of > tools, glued together with some Tcl/Tk hacks :-) But usually you just use > the proprietary IDEs of the vendors. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de yes, i do:) well the vendor flow, eh call it whatever you want, set of commandline tools it's not however like GCC toolchain for ARM GCC toolchain for AVR XXX toolchain for FPGA maybe i explained it wrong, the toolchain call so much for "GCC toolchain".. even if make is used to run FPGA vendor flow, it not the "C compiler toolchain" AnttiArticle: 142792
Petter Gustad wrote: > Altera has pretty good Linux support. I've been using Quartus under > Linux¹ for a couple years including JTAG programming, signaltap > debugging and NIOS II IDE debugging without any problems. I've also > used head-less Linux boxes as JTAG servers with the Altera programming > software. But why (oh why) is the free IDE only for Windows? It makes no sense to buy a (relatively) cheap development board i order to learn about FPGAs, only to have to shell out a major amount of money for a Linux IDE. And to use the Windows IED I'll have to invest in a Windows licence (and a machine capabe of running WinXP at least). Both ways I lose. > As for both Altera and Xilinx I've also used my own custom programmer > which is Ethernet attached. I simply send my programming file to the > programmer using tftp which is available for most OSes. Unfortunately, > I don't have any documentation on the signaltap and chipscope > protocols in order to support those :-( Interesting. Is this by any chance freely available / open source? -- Torfinn IngolfsenArticle: 142793
Thorsten Kiefer wrote: > Hi, > I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the Digilent > USB/JTAG cable. > I find ISE 11.1 too slow under Windows, so I want to use it with Linux. > My question is : is it possible to program the FPGA under Linux ? > Xilprg is too old. Export from digilent is discontinued and not available > for Linux. > Are there any alternatives ? I am partially moved over to Linux, and have both Windows and Linux Ise at the same time. What I am doing though, for Spartan 2E right now is programming SST serial flash memories with test configurations and then loading the FPGA from there. I need some logic on my board with the Spartan 2E, but Spartan 3 is supposed to be able to directly load from the SST memories. So, I built a simple parallel port programmer for the SST parts. It is a simple serial device, you load a 16-bit command word to erase, program or read back. The programmer has a 3.3 V power supply and a single CMOS chip as a level translator. I could probably let you have the c code for writing MCS files to the SST chip. It takes about 45 seconds to program the 1 mbit part. JonArticle: 142794
Frank Buss wrote: > Antti.Lukats@googlemail.com wrote: > >> Option 1: >> Get a PC with preinstalled WinXP/Vista and forget the attempts to use >> FPGA tools under linux >> This option saves lots of frustration and is worth the money spent > > I use Windows, too, but maybe a VMWare, or with another virtualization > software, you don't need at least an extra PC (I'm using this on my desktop > PC to run Debian Linux in VMWare, which works fine). Or install Linux and > Windows on one PC with a bootmanager like Grub (this is my Laptop setup), > but Murphy's Law says, that you just need some program for Linux fast (e.g. > phone call from a customer and you have to check something) when Windows is > booted and vice versa :-) > Windows 2K Pro running under VMWare works perfectly to program Xilinx CPLDs with the Parallel Cable III. I'm sure it would work fine for downloading FPGAs, also. (I just prefer EPROMS for that, as there are less cables, par ports, etc. required that way. If you are using ChipScope, then you need it hooked up anyway. JonArticle: 142795
Johnson wrote: > Could anybody please show me a list of popular FPGA development > IDE/toolchains and their approximate costs? Your choice of silicon more-or-less dictates the development tools you'll be using. Yes, there are 3rd party synthesis tools but for "entry level development" you're most likely looking at standard silicon vendor packages. As for choosing silicon, unless you have an application that can take advantage of a specific feature, the decision is to some degree a "religious" one. Sometimes the choice is even based on the development tools rather than the actual silicon. So your questions are, to a large degree, "not applicable". For entry-level, mainstream development you choose your silicon and you're stuck with the vendor tools as supplied. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 142796
On 9=D4=C21=C8=D5, =CF=C2=CE=E71=CA=B125=B7=D6, "Antti.Luk...@googlemail.co= m" <antti.luk...@googlemail.com> wrote: > On Sep 1, 6:56 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > > > On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@googlema= il.com" > > > <antti.luk...@googlemail.com> wrote: > > > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@goog= lemail.com" > > > > > <antti.luk...@googlemail.com> wrote: > > > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wro= te: > > > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@= googlemail.com" > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > > > who have the available wrapper? > > > > > > > > wau do you think its only the wrapper you need? > > > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > > > then think how likely is to get a free IP > > > > > > > > Antti > > > > > > > asics.ws also has usb 3.0 solutions i think > > > > > > > i only need this wrapper. > > > > > > 1) contact PLDA > > > > > 2) contact asics.ws > > > > > 3) write yourself > > > > > > Antti > > > > > PS look at your rating: > > > > > you have been rated 20 times, and the rating score is 1 out 5, > > > > > means that.. [insert here....] > > > > > > there is no need for wrapper if you dont have the USB 3.0 IP > > > > > but if you have the IP, you would also have the wrapper.. > > > > > I have designed usb3.0 host controller sucessfully. but i need veri= fy > > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.-= Hide quoted text - > > > > > - Show quoted text - > > > > try using 1GbE setting for MGT wrapper, if you test with your own tes= t > > > IP it should work already > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > it doesn't work with PCIE GEN2 template. > > > Can it work with 1GbE template? why? > > writing a IP core is 10% of the work > sim testbench, verification ,FPGA testing, > test software, compliance testing, documentation > > make up the 90% > > are you asking i do that 90% for you? > for 50% share of your potential profits, I might..:) > or if you plan to open-source it, i also would help you > but if you want to cash-in i will not do your work > > hm.. but u are welcome to contact me in private, still > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - it is very easy for me write the wrapper. i only want to know if the 1GbE template works for usb3.0 pipe PHY.Article: 142797
On 9=D4=C21=C8=D5, =CF=C2=CE=E71=CA=B125=B7=D6, "Antti.Luk...@googlemail.co= m" <antti.luk...@googlemail.com> wrote: > On Sep 1, 6:56 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > > > On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@googlema= il.com" > > > <antti.luk...@googlemail.com> wrote: > > > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@goog= lemail.com" > > > > > <antti.luk...@googlemail.com> wrote: > > > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wro= te: > > > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@= googlemail.com" > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > > > who have the available wrapper? > > > > > > > > wau do you think its only the wrapper you need? > > > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > > > then think how likely is to get a free IP > > > > > > > > Antti > > > > > > > asics.ws also has usb 3.0 solutions i think > > > > > > > i only need this wrapper. > > > > > > 1) contact PLDA > > > > > 2) contact asics.ws > > > > > 3) write yourself > > > > > > Antti > > > > > PS look at your rating: > > > > > you have been rated 20 times, and the rating score is 1 out 5, > > > > > means that.. [insert here....] > > > > > > there is no need for wrapper if you dont have the USB 3.0 IP > > > > > but if you have the IP, you would also have the wrapper.. > > > > > I have designed usb3.0 host controller sucessfully. but i need veri= fy > > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.-= Hide quoted text - > > > > > - Show quoted text - > > > > try using 1GbE setting for MGT wrapper, if you test with your own tes= t > > > IP it should work already > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > it doesn't work with PCIE GEN2 template. > > > Can it work with 1GbE template? why? > > writing a IP core is 10% of the work > sim testbench, verification ,FPGA testing, > test software, compliance testing, documentation > > make up the 90% > > are you asking i do that 90% for you? > for 50% share of your potential profits, I might..:) > or if you plan to open-source it, i also would help you > but if you want to cash-in i will not do your work > > hm.. but u are welcome to contact me in private, still > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - it is very easy for me write the wrapper. i only want to know if the 1GbE template works for usb3.0 pipe PHY.Article: 142798
On Sep 2, 4:21 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > On 9=D4=C21=C8=D5, =CF=C2=CE=E71=CA=B125=B7=D6, "Antti.Luk...@googlemail.= com" > > > > <antti.luk...@googlemail.com> wrote: > > On Sep 1, 6:56 am, "murl...@gmail.com" <water9...@yahoo.com> wrote: > > > > On 8=D4=C231=C8=D5, =CF=C2=CE=E73=CA=B122=B7=D6, "Antti.Luk...@google= mail.com" > > > > <antti.luk...@googlemail.com> wrote: > > > > On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wrote= : > > > > > > On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@go= oglemail.com" > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> w= rote: > > > > > > > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk..= .@googlemail.com" > > > > > > > > <antti.luk...@googlemail.com> wrote: > > > > > > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote: > > > > > > > > > > who have the available wrapper? > > > > > > > > > wau do you think its only the wrapper you need? > > > > > > > > ask PLDA what their USB 3.0 IP cores costs > > > > > > > > then think how likely is to get a free IP > > > > > > > > > Antti > > > > > > > > asics.ws also has usb 3.0 solutions i think > > > > > > > > i only need this wrapper. > > > > > > > 1) contact PLDA > > > > > > 2) contact asics.ws > > > > > > 3) write yourself > > > > > > > Antti > > > > > > PS look at your rating: > > > > > > you have been rated 20 times, and the rating score is 1 out 5, > > > > > > means that.. [insert here....] > > > > > > > there is no need for wrapper if you dont have the USB 3.0 IP > > > > > > but if you have the IP, you would also have the wrapper.. > > > > > > I have designed usb3.0 host controller sucessfully. but i need ve= rify > > > > > it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device= .- Hide quoted text - > > > > > > - Show quoted text - > > > > > try using 1GbE setting for MGT wrapper, if you test with your own t= est > > > > IP it should work already > > > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > > it doesn't work with PCIE GEN2 template. > > > > Can it work with 1GbE template? why? > > > writing a IP core is 10% of the work > > sim testbench, verification ,FPGA testing, > > test software, compliance testing, documentation > > > make up the 90% > > > are you asking i do that 90% for you? > > for 50% share of your potential profits, I might..:) > > or if you plan to open-source it, i also would help you > > but if you want to cash-in i will not do your work > > > hm.. but u are welcome to contact me in private, still > > > Antti- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > it is very easy for me write the wrapper. > > i only want to know if the 1GbE template works for usb3.0 pipe PHY. if it very easy why dont you do it? AnttiArticle: 142799
Hello to everyone, I have a question about sysgen simulation. This is the situation. I have design that have two clock domains. one will work on 133MHz and the other will work on 40MHz. from transition from one clock domain to the other I planed to use dual port memories and registers. but I was stacked when I tried to write testbench in matlab. I don't know how to archive this. is there any defined way how this is done. i noticed some block multiple system generator that i found out that should be used when differnet clocks exist in design. should I use this block as some help. I have never done system with two domains in sysgen so I am a little confused. thanks for help Zoran
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z