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Austin Lesea wrote: > Mike Treseler wrote: > > Austin Lesea wrote: > >> If you know you are going to use part A, or part X, you will then use > >> the powerful built in features that each vendor offers. > > > > Many do, but I don't. > > If the feature can't be inferred from code > > for both vendors, I'd rather not use it. > > Mike, > > Then you are not a high end user. How silly. You can infer DDR registers, shift-registers (which map flawlessly to SRLs), and even a number of math functions (which map to the latest V4 DSP48 blocks). What else does it take to meet your criteria of being be a high-end user? Have fun, MarcArticle: 80676
Hi..
If u r using EDK ..then when u invoke Create/Import Peripheral
Wizard..It will give u an option to enable DMA..so if u go on clicking
next..Finally u will have a user_logic.vhd file in the pcores directory
with some simple State Machine which can do a DMA for you..Even I am
trying this ..but not yet successful..ANd afterwards u need to write a
simple C code to enable the DMA and all other stuff....Even the
procedure to write the C code is generated in the VHD file as a side
note..
Have a good time DMA'ing....
--
Parag Beeraka
Article: 80677Just a quick (silly) question.. You have your clk signal coming in on a clk pin, you put it though a DCM or two and then it goes off to a global clk net in the FPGA.. Thats all fine with me.. In putting the clk though some logic (divider/counter) instead of DCM's, does the synthesis tool still put the end product on the global clock net?? I would hope that it does, but I'm worried that it would just treat it as another signal, due to the modifications that have been made... ThanksArticle: 80678
Hi..
Has anyone been able to download their own bitfile (other than
..ml310_pci_bootloop.bit) and run linux (by downloading the elf file )
using xmd...
What I did in generating my bit file is opened up EDK and then
added up my own core (an OPB core indeed ) changed the settings in
Software Platform to include linux_mvl31 for ppc405_0 and set the
parameters in Library / OS parameters ..Then I generated the
libraries...Then I obtained the download.bit file (which includes a
bootloop indeed )..I downloaded the bit file using iMPACT on to the ML
310 and then downloaded the linux kernel Image elf file using XMD ..but
I dont find any change on the serial port terminal.....
So If anyone had success in doing this stuff then please help me
out guys.....
Thanks in advance........
--
Parag Beeraka
Article: 80679Austin Lesea wrote: > Mike, > > You know your business, that is for sure. And based on that, you make > decisions. We have a number of customers who treat FPGAs as a commodity. > > Use no special features. Generic HDL only. > > Not my favorite model, but I know some folks use it. > > Austin I'm a big supporter of using generic HDL, because it makes your design portable. It's portable not just in a sense that you can synthesize the design on different platforms TODAY, but also that you can easily apply it to TOMORROR's hardware. Portability is one of the big philosophies behind the UNIX movement (and yes that is software, but the idea is the same). Without it, UNIX wouldn't have survived past PDP-11. My point is, utilizing some special features may get you 20% more performance today. But next year, some other vendor might come up with a good platform that runs 50% faster than your current vendor's platform. If you use generic HDL, very little, if any, efforts are needed to move on to the better technology or platform. Whereas specialized HDL designs will soon require too much effort to keep up with the new technology. Finally, the less technology-dependent your design is, the easier for you to leverage the advancement of the synthesizers. Maybe the synthesizers today cannot imply some of the logics to optimal components, but tomorrow they will be able to. Having said so much about generic HDL, I also insist that HDL designers should know what exactly they are designing. Sometimes what the synthesizers generate is not what you really want, in which case you have to step in. -jzArticle: 80680
Hello Brendan Thanks for the reply. When we enter a frequency for the primary input in Xpower, for example 1 Mhz, does it consider the input to be a square wave ? My primary inputs do not toggle every cycle, so the term "frequency" is confusing to me. any clarification is greatly appreciated. Thanks swamy Brendan Cullen wrote: > Hi Swamy, > > swamydp@yahoo.com wrote: > > > Hi > > > > what algorithm does xpower use to calculate the freqency of internal > > nodes in a netlist ? is it some kind of transition density propagation > > but that method requires activity factor for primary inputs and also > > probabilities of primary inputs. > > > > Also is the interconnect power dissipation taken into account ? > > The most basic method is through user i/p. Others include importing > simulation information and also the use of a probability algorithm in how > primary i/ps are propagated. > > The interconnect power dissipation is definitely taken into account. > > Brendan > > > > > > > Thanks for any help > > swamyArticle: 80681
Hi Marc Sorry if it wasnt clear, I understand what resets are used for, and your examples are no different to what I was thinking off, and they are still asyncronous arnt they?? I dont understand what issue there is over multiple clock domains, which is the essence of this topic though.. ThanksArticle: 80682
Hi Paul, > There are distributor FAEs, factory FAEs, and others who will hold your > hand and give you a back-rub if it helps you be successful with their > product! I'm good with back-rubs, but I specialize in Shiatsu, which helps a great deal but isn't pleasant at all. BenArticle: 80683
"Mentor Graphics will not allow an inexpensive license switch from our present VHDL to the verilog" Try asking if they can trade a verilog license for a vhdl license that you can spare for the time being.Article: 80684
Looks like no chance dude. better go for higher device.Article: 80685
When I tried Xilinx Webpack 6.3, I noticed that the XST (Xilinx Synthesis Technology) was missing some Verilog-2001 features. For me, the showstoppers were no $signed and $unsigned system- tasks. (I know they don't do anything when moving between signed<->unsigned vectors of identical bit-width, but our RTL uses them to clearly denote the designer's intent.) And lack of Verilog macro-arguments ... `define MINIMUM2( x , y ) ( ((x) < (y)) ? (x) : (y) ) ^^^ This causes XST preprocessor to throw a syntax-error. Have these issues been addressed?Article: 80686
Hi Adrian > Number of occupied Slices: 2,625 out of 1,920 > 136% > (OVERMAPPED) This part of your design report shows that the core does not fit into the X3S200 device. With some luck you can use different synthesis constraints and higher efforts for the mapping and PAR to reduce the number of occupied Slices. Have a nice synthesis EilertArticle: 80687
Well he asked for opinion Al vs Xi and here is my frank ones. The X men have literally flooded the market geographically as well as through their wares and it is definitely easier to get hold of them or their chips.. Infact the above factors alone many times dictate the choice of device rather than their actual performance and cost. We are a design consultancy and distribution services firm -xilinx being one of them. And I havent heard my colleagues in design speak of let alone try Al for the designs. I felt I was blindsided with all this marketing and patronising attitude of xlx presence and downloaded a web version of quartus-2 for taking a look at the other world sans xilinx. I find the tool cool and very methodical in its workings and good qor. Well thats for me as an individual and I cant see myself convince managers here to checkout those. They instinctively believe that xilinx is the FPGA.Article: 80688
"Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag news:1110439773.500523.62780@z14g2000cwz.googlegroups.com... > Well he asked for opinion Al vs Xi and here is my frank ones. The X men > have literally flooded the market geographically as well as through > their wares and it is definitely easier to get hold of them or their > chips.. Infact the above factors alone many times dictate the choice of > device rather than their actual performance and cost. We are a design > consultancy and distribution services firm -xilinx being one of them. > And I havent heard my colleagues in design speak of let alone try Al > for the designs. I felt I was blindsided with all this marketing and > patronising attitude of xlx presence and downloaded a web version of > quartus-2 for taking a look at the other world sans xilinx. I find the > tool cool and very methodical in its workings and good qor. Well thats > for me as an individual and I cant see myself convince managers here to > checkout those. They instinctively believe that xilinx is the FPGA. > Hi Neo, you are not the only one who has looked at Altera Quartus for 'second opinion' and yes the Altera tools are easy now as are the Xilinx ones, there are some differences but those are mostly only a matter of taste and personal preferences. for both X and A, you create a project, select part, add source, assign pinlock then hit compile then start programmer and hit program and you have a working silicon. Even being X man, I have to admit that the SignalTap is probably easier to use (even when not so powerful) than ChipScope and that the Quartus programmer is a bit better than iMpact (what is actually a nighmare in my opinion). I was also impressed when i did see the Altera Eclipse IDE to succesfully configure and compile NIOS II uClinux kernel and filesystem on Windows machine, doing it for Microblaze requires compilation on linux host so far. AnttiArticle: 80689
Hi all I want to design a 1024 poles FIR filter on FPGA. But I had no experiences on large scale FPGA programming. Can anybody tell me which chip should I use? mike -- ezpcb.comwww.totallychips.com - VHDL, Verilog & General Hardware Design discussion ForumArticle: 80690
I think you should not use atlpll,and you should app the megafunction to implement your project.Article: 80691
Hi Kevin, Well, I'm saying change the design so the full flag is combinatorial. Paul did say he was re-designing it, as it doesn't work. OK, the way this works is that the metastability only happens on the write side as a read completes, and on the read side as a write completes. So, you're correct that there are flag errors occasionally, but catastrophic errors, no. The bitbucket retains its integrity! (Given you follow the bit at the end of my post about completion) There's always a least one space/item to fulfill the requests from either side. There are false positives (harmless) for the flags but never false negatives (catastrophic). Gray code merely reduces the number of false positives. You still have to cope with this whatever code you use, so don't bother with Gray code. I've never liked Gray code, and never needed it. I think! Cheers, Syms. "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:d0nivd$bov4@xco-news.xilinx.com... >I think his main problem is that the full flag doesn't deassert when data >is read out because the full flag logic isn't being clocked. It asserts >OK. Besides, the method described will yield catastrophic errors. >Comparing non-Gray-coded pointers across domains during a transition will >result in reading values that are neither the current nor next value, >meaning that the full flag can be deasserted when the FIFO is full, causing >the user to write data into the bitbucket. > > Symon wrote: >> Paul, >> Hang on, isn't this easy? Only the write side is interested in the Full >> Flag, right? The write side is throttled. That makes it a lot easier. >> So, you have a binary coded incrementing write pointer. It points to >> where the next data will be stored. You have a binary coded incrementing >> read pointer. It points to where the next read comes from. Use a >> combinatorial comparison to see if the read pointer is one more than the >> write pointer. If so, report full to the write side. This 'full flag' can >> only be seen as metastable by the write side if a read has just happened. >> In which case write or don't write doesn't matter. There will be space. >> On the read side use a combinatorial comparison to see if the read >> pointer is equal to the write pointer. This means empty. This 'empty >> flag' will only be seen as metastable by the read side if a write has >> just happened. In which case a read or not read cycle is OK, there will >> be data to read. >> No Gray code nonsense needed as long as you don't mind a few transient >> false fulls and empties. You could add extra stuff if you wanted to fill >> the thing right to the brim, because then the full and empty conditions >> both have the pointers equal. >> You also need to make sure, when empty, the write cycle completes before >> the read side can see the 'empty flag' go away. And vice-versa. >> Cheers easy, Syms. >> p.s. My spell checker suggests detestable instead of metastable. How >> appropriate! >>Article: 80692
Hey Mike, You can use whatever chip you want as long as you tell me how you're gonna make poles with a FIR filter. The F in FIR stands for finite. A pole implies infinity. Infinity is more than 1024. Does not compute. Cheers, Syms. "ezpcb.com" <ezpcb.com.1lo4m0@info@totallychips.com> wrote in message news:1110441608.f90fef421894acf05b3ae0622b4253ec@teranews... > > Hi all > I want to design a 1024 poles FIR filter on FPGA. But I had no > experiences on large scale FPGA programming. Can anybody tell me which > chip should I use? > > mikeArticle: 80693
Hi all I'm starting a new project for DSP on FPGA , I got an experiance in VHDL but I want to start dealing with C/C++ coding for Hardware description. So any one can help me to answer the following questions: 1) Which is better to start with SystemC or HandelC and what is the major different between them. 2) What tools avaliable for both of them. 3) What is the best avaliable references for both. Thank you all Ahmed ElhossiniArticle: 80694
Hello everyone, I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ USER4 JTAG commands from my software. I have used my software to access such USER1, USER2 commands in previous generation FPGAs such as Virtex-II. Virtex 4 uses different JTAG command bit patterns (10 bit long) and I changed the table so that JTAG commands to be issued have the correct JTAG command bit patterns. Anyway, after spending hours and hours, I couldn't make it working. The JTAG command sequence seems correct as far as I see in the scope and HEX print out. Also, I can get the correct IDCODE using JTAG IDCODE command. IDCODE = 10'b1111001001 USER1 = 10'b1111000010 I added probes to BSCAN module signals so that I could see the signals coming out from the BSCAN module. But I didn't see any signals coming out from the BSCAN module even I tried all USER1 ~ USER4 commands. (ex. sendIR(USER1) + readDR()) My question is "Does anybody try using the Virtex4 USERx JTAG command?" If anybody have tried it, I definitely would like to hear that. I checked the Internet newsgroup as well as Xilinx support but so far, I cannot find any relevant info regarding to this. Any info, any suggestions would be highly appreciated. Best regards, Aki NiimuraArticle: 80695
read the ERRATA !!! V4 ES silicon only has USER1 command USER2,3,4 are not working at all. Antti PS the USER1 seems to work as the XMD and ChipScope both can communicate over USER1 <akineko@gmail.com> schrieb im Newsbeitrag news:1110446449.077000.311890@o13g2000cwo.googlegroups.com... > Hello everyone, > > I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~ > USER4 JTAG commands from my software. > > I have used my software to access such USER1, USER2 commands in > previous generation FPGAs such as Virtex-II. > > Virtex 4 uses different JTAG command bit patterns (10 bit long) and I > changed the table so that JTAG commands to be issued have the correct > JTAG command bit patterns. > > Anyway, after spending hours and hours, I couldn't make it working. The > JTAG command sequence seems correct as far as I see in the scope and > HEX print out. Also, I can get the correct IDCODE using JTAG IDCODE > command. > > IDCODE = 10'b1111001001 > USER1 = 10'b1111000010 > > I added probes to BSCAN module signals so that I could see the signals > coming out from the BSCAN module. But I didn't see any signals coming > out from the BSCAN module even I tried all USER1 ~ USER4 commands. (ex. > sendIR(USER1) + readDR()) > > My question is "Does anybody try using the Virtex4 USERx JTAG command?" > > If anybody have tried it, I definitely would like to hear that. > I checked the Internet newsgroup as well as Xilinx support but so far, > I cannot find any relevant info regarding to this. > > Any info, any suggestions would be highly appreciated. > > Best regards, > Aki Niimura >Article: 80696
"Jens Baumann" <annonce05_nospam@web.de> schrieb im Newsbeitrag news:422ee0fe$0$29285$14726298@news.sunsite.dk... > Ulrich Kloidt wrote: > > > Hello Jens, > > > > Altium is offering an eval board with a Xilinx® SpartanT-3 FPGA Device > > (XC3S400-4FG456C) for EUR 99,-. You can order it from the local Altium > > office located in germany. More info about this board is available at: > > > > http://www.altium.com/livedesign/ > > > > It comes with a 1 moth eval license of the Altium Nexar Software. But in > > case you don't want to purchase the Nexar software afterwards you can > > still use the board as a 'normal' evaluation board together with the > > Xilinx software. > > Yes, I found this board yesterday and I think, I will order it. Does Altium > somewhere confirm, that the board is usable with the Xilinx software? > > Jens I haven't found it written somewhere explicit. But I've checked the PDF file containing the schematics of the LiveDesign eval board. And herein the parallel port interface schematic is listed in chapter 'ISE Parallel Port Interface' too. It is described as 'Printer Port JTAG Interface (ISE Compatible)'. --- UlrichArticle: 80697
Hi! I've been having a really weird problem with a Xilinx Virtex-E XCV1000E development board from AVNET. I've got a VHDL design that I've been working on since october last year. When I upload the compiled design into the FPGA, everything works fine except after a couple of seconds (10s or so), the board resets itself and the FPGA is reprogrammed with the onboard design. (There is a sample design in an onboard ROM chip. I download my design via the JTAG interface.) When I take an old design (Tuesdays' in fact), everything runs fine and stable. The only change is that I make two instances of a module instead of one. The module is a self-written serial multiplier with RAM and ROM. The only difference between the two instances is a different ROM configuration (ROM data). The input lines (20-30 lines) are identical and the output lines (three of them) are treated very similar. I have already consulted my University colleagues, but so far without results. I already checked temperature, the clock/reset nets and I/O pin assignment. Everything looks fine to me, but I'm certainly not an FPGA wizard... Any ideas? Any recommended course of action? Thanks for your help! Cheers, -- UlfArticle: 80698
Hello, I am writing a character controller using Altera MAXII device. This controller will monitor the input signals from lpt port. I make a simulation and download to real chip to verify function, but unfortunately it won't work as I designed. The simulation show that the state translate signals was initiated abnormal.. I pass this to Altera local FAE, no one knows why, and their "my support", no response. I also make the simulaiton on their QII 4.1 and 4.2, the result is the same. Since I can't post my code and result here. If you are interested, I can mail to you for your reference! Thank you in advance. BR, JohnsonArticle: 80699
Hi everbody, The Stratix PCI kit is a 32/64-bits PCI board from Altera with 256 MB of DDR SDRAM (SO-DIMM). This kit includes a nice reference design that has a PCI to DDR bridge. We would like to use this design as a starting point for our own designs. Unfortunately this design only works with the old Quartus II v2.1 and the v1.2.1 SDRAM IP Megacore from Altera. Importing the older project in the newer Quartus 4.2 does not work. We tried creating a new project with the cores, pin settings, constraints etc. But the only thing that can be read from the DDR memory is garbage. Worse, it even gives this garbage when the SO-DIMM module isn't even inserted (it reads out: 9d66001b .... 9d22001b, while the working design gives something like ffff00 in that case (which is far more logical for disconnected hardware IMHO). We tested this with both the old and the new SDRAM Megacore. Could this be some project setting we overlooked? Byte lanes? Assignments? LogicLock settings? I tried asking Altera for help, they suggested downloading a newer PCI core because it included a newer reference design. Unfortunately that one doesn't use DDR but SDR instead. Then I asked if they could send me a reference design from one the newer kits (hoping to extract some useful information from it), and they said they can't (???). It probably has something to do with the datapath, because the system reads out garbage from the 'memory' even when the module isn't psysically present in the system. Though, I don't understand why... Anybody had any luck converting the (kit included) PCI 2 DDR reference design (Quartus II 2.1) to the new Quartus 4.2? Have a nice day! -- Edwin
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