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> V4 ES silicon only has USER1 command USER2,3,4 are not working at all. Antti, you saved my day. I was actually using USER2 command and my Virtex-4 is an ES part. > read the ERRATA !!! These day so many thing I need to read and everybody is using ERRATA to justify the bugs they made (actually I do, too). But I should have been more careful about such. Anyway, thank you for your prompt response. Best regards, Aki NiimuraArticle: 80726
Leave it to the posters, please, to choose the posting style. If you're reading the newsgroup regularly, you're familiar with the deiscussion threads and don't always need to review. Many newsreaders open the message and response for top-posting friendly operation. I often skip messages entirely that are bottom posted because the topic is *probably* not of interest and it's not worth the bother of scrolling down to see if there IS something interesting. It is NOT always "easier to read" it's just easier for you. - John_H "Jason Zheng" <xin.zheng@jpl.nasa.gov> wrote in message news:d0q7hi$rmq$1@nntp1.jpl.nasa.gov... <snip> > No offense, but would you please stop top-posting on news groups? > Bottom-posting is easier to read, especially when quoting several > responses. This website has more explanations on why: > http://www.caliburn.nl/topposting.html > > JasonArticle: 80727
Jason, My preference is for top posting. I am sorry it offends you, but I think "top down", not "bottom up." I will just erase the other stuff, as it usually has not value in the post anyway. AustinArticle: 80728
Hi there, > We do not have any constraints on any of the I/O going to the > SRAM/Flash. The assumption is that since these are registered I/O that > it would not be necessary. Is this assumption correct? Unfortunately not. If you run the core at 92MHz, there's a fairly good chance that Quartus clumps the logic together in some part of the FPGA in order to easily meet the Fmax. It may use registers on the data in/out bus, but these may be somewehere in the center of the die as well, causing long setup and hold times anyway. Given your clock frequency requirements, I would suggest setting global Tsu and Tco constraints of about 8ns (which will leave you ~3ns of PCB flight time). Best regards, BenArticle: 80729
And: MGTs, Power PC's, EMAC's, APU's. Lots of things that synthesis does poorly, or not at all. Oh, but Altera doesn't have any of these .... so they would not want to direct your attention to items that they are completely missing (in their product offering). AustinArticle: 80730
glen herrmannsfeldt wrote: > Following the unix analogy, where some low level parts might be > written in assembly, write the generic HDL, and then replace > specific modules with custom versions to get the extra > performance. > > -- glen Thanks for the good laugh. While this may hold fine for small designs, my humble experience is that the synthesis tools behave so non-linear with complex ones that even Mr. Spock would tremble. Change a bit here, resize a vector there, swap your tool version and your costly performance analysis and custom optimization --including your manual, wrist straining P&R-- are valid no more. However, I have found that most of the tools behave generally well after pipelining your design. *If* you break your signal flow and processing adequately, the register-isolated parts are treated again as 'simple designs' by the synthesis tool and you are back on track. Cheers. -- /"Contrary to what my colleagues have told you PabloBleyerKocik/ about the bleak prospects for silicon transistors, pablo / I happen to have a few of them here in my pocket." @bleyer.org / -- Gordon Teal at one 1954 IRE conference.Article: 80731
John Adair wrote: >Worth looking at Platform Flash for size and price. Usually much cheaper >than the older programming prom families. > >If this is a new board then go the further stage and use Spartan-3 your >design. You will have to protect the Spartan-3 against 5V and may need 5V >level shift if you have 5V CMOS level logic but you will benefit still from >cost savings etc. Spartan-2E will need the similar protection and level >shifting so no advantage over Spartan-3 in this respect. Spartan-2E is >generally dearer than Spartan-3. > > Spartan-3 only comes in even bigger sizes than Spartan-IIe! The SPROM kills the cost advantage. I'm loading my XCS30 FPGA from a 256 KBit SPROM. I have to go to a 512 KBit SPROM to use the XC2S30, but the smallest Spartan-IIe part is the XC2S50xxE, which bumps you up to 1 MegaBit. >It is also worth getting in contact with the Xilinx University Program if >you are a student or within an academic department. They can help out >various aspects FPGA selection etc. > > Nope, not a university project. This email is my "day job", the project in question is for my own business. Anyway, the design fits just fine in the XCS30 chip, so I don't want to be forced into a larger array needing more config bits. Thanks, JonArticle: 80732
Gabor wrote: >Be sure your design fits in the part you are choosing, first. Note >that >the XCS30 has a lot more CLB's than the XC2S30. The "30" K-gate number >in the Spartan II comes partially from the block RAM you didn't have >in the older part. > Yikes! I didn't realize this! Thanks for bringing it to my attention! > >Look at PlatformFlash (1 Mbit minimum size at about $3 in quantity). > Does this emulate a serial PROM? Or, do I need address counters and shift registers to make a serial stream? (I guess if it is byte-wide, I could use the parallel configure mode.) >If you >go this way the Spartan IIE looks better unless you have 5V interfacing >issues. > Everything external is 5V. But, I can buy a lot of level translators for the $15+ difference between 5V Spartan and Spartan-II. > Using a cheaper PROM loses its advantage if you need to add a >CPLD to interface it. > Clearly. And, another part to program, too! But, if I can do the interface with only 2 74HC-type chips, that is not too bad. > Also the PlatformFlash is easy to program in >system >using iMPACT. > > > >Before the PlatformFlash came along I used Atmel Dataflash parts for >large bitstreams (16Mbits +), but in that case I had a tiny micro >to help with the job. For something like a 2-wire serial EEPROM >(24C512) you could add a PIC micro for under $1 and get the job >done if you're not too worried about the total configuration time. > > Well, as I said, I think I've figured out a way to use slave serial mode to do a slightly slower config with only 2 74HC chips. Nothing to program but the PROM, and it can go as fast as the PROM can spit it out (400 KHz). But, I'll look into this PlatformFlash. Thanks, JonArticle: 80733
I'm really enjoying the 'generate' feature of Verilog-2001. However, I'm wondering if I can use it or something similar to add ports to the port list. I'm pretty sure I can't but I thought I'd ask. For example, if the number of ports is, say, four, I want to have four data buses in the port list, like so: input [15:0] databus0, input [15:0] databus1, input [15:0] databus2, input [15:0] databus3, ... Obviously for single-bit signals I can put them in a bus which has a width of four. But for buses, I either have to instantiate them separately, or have a 2-dimensional port, like [15:0] databus[0:3], which I don't think I can do. -KevinArticle: 80734
i'm trying to do that. i think it must be done with prochip designer, but prochip doesn't suport atf750 :-? what's happen with atf750? its only supported by wincupl? help thanksArticle: 80735
I very much disagree. Before Google changed their format they would only display the first 30 or so lines of the message. You would have to follow a link to get the rest. Then, when you came back to the thread, you were redirected to the start of the thread, losing your place in the thread. You were left to your own devices to locate the last message read. What a pain, especially for the 1-2 line responses! Tom BTW, if you want to start imposing netiquete on everyone else please get yourself elected dictator first. Jason Zheng wrote: > Austin Lesea wrote: > > Jason, > > > > All very good points. > > > > My point was simply that a power user trying to get the last 2 ps out of > > their design usually ends up using the features specific to that part, A > > or X. > > > > By doing so they often can use a lower speed grade part, or a smaller > > part, and save a lot of money. > > > > (No offense intended to anyone). > > > > Austin > > > > Austin, > > No offense, but would you please stop top-posting on news groups? > Bottom-posting is easier to read, especially when quoting several > responses. This website has more explanations on why: > http://www.caliburn.nl/topposting.html > > JasonArticle: 80736
Kevin, Unfortunately, I don't thing the generate statement can do conditional port generation. I also know from personal experience that 2-dimensional ports are not allowed. One nice thing you can take advantage of in this vein is to not declare every port when you instantiate something. So you declare all the possible ports you could need, but only instantiate the ones you want. For instance, if you have databus0, databus1, databus2, and databus3 as ports, you can still just instantiate the module as <code> mymodule i_mod ( .databus0(i_databus0), .databus1(i_databus1) ); </code> Perhaps not a very convenient solution, but it might be better than nothing. MikeArticle: 80737
But are you using a dedicated SPROM? The Spartan-3E is designed explicitly to gluelessly take advantage of cheap SPI memories allowing a very low configuration cost even if it takes more configuration bits. Lower than the other solutions you appear to be considering. If you were making 500k units in the end of 2006, your price for the XC3S100E plus an SPI PROM would be about $2.50. "Jon Elson" <jmelson@artsci.wustl.edu> wrote in message news:4230D706.8030007@artsci.wustl.edu... <snip> > Spartan-3 only comes in even bigger sizes than Spartan-IIe! The SPROM kills > the cost advantage. I'm loading my XCS30 FPGA from a 256 KBit SPROM. > I have to go to a 512 KBit SPROM to use the XC2S30, but the smallest > Spartan-IIe part is the XC2S50xxE, which bumps you up to 1 MegaBit. <snip> > I don't want to be forced into a larger array needing more config bits. > > Thanks, > > JonArticle: 80738
Austin, Just out of curiosity, why do you start new threads about material that was discussed in already existing ones? By my count, this is thread number 4 on the same topic; all started by you in response to an article in a different thread (correct me if my counting is wrong). Would you mind sharing the reason for this? Thanks, Ljubisa Bajic Austin Lesea <austin@xilinx.com> wrote in message news:<d0prbq$7055@cliff.xsj.xilinx.com>... > Paul, > > I posted what the worst case was (more than a week ago). > > If you are using our parts, and you want to know, your FAE can tell you > everything, including plots from thousands of parts, over all the corners. > > In other news -- > > "Virtex-4 FPGA Availability: > > Virtex-4 LX25, LX60, LX100, SX35, SX55, and FX12 are shipping today. > Xilinx now has a total of 14 FPGAs in production at 90nm, more than > three times the number of its nearest competitor." > > > AustinArticle: 80739
soar2morrow@yahoo.com wrote: > I very much disagree. > > Before Google changed their format they would only display the first 30 > or so lines of the message. You would have to follow a link to get the > rest. Then, when you came back to the thread, you were redirected to > the start of the thread, losing your place in the thread. You were left > to your own devices to locate the last message read. What a pain, > especially for the 1-2 line responses! > Whether what google groups did was good or bad is still questionable. You cannot judge the merits of style based on ONE application that you use to access newgroups. > > BTW, if you want to start imposing netiquete on everyone else please > get yourself elected dictator first. > Tom, and to all those who insist on top-posting, what I said was merely a suggestion to a user Austin, because she quoted a few posts that have a top-down chronological order, and she put her replies on the top. And that annoyed me a bit. If it offended anyone, I'm sorry.Article: 80740
Hi..
I got the thing working ..I added my own core to the Xilinx
example , set the address ranges and it worked fine ...Many many thanks
for the reply..
--
Parag Beeraka
Article: 80741Austin Lesea wrote: > And: > > MGTs, Power PC's, EMAC's, APU's. > > Lots of things that synthesis does poorly, or not at all. > > Oh, but Altera doesn't have any of these .... so they would not want to > direct your attention to items that they are completely missing (in > their product offering). Howdy Austin, What is this? http://www.altera.com/products/devices/stratixgx/features/sgx-transceiver.html True is isn't a full PPC, but they have processors too: http://www.altera.com/products/devices/stratixgx/features/sgx-stratixgx_nios.html I suppose APU is an arithmetic processing unit, i.e. a DSP block - you know, the one that had an accumulator long before Xilinx: http://www.altera.com/products/devices/stratixgx/features/sgx-dsp.html Have fun, MarcArticle: 80742
Antti Lukats wrote: > read the ERRATA !!! > > V4 ES silicon only has USER1 command USER2,3,4 are not working at all. > Additional info: I found Xilinx Answer Record #20129 mentioning the problem in the Virtex 4 LX25 ES part. > General Description: > LX25's BSCAN_VIRTEX4 RESET and DRCK signals might not function > as expected on the ES parts. > > Solution 1: > > To work around this issue, simply invert the RESET output and > avoid using DRCK signals when the JTAG_CHAIN attribute is set > to other than "1". However, since this issue will be fixed > in a future device revision, implementing this work-around > might result in an incompatibility with this future revision. // In short, LX25's JTAG BSCAN block is broken (ES part). I painfully found that the JTAG Reset signal polarity was inverted! Hope other people won't stumble on this problem like me. Aki-Article: 80743
Ed McGettigan wrote: > Vladimir, > > I apologize, but this answer record is misleading. There > are two different physical types of Gigabit Ethernet, the > Base-T versions and the Base-X versions. What you are > describing is that you want to implement a 1000-Base-T > which is a RJ45 connector and CAT5/5e/6 cable and you can not > do this directly from a RocketIO MGT. > > The RocketIO MGTs are electrically and physically compliant > to the Base-X versions (SX/LX), but not the Base-T version. > If you want to drive Base-T and you want to drive it with > a RocketIO MGT, then you need to use it configured as a SGMII > interface either to a discrete 1000-Base-T Phy (less expensive), > or to a SFP cage with a 1000-Base-T module (more expensive) > instead of the normal SFP optical module. > [...] Howdy Vladimir, Just to be perfectly clear, the 1000Base-X that Answer Record 13928 is referring to is *fiber* based Ethernet. SGMII is one way to interface to GbE phy's. xGMII (RGMII is what we use) is another, possibly easier way (or at least, slower speed that doesn't require MGT's). Physical layer chips for 1000Base-T cost something over ~$10/port. 1000Base-T SFP's cost something approaching 10x that (depending on volume). Good luck, MarcArticle: 80744
adrian wrote: > backhus escribi=F3: > > > >> Number of occupied Slices: 2,625 out of 1,920 136% > >> (OVERMAPPED) > > > > This part of your design report shows that the core does not fit into > > the X3S200 device. > > With some luck you can use different synthesis constraints and higher > > efforts for the mapping and PAR to reduce the number of occupied Slices. > > Tnankyou for your reply. > How can I configure EDK for using other/better synthesis constraints and > higher efforts? Howdy Adrian, You may be able to drive the LUT utilization and the number of occupied slices down closer to 100% by turning on timing-based mapping (timing) and turning your -k (Map to input functions) option on MAP to its maximum, but I'd be a little surprised if made your design small enough to fit. Are you sure there isn't logic you can optimize manually (yourself)? Good luck,=20 MarcArticle: 80745
dwerdna wrote: > Just a quick (silly) question.. You have your clk signal coming in on > a clk pin, you put it though a DCM or two and then it goes off to a > global clk net in the FPGA.. Thats all fine with me.. > > In putting the clk though some logic (divider/counter) instead of > DCM's, does the synthesis tool still put the end product on the global > clock net?? I would hope that it does, but I'm worried that it would > just treat it as another signal, due to the modifications that have > been made... Xilinx will let you do crazy things to clocks before you put them on the global clock net, with no objections. MarcArticle: 80746
dwerdna wrote: > Hi Marc > > Sorry if it wasnt clear, I understand what resets are used for, and > your examples are no different to what I was thinking off, and they are > still asyncronous arnt they?? I dont understand what issue there is > over multiple clock domains, which is the essence of this topic > though.. When you release the reset, it may be asynchronous to the clock - so some FF's may come out of reset before others. That can cause problems for things like state machines and counters. Search comp.arch.fpga (and probably comp.lang.vhdl) for reset+release ... Have fun, MarcArticle: 80747
> Tom, and to all those who insist on top-posting, what I said was merely a > suggestion to a user Austin, because she quoted a few posts that have a > top-down chronological order, and she put her replies on the top. And that > annoyed me a bit. If it offended anyone, I'm sorry. Well, you've one upped me. Things have gotten heated between Austin and I before, but I don't think I've ever called him a her ;-) - PaulArticle: 80748
> The mega function created has a pin called input (or similar). You simply > connect this to a device pin, and then assign the location you need for > the CLKn pin. Yes, that's the correct way to do it. Hook up a design input pin to the PLL input, then assign that input to a clock I/O. - PaulArticle: 80749
Fernando Peral wrote: > i'm trying to do that. i think it must be done with prochip designer, > but prochip doesn't suport atf750 :-? what's happen with atf750? > its only supported by wincupl? help So why not use WinCUPL ?. The 750 is a simple chip, (at the 22V10 end of the spectrum) and the Cupl flow works well for this. -jg
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