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Paul, let's for a moment forget about routing. The 8-bit adder must fit into a single CLB (8 LUTs with carry) plus an extra LUT for the 9th bit. And the critical path has to be, as you say, from the LSB to the MSB, since the carry path ripples. If you get a different structure, change it! Coregen and other tools should help you, not prevent you, from getting max performance. Peter AlfkeArticle: 85451
I seem to remember Synplicity and Quartus allowing the user to select an Altera Stratix Hardcopy device as the target directly, as opposed to targeting an FPGA that is used for prototyping. Quartus 3.0 seems to support this, and I swear Synplicity did as well. However, I've gone back from Synplify 7.7 to 7.1, and I can't find any versions that support Stratix Hardcopy as a target. Am I crazy, or does anyone else remember this? Also, why did Altera remove support for this? Now, you have to use an FPGA prototype, and there doesn't seem to be a path to go directly to a structured ASIC. Thanks. JohnArticle: 85452
Using the coregen to generate an RPM gives a "vertical" structure with the slices one above the other using 2 CLBs. I can certainly try not using the RPM and arranging the slices so they are all in the same CLB. For an RPM coregen adder I get: latency 1: 3.974 ns for an 8 bit output 4.186 ns for a 9 bit output latency 2: 3.956 ns for a 9 bit output latency 3: PAR fails for an RPM complaining that IOBs aren't supported in RPMs - looked at .edn file and don't see any IOBs?!?! turning off RPM I get 4.311 ns latency 4: RPM works OK, but I get 4.044 ns. Worse than latency 2. Looking at critical path there are now 2 LUTs with MUXCY between them. CoreGen Adder/Subtractor v7 isn't as clever as I would have hoped; it does look like I can do better without it. Interesting stuff, I'll keep at it. As other people have pointed out, having 2 adders running at half speed is still an option. Peter Alfke wrote: > Paul, let's for a moment forget about routing. > The 8-bit adder must fit into a single CLB (8 LUTs with carry) plus an > extra LUT for the 9th bit. > And the critical path has to be, as you say, from the LSB to the MSB, > since the carry path ripples. > If you get a different structure, change it! > Coregen and other tools should help you, not prevent you, from getting > max performance. > Peter Alfke >Article: 85453
Hi Erik, > For the record I have nothing against Altera, but without Quartus running > "easily" in Linux, they're mostly out of the running otherwise. What's your problem with Quartus on Linux? Since 4.0 it's been running flawlessly (well, as flawless as its Windows counterpart) and quickly on RedHat, Gentoo, Suse, and even Knoppix (i.e. Debian) in this little computer room. Four completely different distributions. The only thing you may need to do is to comment out a line in the adm/qenv.csh file (around line 110), but only if you're not running Red Hat but _are_ running a 2.6 kernel with a glibc that has NPTL support compiled in. The only trouble I'm having is when somebody sends me a project to work on that was created on Windows and the filename does not exactly match the module name, but that's mainly an irritation. Also, the tools are TCL scriptable, generate Makefile-friendly .done files - so what's your problem? Best regards, BenArticle: 85454
"Paul Smith" <ptsmith@nospam.indiana.edu> schrieb im Newsbeitrag news:d8a8u2$o4h$1@rainier.uits.indiana.edu... > CoreGen Adder/Subtractor v7 isn't as clever as I would have hoped; it > does look like I can do better without it. I guess you have to look at reality. 4ns isn't awfull lot of time. Spartan-3 is fast, but not the fastest FPGA known to man. Even in the slower speed grade and highest temperature and lowest voltage. Do you REALLY need to push the limits that far? I would go for lets say 50C max and intentionally tune up the core voltage to the max. limit. This will probably give you enough margin to run the adder at 250 MHz. Looking at the output of the timing analyzer you can see that there is almost no more gain in additional pipeline stages. There is no logic shorter than 1 LUT level. And even splitting up the adder into two 4 bit adders doesn't help, since the carry chain propagation is the smallest part of the timing chain (just 120 ps for two bits, max into 3x120 ps for A_0 to C_8). Regards FalkArticle: 85455
Austin Lesea wrote: > What is vcolo.com doing with FPGAs? Looks like you re-sell computer > resources virtually? Nothing. I'm starting to experiment with FPGA stuff on my own, but I co-own vcolo.com and that's the address I use. <OT type="plug">FWIW for anyone who might be interested, we user User-Mode Linux to give customers everything from the kernel down totally dedicated and isolated, so you can run *any* [legal] software you want, unlike a classic "VPS" (e.g. Virtuozzo) or web hosting. Prices reflect the shared-resources nature, but performance tends not to show it.</OT> > If all you need are some samples, you should develop a better > relationship with your local X distributor or X representative. The problem is that I don't *have* a distributor or representative. I have Digikey, Mouser, Newark, etc. I'm screwing around with developing stuff with FPGAs because it's cool and I have some product ideas I want to see if I can make work. I need q.1 of a given part as appropriate for my prototyping (think home-etched boards, maybe a toaster-oven soldering kit if I can't pull off hand soldering of TQFP/SSOP stuff), using free tools like ISE. *IF* my idea becomes viable, whichever FPGA gets used in my prototype will likely be the one used in production. I have several ideas that AFAICT are *very* commercially viable, if I can build them. Being a software guy, I've got a lot of hardware stuff still to learn, but if I can't even get parts, I'm not gonna get anywhere in the first place. Someone else mentioned that Digikey seems to have some XC2S parts finally, which is good, but comments elsewhere indicated that the startup sequencing of the Spartan2's can be more of a pain to deal with than the 3-rail requirement of the Spartan3's... They're also much lower density, which may not be a problem in some of my design ideas but will be in others.Article: 85456
Ben Twijnstra wrote: > What's your problem with Quartus on Linux? Since 4.0 it's been running > flawlessly (well, as flawless as its Windows counterpart) and quickly on > RedHat, Gentoo, Suse, and even Knoppix (i.e. Debian) in this little > computer room. Four completely different distributions. > Also, the tools are TCL scriptable, generate Makefile-friendly .done files - > so what's your problem? I'm doing amateur hobbiest stuff, so there is no Linux version for me. I've heard around c.a.f that Webpack will be coming out for Linux "soon", but afaict it doesn't exist yet. Once that's available, I will definitely be setting it up and playing around with integrating its toolchain into my development processes. That would then make q.1 parts availability just about the *only* issue for my particular case in deciding between Xilinx and Altera... Eventually for larger projects, when I know a lot more about FPGAs, I might be able to make a distinction between the parts on their technical merits, but like I said, I'm very new to all this stuff and have no such clue yet.Article: 85457
Does anybody know if ISE tools (bitgen, par, map, etc.) could utilize dual-core CPU's to speed up their process? I am using a P4EE 3GHz on an SMP-enabled Linux system. The tools are reported to use only 50% of the CPU time.Article: 85458
"Antti Lukats" <antti@openchip.org> wrote in message news:d88m0o$be1$03$1@news.t-online.com... > > Q: as the DDR chips are mounted VERY close, all wires less than 0.5 inch? > and there is never more than one load on the DDR chips, I am wondering is it > safe to not have DDR termination resistors by using DCI in the FPGA and > switching the DDR into SSTL1 mode by the extended mode register write? > Antti, If the risetime is six times the flight time of the traces, you'll probably be safe without terminations. Risetime 1ns => 1 inch trace length in FR4. (25.4mm for metric Estonians! Actually, are Estonians metric?) Trace length must, of course, include the bond wires, bga traces, lead frames. Cheers, Syms.Article: 85459
Anybody have experience with the -g Persis:Yes option in bitgen? I tried using this option to be able to read back the configuration during run-time. However, bitgen reports error saying a couple of pins' IOBs are not to be used since they are persist. I looked up the ISE manual and it clearly states that persist option will only check the pins used for SelectMAP mode. I checked the pins that were reported, and none of them are SelectMAP pins. What is going on here?Article: 85460
ISE 7.1 defaults to 85 C and 1.14 volts; I thought the idea was that if a design meets timing under these limits you were safe under "normal" conditions. Hopefully I won't REALLY be pushing the limits that far.... Falk Brunner wrote: > grade and highest temperature and lowest voltage. Do you REALLY need to push > the limits that far? I would go for lets say 50C max and intentionally tune > up the core voltage to the max. limit. This will probably give you enough > margin to run the adder at 250 MHz.Article: 85461
Erik, OK, thanks for the explanation. Spartan 2 today is based on a very mature process, and the sequence is 'don't care', and the power on surge is within the specifications clearly outlined in the datasheet. The Spartan 2E is a much better choice, and is based on the "EA" shrink (hybrid .18/.15u process), and also has no 'sequence issues', and an even smaller power on requirement than Spartan 2. 'Sequence issues' for any Xilinx part all relate to their use: what happens when you plug them into a live bus, anbd what do you expect to happen while you power them ON, OFF, or do nothing. The support through the web technical answers detail all that stuff. Some parts are more hot plug friendly than others, and none sustain any damage to themselves as long as the absolute maximum voltages and currents are adhered to. Very few people in your situation are designing boards that are going to be hot-plugged, and even fewer care what happens when you do. For those who do care, we have a full range of documented proven solutions. Xilinx admittedly does not cater to the home hobbiest, as we don't see much revenue from that source. I am happy to see Xilinx FPGAs being used for software defined radios by amateur radio hobbiests (being that I have the call sign AB6VU, and I am also very interested and involved in SDR for our commercial customers). http://www.gnu.org/software/gnuradio/doc/exploring-gnuradio.html#intro I am sure that must be tough going, but most hobbiests realize that buying exiting development boards (like the Spartan 3 student Digilent pcb for $99) is a better choice than trying to etch your own pcb's in the sink. http://www.digilentinc.com/info/S3Board.cfm We do cater to Universities and Schools, as training generations of engineers (since 1985) to use our parts is a very viable business decision. Perhaps stepping on board with those suppliers (like the one mentioned above) is much easier. http://www.xilinx.com/univ/ AustinArticle: 85462
Hi all, We want to implement a JTAG programmer in an Altera Stratix device to program a chain of EPC16 devices. The Stratix device is commanded through a fibre interface connected to a PC (the ONLY possible connection to the PC). So far, as we understand we have two options, one is to use JAM/STAPL format and the other option is to use isc files (IEEE 1532). In either case, we could instantiate a NIOS to handle the JTAG programming. I wonder if we can get an expert's opinion on which option makes more sense perhaps depending on the quality of the JAM/isc files that Quartus generates and how long it takes to program the part. Is it true that the programming time is shorter when using isc files? What are the pros and cons of each option? Thanks, mArticle: 85463
Paul,
You are getting an extra level of logic, most likely because of the way
the synthesizer handles an add/subtract. I am assuming you coded it
something like;
if sub='1' then
q<= a-b;
else
q<= a+b;
end if;
Synthesis tools wind up giving you a mux that selects between an adder
and a subtractor instead of an adder with inverted inputs. The other
possibility is that you have a reset/preset value that is forcing that mux
if you code it like this, you'll get the desired construction:
b_fb <= not b when sub='1' else b;
b_cin <= 1 when sub='1' else 0;
process(clk)
begin
q<= a + b_fb + B_cin;
Basically, this construction gives the synth a really strong hint about
how it should be constructed for single level implementation. Without
it, the synths seem to be a little too brain dead to figure it out. You
may also find you need to put the addition as a concurrent process and
put a syn_keep on it, depending on the version of the synthesizer you
are using.
You'll also want to put adders on the A and B inputs and place those
registers immediately adjacent to the adder LUTs so as to minimize the
routing delays. In cases like this where you need a specific
construction and placement to attain the required performance, I find it
easier to just use macros with instantiated placed primitives. Then
again, I've already got those macros in my library. Basically, they
consist of a for-generate statement that instantiates and places the
LUT, flip-flop and carry chain logic for each bit of the adder. A
similar macro does the same for the input regsters, and then you can put
RLOCs on the instances of the macros to place them as a bigger macro.
250 MHz is attainable with the S3 parts, but you do have to be careful
about placement.
You shouldn't have to duplicate adders. If you do (Falk seemed to
misunderstand this by his comment), you also have to duplicate the
input registers and then use clock enables on both the input registers
and the adder/subtractors so that one set is enabled on the even clocks,
the other on the odd clocks (actually, you don't need the ce's on the
adder/subtractor, but it may make it easier to specify the multi-cycle
timing, and it will cut down slightly on power consumption). Each set
needs a multi-cycle constraint to allow two clock periods for the signal
to propagate from the input register thru the carry chain to the output
register.
Paul Smith wrote:
> Hi,
>
> I need to add a pair of 8 bit (unsigned) integers to get a 9 bit
> (unsigned) result at 250 MHz, preferably in an XC3S50-4.
>
> Using the Coregen adder/subtractor V7 with maximum pipelining (9) and
> RPM on, the best cycle time I can get is 4.55 ns. At each pipeline
> level the critical path is a LUT, a MUXCY, and another LUT.
>
> Can anyone point me at some hints for a faster implementation (besides
> going to a faster part?
>
> TIA
>
> Paul Smith
> Indiana University Physics
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85464
Davy wrote:
>Hi all,
>
>Is there any tools to convert Matlab M-language to HDL? Thanks!
>
>Best regards,
>Davy
>
>
>
Accelchip sells a tool that does it, but you'll need to tweak the code
some to get something that is reasonable in hardware. You'll get better
results by simply using Matlab as a simulation model and designing a
matching circuit in your favorite HDL.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85465
Relax guys, it is both a dessert topping AND a floor wax!
Sheesh, you guys are like my kids always needling each other trying to
get a reaction. Both of you have good parts!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85466Austin Lesea wrote: > Very few people in your situation are designing boards that are going to > be hot-plugged, and even fewer care what happens when you do. For those > who do care, we have a full range of documented proven solutions. The design I have in mind right now is hot-plugged, but only on the USB side. The FPGA will be glue between the USB chip, DRAM and flash. I'm hoping that the power-up requirements of an XC2S50E or -100E won't require any significant control circuitry. Eventually I hope to reduce the logic requirements to a lot fewer pins and gates, into CPLD realm, but for experimentation I want to have every pin of every device routed through the FPGA, even if half the logic is just crosspointing. > I am sure that must be tough going, but most hobbiests realize that > buying exiting development boards (like the Spartan 3 student Digilent > pcb for $99) is a better choice than trying to etch your own pcb's in > the sink. I have this board, and am going to try to do my initial development by building boards to plug into the 40pin connectors, but among other things that limits me afaict to an x8 DRAM instead of x16, due to lack of pins. A x16 JEDEC pinout for 256 or 512Mb has 16 data lines, 13 addr lines, BA0, BA1, RAS#, CAS#, WE#, CLK, CKE, DQML, and DQMH. Total of 39. I'm still figuring out how SDRAM works, but I'm only sure I can tie CKE, DQML, and DQML. That gets me to 36, but there are only 34 I/O's on connectors A2 and B1 of the Spartan3 board... Flash is easier, only 15 pins. USB I've already done hand-wired using the ELRAsoft EZ-USB FX2 board, and in a manner IMO far superior to the board Digilent sells to do the same thing (I actually connect all the pins... x16 data and control). Already done a basic test design all the way through to user-space software in Linux on that setup (host-controlled PWM of the 8 LEDs).Article: 85467
Hi Alex, I couldn't find your original email so I thought posting on CAStalk Here's my original message: > > Hi Alex, > > I'm Dimitri Turbiner. > Actually I'm extremely interested in working exactly > on the XUPv2p board and since I saw your post on > CAStalk that you have already a working instalation of > Linux I would like to ask you some questions: > > First let me describe you my project. > We have an old french robotical arm ( > http://microcontroleur.vije.net/Images/ERICC/ERICC.jpg > ). And I want it to play chess. It has some very old > 8085 based controling boards wich need to be replaced > by newer controllers. This will be easily done in the > FPGA fabric. Next, when the arm moves the chess pieces > around fairly good, I can hang a camera above so that > it will recognize the position of the pieces (My most > basic idea about that was simply sticking small pieces > of paper of specifical color each to each chess > figurine). Again I thought about Digilent video > digitizer board and some cheap analog camera. The next > step will be to put a RTOS on the board and be able to > remotely control the robot. The last thing will be to > make GNUchess run onboard so make the robot a fully > independent chess player. > > > 1) Was it possible to use the vga for console output > or you did everything through serial or ethernet? Were > you even able to run X in it? > > 2) My idea was to fully put linux on the 2 PPCs. I > read that because of some cache architecture > incompatibilities it is not possible to run a real > dual processor linux kernel. > So my idea was to simply run two parallel linux > systems. One would be fully dedicated running GNUchess > and the other one would do all the rest (web > interface, SSH, logs...) > To switch between the two systems (vga output and > keyboard would be shared) I would simply press a > button on the board or something like that. > So my question to you who already have experience > using the board is that would it be reasonably > feasible? > > 3) I don't know if you have experience using the > camera digitizer board form Digilent. If you do, would > it be very difficult to implement a simple shape (or > color) recognition system on the fpga fabric and > interface it with one of the linux systems? > > > If you have some advices to give me or something like > that I will be extremely appreciative. You should > understand me; what i need most right now is to talk > with experienced people who could give me advices. > > Thanks you very very much, > Dimitri > > __________________________________________________ > Do You Yahoo!? > Tired of spam? Yahoo! Mail has the best spam protection around > http://mail.yahoo.com > > >Article: 85468
The 7.1 does generate a correct UCF file and constraints. The problem seem related to the ISE tools, which synthesize ro translate to a larger design, with deeper level of logic. I also tried different level of effort. This helped, but still does not get as packed as ISE 6.3 tools. Maybe a newly implemented algorithm need some tweeking. Thanks for the answers, so I'm not the only one having those issues.Article: 85469
Hi Antti, What are the advantages of XP over PA3? I have to pick one of them for "system pld" in my board. I know XP has single power supply, initialized BRAM, very fast powerup load from internal flash. From the other hand PA3 has more flexible packaging, that allow to go down in price. Also I heard that PLL is better. Don't know about development software, seems to be kind of the same. > Antti Lukatswrote: "starfire" <starfire151@cableone.net> schrieb im Newsbeitrag > news:11afakg1pbsp9a6@corp.supernews.com... > Has anyone tried the Actel ProASIC3 Starter Kit? What is the cost of this > unit? > > From the documentation, the chip claims to be able to run from an external > 350MHz clock (and it appears the internal PLLs can generate a 350MHz clock > from an external source) but the system says it can only do about 150MHz > internal? Is this correct? > > Are there other companies making flash-based FPGAs? Is there a better > Starter Kit value available somewhere that anyone knows about? > > Thanks. > > Dave > > are you sure PA3 kit is already available !!?? to my knowledge all PA3 shipments are delayed unitl august september? I do have the PA+ kit but havent done much with it. check out Lattice XP series, they have many advantages over PA3 XP10 starterkits are available silicon also Antti[/quote:9f6ebfd223]Article: 85470
"dima2882" <vadimv@ieee.org> wrote in message news:ee8ec82.1@webx.sUN8CHnE... >I also noticed that the fitter for ISE 7.1 isn't as efficient. I had a >legacy design for an XC9500, and I called Xilinx tech support on an >unrelated issue. I was using 6.3, the tech support guy used 7.1, and he >couldn't fit my design to the chip. He had to install 6.3 to be able to >work on it. It really does seem that the new fitter isn't as efficient. Hit a good one with 6.2 and 6.3 when using schematics with xc9572xl making your own xor takes up less space than the builtin xor. Haven't tried it with 7.1 yet. AlexArticle: 85471
I have similar problems with the (official) ML40x reference design and the EDK 7.1Article: 85472
m_oylulan@hotmail.com wrote:
>I find this statement confusing. I thought that the advantage of the
>bit-parallel was that it has a much lower latency = number of
>iterations, while the bit-serial has a latency = word width * number of
>iterations. So why is the "latency in a parallel system as high or
>higher?"
>
>Thankyou,
>Mees
>
>
>
At a given clock frequency, it is true that the bit parallel will have
a lower latency (that should be obvious), however a totally bit serial
design can generally be clocked faster than an equivalent bit parallel
design. In certain pipelined bit serial designs, you can also begin the
next stage before the previous one is completed, hiding some of the
latency, so the overall latency is only a little longer than the bit
parallel latency. Unfortunately, CORDIC is not one of those because you
need the sign (last bit generated) of one stage before you start the
processing for the next stage. Nevertheless, at the time that paper was
written, a bit serial design in the then current FPGAs could be clocked
much faster than a bit parallel arithmetic design in the same part, so
while the number of clocks of latency was greater, the higher clock
frequency makes up for much of that latency in terms of absolute time.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85473Hi Peter, Peter Sorensen wrote: > I have been having problems with the EKD 7.1 and the ML40x reference design for quite some time now. ISE/EDK 7.1 cannot meet the timing constraints on that design. I would really appreciate if anyone would post a solution to this problem? On the MicroBlaze uClinux website I host a version of the ML401 reference design de-rated to 66MHz - this meets timing under ISE/EDK7.1. Apart from modified clock generation and timing constraints, the system is trivially modified to make it uClinux capable, but fundamentally it's the same as Xilinx's original design. You'll also need to grab the uClinux BSP support files, or simply revert the "OS" section in the MSS file to standalone. http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html Hope this is useful, JohnArticle: 85474
I am using it on Windows on an SMP machine and never more than one processor is executing the code at any given time. Sad but true. -- Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics "praetorian" <Hua.Zheng@jpl.nasa.gov> wrote in message news:d8abui$bfe$1@nntp1.jpl.nasa.gov... > Does anybody know if ISE tools (bitgen, par, map, etc.) could utilize > dual-core CPU's to speed up their process? I am using a P4EE 3GHz on an > SMP-enabled Linux system. The tools are reported to use only 50% of the > CPU time.
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