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What are the 5V or 5V tolerant options for non-volatile, reprogrammable, In System Programmable logic, capable of storing at least 400 bits ? Does anybody knows of another flash-based FPGA vendor besides Actel and Vantis/Lattice? Regards, M=E1rcio.Article: 87851
John Adair wrote: > Latest version supports up to XC3S1500. XC3S400 has been support since > 6.1-6.3 time. > Spartan 3E too? Thanks for input. Good day! -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarleRemoveThis@BOGUSsandia.gov NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 87852
asd, In the Spartan 3, or 3E, there is no ICAP interface to reprogram the DCM while in operation. In Virtex 4, there is not only the ICAP interface, but also the DRP (dynamic reconfiguration port) for the DCM which allows you to change settings. The DCM must be reset after the constants are changed, however. This can also be done by reconfiguration, but I am concerned that for Spartan 3, this also does not work well, as the parts will be interrupted completely while reprogramming, wheras the Virtex parts can be reprogrammed while still operating. Austin dalai lamah wrote: > I'm sorry if this is a trivial question, but I haven't found anything on > this topic in the Xilinx site: is it possible to implement a programmable > frequency synthesizer with Spartan3 DCMs? With "programmable" I mean > programmable at runtime (just like you can do with a programmable PLL > synthesizer), not just at design time. > > Thank you! > > -- > asdArticle: 87853
Hi, is anyone interested in beta-testing a small svfplayer (right now it works with DLC5 on 2.6 kernel) ? PiotrArticle: 87854
I mean I haven't seen him posting anything for awhile. Maybe he is now "Steven Kidnaped". :) I also want to know when the chips will be out, and how much will they cost. I have a project that will be in production by the year end. Luiz CarlosArticle: 87855
Hi Peter, > Here is the description of a Frequency Synthesizer that we recently > built 250 copies of. Very popular in our lab and with FAEs. We are > looking at the next generation going to a few GHz using MGT outputs. > Fun project... Does it have a Spartan or a Virtex inside? Best regards, BenArticle: 87856
Present generation: Spartan3 plus external PLL for higher freq. and less jitter.( <100 ps) Next generation: Virtex-4 FX (needs MGTs) PeterArticle: 87857
Hi Vish, If you are wanting to detect the location of the most significant bit then you may want to use a "propagate kill" circuit that maps very well to the FPGA carry chain (at least in Xilinx anyway). I won't attempt to describe it here, have a read of the following paper - page 6 in particular. www.ece.byu.edu/faculty/nelson/research/pubs/fpl2002.pdf google fpga propagate kill also returns this as top result. I think floating point arithmatic often needs to find the MSBit in the normalise process so maybe a google on FPGA floating point designs may find something. Out of interest, why are you trying to create an "asynchronous system"? Research topic? I believe synchronous design techniques are more appropriate if you are targetting an FPGA implementation.... backhus wrote: > Hi Vish, > In VHDL you can use the IF-ELSIF Statement. > > IF A = B THEN > --do something > ELSIF B = C THEN > -- do something else, but only if a=b didnt match before > ... > ELSE > -- do some default stuff if nothing else fits > END IF; > > Depending on the deepth of this structure your design will become quite > big and slow though. But the structure creates the priority dependance > and if your compares are kept simple (only = and /=) and need only a > small ammount of bits it may fit to your needs. > > have a nice synthesis > eilert > > llabakdas@gmail.com schrieb: > > +HI, > > Is it possible to create a comparator structure that has a priority > > structure eg My system has more than 65% cases where the winner is > > determined by the msb(matlab simulations).I am trying to create an > > asynchronous system, so early completion would be beneficial for my > > system. > > > > > > Essenatially i need a completion detection comparator. > > > > > > THanks > > Vish > >Article: 87858
On 2 Aug 2005 12:00:17 -0700, "Maaf" <mitrusc1980-newsgroup@yahoo.com.br> wrote: >What are the 5V or 5V tolerant options for non-volatile, >reprogrammable, In System Programmable logic, capable of storing at >least 400 bits ? > > >Regards, >Márcio. Look at the Xilinx XC9500 series CPLDs. 9500 is 5V, 9500XL is 3.3v - not sure if it's 5V tolerant. Also look at XIlinx Coolrunner devices. but what do you mean by 'store 400 bits'...? >Does anybody knows of another flash-based FPGA vendor besides Actel and >Vantis/Lattice? Altera, AtmelArticle: 87859
Austin, I appreciate all of the detail, but I guess my concern was more simple: 1. Will I damage my V4 devices if the I/O pins get driven when the core is unpowered? 2. Are there current paths from the I/O pins to the supply that could cause the device to get "powered" from driving the I/O with the core unpowered? Apologies for using the term "hot-swap" if it is not the correct one :) Thanks, JDArticle: 87860
Maaf wrote: > What are the 5V or 5V tolerant options for non-volatile, > reprogrammable, In System Programmable logic, capable of storing at > least 400 bits ? Of ROM or RAM ? > > Does anybody knows of another flash-based FPGA vendor besides Actel and > Vantis/Lattice? Altera have the MAX II, tho they 'forgot' to put RAM in that (unlike the lattice MachXO), so that will struggle on 400 bits, and also on the 5V aspect. Atmel have a dual-die version of the FpSLIC - loader in the same package, and that process is old enough to still be in the 5V realm. The uPSD from ST, have small CPLDs and easily meet 400 bits/5V/Flash items. Actel have some waffle on their comming Fusion devices, but it is presently mainly a waste of designer's time - lots of power-point froth, and no specifics. Might this have 5V pins - who can tell ? -jgArticle: 87861
Peter Alfke wrote: > Yes, it can be done, but it's far more flexible to use Direct Digital > Synthesis to generate arbitrary frequencies over a very wide range. > Here is the description of a Frequency Synthesizer that we recently > built 250 copies of. Very popular in our lab and with FAEs. We are > looking at the next generation going to a few GHz using MGT outputs. > Fun project... <snip> Sounds great - any photos ? Why stop at 1Hz ? What about sine output, at lower frequencies ? -jgArticle: 87862
Peter - Are you going to do an app note on this? Sounds like a neat project and a neat tool. John ProvidenzaArticle: 87863
Jim, I'll send you a photo. 1 Hz could easily be extended to 1 mHz or lower. Why? There are several BRAMs left over for sine-wave table-lookup. PWM output or separate D/A? Who wants it, for what?. It comes in a pretty and rugged Al-case, size of a cigarette pack (in case you remember...) PeterArticle: 87864
Hi I'm trying to put an IOB range contraint on an AREA_GROUP I did the following: AREA_GROUP "GRP0" RANGE = A2:A25; But the mapper refuses to recognize it. I looked up IOB AREA_GROUP constraint in the constraints guide. It doesn't provide details on actual syntax. Does anyone have experience using this contraint? Examples would be most welcome. ThanksArticle: 87865
Baxter wrote:
> I inherited some code for the Actel fpga.
> I need two things:
> 1 - to be able to read the code/project and determine what it does
> 2 - to be able to revise/maintain the code.
>
> I would like recommendations as to what toolchain to port this code to.
> Money is an issue - ROI is quite low.
If the code is a netlist and you don't know
what it does, I see little value in maintaining it.
If it is generic RTL code with a testbench,
you can make modifications and test them, and
port to any fpga you like.
-- Mike Treseler
Article: 87866I have found that when reset behaves differently in simulation than in PAR it usually points to the global reset path been gated. Generally you should treat reset signals with almost the same care you treat Clk signals (most importantly by not gating them). Try also passing the reset signal through an BUF or even edge detecting it to ensure that it is stable. (remember that most reset signals come from outside pins and can have wild fluctuations before settling). Generally, behavioral simulations assume ideal signals. Hope this helps. RobinArticle: 87867
I'm new to this kind of programming - I don't know what "netlist" or "RTL" are. I have a general idea what the code does, I need to find out the nitty-gritty details. As it stands now, I have a binary file I can use to burn chips, but no ability to maintain or extend the code. I'd like to port the design to a slightly different platform -- I'd still be using the same chip, but likely the chip software would have to change slightly. It's got lots of different files, including some .vhd. I was hoping to find someone with lots of Actel experience. -- --------------------------------------------------------------------- DataGet & PocketLog www.dataget.com Data Collectors www.baxcode.com -------------------------------------------------------------------- "Mike Treseler" <mtreseler@gmail.com> wrote in message news:BPSdnb1oosj_g23fRVn-vA@comcast.com... > Baxter wrote: > > I inherited some code for the Actel fpga. > > I need two things: > > 1 - to be able to read the code/project and determine what it does > > 2 - to be able to revise/maintain the code. > > > > I would like recommendations as to what toolchain to port this code to. > > Money is an issue - ROI is quite low. > > If the code is a netlist and you don't know > what it does, I see little value in maintaining it. > > If it is generic RTL code with a testbench, > you can make modifications and test them, and > port to any fpga you like. > > -- Mike Treseler >Article: 87868
Peter Alfke wrote: > Jim, > I'll send you a photo. > 1 Hz could easily be extended to 1 mHz or lower. Why? Because it's a generator, and one never knows when a slow stimulus is needed :) [The real world does not stop at 1Hz] > There are several BRAMs left over for sine-wave table-lookup. > PWM output or separate D/A? Or sigma-delta DAC ? > Who wants it, for what?. It would need to be 'all in the FPGA' as that's part of the appeal. Maybe an external SPCO analog SW [~SOT23], for low noise Ref and low noise floor. Audio generation is an obvious area, and with effort, it should be possible to get very low distortions, or > 90DB SFDR. -jgArticle: 87869
thanks Vladislav.. it worked perfectly... can i substitute this process for the real fpga.... what is the effect of routing delays compared to the component delays.... how can i account for that in the simulation environment... SumeshArticle: 87870
"Baxter" <lbax02.spamguard@baxcode.com> schrieb im Newsbeitrag news:11f0f3eom8odk97@corp.supernews.com... > I'm new to this kind of programming - I don't know what "netlist" or "RTL" > are. > > I have a general idea what the code does, I need to find out the > nitty-gritty details. As it stands now, I have a binary file I can use to > burn chips, but no ability to maintain or extend the code. I'd like to port > the design to a slightly different platform -- I'd still be using the same > chip, but likely the chip software would have to change slightly. > > It's got lots of different files, including some .vhd. I was hoping to find > someone with lots of Actel experience. > > -- > --------------------------------------------------------------------- > DataGet & PocketLog www.dataget.com > Data Collectors www.baxcode.com > -------------------------------------------------------------------- > well the .VHD are source files, if all the project is on .VHD files then you have no problems. if part of the design is not, eg is in compiled files or in schematic files not readable by available tools then you have more problems. AnttiArticle: 87871
<oen_no_spam@yahoo.com.br> schrieb im Newsbeitrag news:1123016187.105190.239180@o13g2000cwo.googlegroups.com... > I mean I haven't seen him posting anything for awhile. > Maybe he is now "Steven Kidnaped". :) > > I also want to know when the chips will be out, and how much will they > cost. > I have a project that will be in production by the year end. > > Luiz Carlos > Yes Steven Knapp seems to be on vaccation or kidnapped he has not also been replying to personal emails. The pricing is (or will be) a little below S3 pricing, but that depends on the chip density and package type combination. In some cases S3 may be cheaper. But OTOH there is NO price roadmap for S3 at all, for any queries about S3 prices Xilinx suggests using S3E ! For 'production' by the end of the year, you should place full volume orders NOW. Do not delay. I think depending the size-package combination you may be able to use S3E already /(by the very end of the year), but you need to get FULL confirmation of the delivery from Xilinx before decision. AnttiArticle: 87872
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dcn3ss$qou$04$1@news.t-online.com... > <do_not_reply_to_this_addr@yahoo.com> schrieb im Newsbeitrag > news:1122935399.899122.35350@o13g2000cwo.googlegroups.com... > > Humm... Why wouldn't Xilinx support this cable (I thought Digilent and > > Xilinx have a close relationship) and if not Why wouldn't Xilinx > > publish the protocols used by Chipscope server. Are they trying to make > > money by selling their own expensive USB cable ? > > > > Sumit > > > > The Xilinx - Digilent co-oper is not so close. > > Xilinx is NOT publishing the ChipScope server protocol and > Xilinx is NOT publishing the Impact server protocol > > because they may change those with every service pack and the do not want > additional hassle from 3rd parties. Maybe some other issues as well. > > Yes, it looks like Xilinx is trying to make money on the over priced USB > Cable, that doesnt work very good. The PCs with LPT port are coming to be > 'hard to get' items, so the only official cable is Xilinx USB cable, what is > very EXPENSIVE, it only contains Cypress 68013 and Coolrunner, but cost > 495$. > > Antti > > UUPS! I made a mistake - the USB cable is $149 not 495, so its not so bad deal at all. (some other FPGA vendor sells USB cable for 400+ USD so I messed up) sorry. Antti PS we are using the Xilinx USB cables all the time now.Article: 87873
HI, based on your other answer I understand you have a .adb file. This is the actel database which should be useable in the newer versions of actel designer software (When having a very old version you might lost your pinout). I hope you didn't mean a .afm file which is only the programming file for the Fpga and will be (nearly [1]) complete useless. The designer software is available as silver edition for free. This edition is OK for smaller devices. The database contains the netlist which can be exported. But without having any knowledge of rtl and netlist you out yourself as someone who should not even think to modify the netlist to get the desired results. Start searching .vhd or .v files containing the rtl code (register transfer level). The IMHO better way for you would be starting to learn how to design digital cirquits and rebuild the design from scratch. bye Thomas [1] Buying a good support from Actel could help getting some logic out of the bitstream. Actel might have the possibility to get a netlist out of this bitsream.Article: 87874
Hi,
I work on a project involving an optical link. The transceiver is a
finisar one with a CML interface and AC coupled serial links with
internal 100 ohm differential impedance termination for the receiver of
the optical transceiver. I use one RocketIO in an XC2VP7FF672-6I with a
BREFCLK running at 125 MHZ for a 2.5 Gbit/s serial link. I use the
internal terminations provided with the rocketIO with a 50 ohm value
(see below).
VTTX is 2.5V filtered.
VTTX
|
R1
|\ | |\
| \------------------------------C----|----| \
-----| > R2 | >
| /o-----------------------------C----|----| /
|/ | |/
R1
|
|
VTTX
R1 is 50 ohms in the Rocketio and R2 is 100 ohms in the transceiver.
All discrete parts are inside either the FPGA or the transceiver. This
is the design I have implemented and the swing seems to be correct out
of the Rocketio (500 mV single ended swing => 1000mv differential
swing). I have a DC level of about 1.8V.
The question is am I doing anything wrong in this implementation ? The
reason for this is that the optical transceiver does not seem to drive
the correct power ie the extinction ratio is very poor (close to 4)
with the low level being around 300uW which is high. If anybody has an
idea or can tell me what I did wrong I would be very thankfull.
Best regards,
JF
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