Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
jpvarkey@gmail.com wrote: > Iam currently working on carbus project.I am really concerned with > power delay factor in FPGA's especially Xilinx FPGA's .Will that create > a problem for cardbus.Could somebody explain on, what all factors will > affect the power up delay in SRAM based FPGA's. The amount of bytes to be transferred from the flash and their datarate. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 103276
> The amount of bytes to be transferred from the > flash and their datarate. > As well as - The delay prior to starting up the FPGA download. - The delay after all of the data has been downloaded to the FPGA while you're waiting for the FPGA to switch into a 'user' mode (typically though this is pretty small). KJArticle: 103277
Hi,
I've written the code for an application using Xilinx 7.1 . Can
I create an IP core out of it?
Thanks and Regards,
Srikanth
Article: 103278
Hi,
I've written the code for an application using Xilinx 7.1 . Is
it possible to I create an IP core out of it?
Thanks and Regards,
Srikanth
Article: 103279Three options 1) Download something from PLX or simillar. That will document what they have done which is a good start. 2) Download PCISCOPE which is a software tool for looking at PCI devices, the documentation may suffice. 3) Get hold of the spec (illegal) or a textbook. colin jpvarkey@gmail.com wrote: > Could somebody give me the format of type 1 and type 2 configuration > headers.Article: 103280
Try writing some very simple code (a few lines of VHDL) that just drives an output high or low, and see if that works. LeonArticle: 103281
Dear Antti, I am new with EDK environment and want to interface with SDRAM, but when i add device SDRAM into my project my tool Xilinx EDK 7.1 doesn't include driver for SDRAM and also not including any API file for that, so please suggest some remedy for the same if possibleArticle: 103282
bjzhangwn schrieb: > I am writing a interface about the ata interface but I have a problem > that the dma request signal is sometimes always high when power up,and > the hardware reset didn't work. check your power-up sequence ... the drive should go to a ready-state after delay and status-polling. The procedure from the sepc just works fine for me and I never had an issue with *that* ... bye, MichaelArticle: 103283
well what you have done already is an IP core, so what is what you actually want todo? a <= b or c; the above as example is an IP core, in the matter of fact I have sold such a IP core ! AnttiArticle: 103284
there is no driver needed just access the memory with volatile pointer thats it anttiArticle: 103285
It sounds to me like you're not getting a good ground return to your scope. If the board is powered by a "wall wart" supply it is most likely isolated from third-wire ground. If you have a ground clip attached to the board, check to see that you're not also seeing the 50 Hz when you probe the ground clip. This could indicate a bad connection to the probe ground return. Good Luck, Gabor m_oylulan@hotmail.com wrote: > Hello, > > I am trying to program an RC-100 demo board, which contains a > Spartan-II chip. The board is supposed to send three logic outputs to > external devices through I/O pins provided on an expansion header. I am > pretty sure I've coded the program correctly (only to the extent that > it works as intended in simulation), but when I probe the I/O pins with > a scope all I'm getting is what I assume is mains pick-up (50 Hz > ~5Vpk-pk). > > My probes have been calibrated; the probe and scope have adequate > bandwidth (greater than 5x the signal bandwidth), and I get the same > result whether I use the 'Auto-scale' function or manually set the > 'Volts' and 'Time' division scales to the capture the expected > waveforms. In the event that the source of the problem isn't my code, > does anyone have any suggestions as to what I might be doing wrong? > > Thanks, > meesArticle: 103286
As someone who regularly writes code for existing boards, I find it annoying that ISE doesn't make it easier to find non-LOC'd I/O pins. I usually look first at the place&route report and check the "number of LOCed IOBs" line to make sure it's 100%. However there is no translate option to report an error for non-LOCed I/O's. Also it's painful to browse through the pad report, which shows the the status (LOCATED or not) of each IOB in a far right column that is generally off-screen without scrolling. Conversely I regularly need to set the (advanced) uption "Allow unmatched LOC constraints" so I don't need to create a new ucf file for each design on the same board. I'd really rather the unmatched LOC's be allowed (possibly with a warning) as a default, and un-LOCed IOB's to be (optionally) flagged as an error. For anyone designing code for existing hardware, these defaults make more sense. Note that this includes anyone using the Starter Kits, read inexperienced designers. Just my 2 cents, Gabor Aurelian Lazarut wrote: > you can create a script to check the pad report (from par) to make sure > pin locations and IO standards are correct for your particular demo design > Aurash > > GaLaKtIkUs=99 wrote: > > Hi all, Is there a method for personalization of ISE? > > One of the personalizations: > > - For avoiding students to make errors in IOB proprties in UCF > > files (the student's projects are for S3-Starter kit): is it possible > > to add some step in the translate phase? I saw a perl interpreter > > installed with ISE. > >=20 > > Cheers > >Article: 103287
Hi Gabor, why a non-locked pin should be considered an error? if you want to constrain a pin to a location, the tools will (usually) obey, if you do not care by not adding a location constraint why the tools should care, or maybe you want a mechanism which will guess that you actually forgot an entry into your ucf. Aurash Gabor wrote: > As someone who regularly writes code for existing boards, I find it > annoying that ISE doesn't make it easier to find non-LOC'd I/O > pins. I usually look first at the place&route report and check the > "number of LOCed IOBs" line to make sure it's 100%. However there > is no translate option to report an error for non-LOCed I/O's. Also > it's painful to browse through the pad report, which shows > the the status (LOCATED or not) of each IOB in a far right column > that is generally off-screen without scrolling. > > Conversely I regularly need to set the (advanced) uption "Allow > unmatched LOC constraints" so I don't need to create a new > ucf file for each design on the same board. I'd really rather > the unmatched LOC's be allowed (possibly with a warning) as > a default, and un-LOCed IOB's to be (optionally) flagged as an > error. For anyone designing code for existing hardware, these > defaults make more sense. Note that this includes anyone > using the Starter Kits, read inexperienced designers. > > Just my 2 cents, > Gabor > > Aurelian Lazarut wrote: > >>you can create a script to check the pad report (from par) to make sure >>pin locations and IO standards are correct for your particular demo design >>Aurash >> >>GaLaKtIkUs™ wrote: >> >>>Hi all, Is there a method for personalization of ISE? >>>One of the personalizations: >>> - For avoiding students to make errors in IOB proprties in UCF >>>files (the student's projects are for S3-Starter kit): is it possible >>>to add some step in the translate phase? I saw a perl interpreter >>>installed with ISE. >>> >>>Cheers >> >>> > > >Article: 103288
Antti wrote: > well what you have done already is an IP core, > so what is what you actually want todo? > > a <= b or c; > > the above as example is an IP core, in the matter of fact I have sold > such a IP core ! > > Antti Take for example, FIFO or that sort of IP core from coregen. I want to generate a similar stuff which packs instanciation template and synthesize output file. Thanks and Regards, SrikanthArticle: 103289
Aurelian Lazarut (aurash@xilinx.com) wrote: : Hi Gabor, : why a non-locked pin should be considered an error? : if you want to constrain a pin to a location, the tools will (usually) : obey, if you do not care by not adding a location constraint why the : tools should care, or maybe you want a mechanism which will guess that : you actually forgot an entry into your ucf. What'd be really nice would be for the tools to let the user specify the severity of a condition on a per project basis. So for example a non LOCed IO could be flagged as 'no action', 'warning' or 'error' Given how many spurious warnings are often kicked out by the tools, it'd be really usefull to have this as an integrated feature. cdsArticle: 103290
Hello I just finished the test with the UC-II gigabit ethernet design for the ML403 board. Unfortunately, the design is very slow for high speed transmission. The main problem is the little quantity of memory for the code of the TCP/IP stack, so you need to optimize in space, and the instruction speed is decreased. But for slow applications this is a great solution, because it's simply and easy to learn. The next step? Hardware processing... RegardsArticle: 103291
Well actually you can buy a single chip 4 Mbit RAM that will fit the DIL headers. There are solder bridges to facilitate that chip and others and there is one in Farnell last time I looked. A RAM module is also on it's way to if that is not enough. If you want more boot space then we can also accomodate a disk drive or MMC card with module add-on. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board. http://www.enterpoint.co.uk "Antti" <Antti.Lukats@xilant.com> wrote in message news:1148908918.240508.253910@j55g2000cwa.googlegroups.com... > John, > > your boards are EXCELLENT for the money they cost but this time the OP > asked for 'uclinux' ready boards. > > the requirement for uclinux is > > 1) xilinx FPGA S2-200 or larger, S3-1000 or larger preferred > 2) 4MB RAM > 3) some way to load boot image 2MB flash or some media load the image > from > > Raggestone1 does not have a option with 4MB ram ASFAIK so its not an > option for the OP > > Antti >Article: 103292
John, the requirement is 4 MBYTE RAM not 4 mbit !! there is no dil socketed 3.3V 4MBYTE ram modules available ASFAIK AnttiArticle: 103293
I have some very old jedecs for a 22v10 that I would like to back compile into abel logic equation files. Any ideas ? ThanksArticle: 103294
> Google for pci local bus specification revision 2.2 google "pci23.pdf" it looks like it's the sixth link downArticle: 103295
For those that have asked about our Overcoat option to generate FPGA arrays there is now a page on our site at http://www.enterpoint.co.uk/moelbryn/overcoat.html showing the mechanics of how we do it. The array shown can operate either in a motherboard as shown or stand alone on the bench. Currently this a build to order option but we are looking at keeping some stock if there appears to be some demand. John Adair Enterpoint Ltd. - Home of Overcoat. FPGA Array Processing. http://www.enterpoint.co.ukArticle: 103296
OK. But If I did manage to get hold of external clock recovery circuit, can the PCI SIG compliance board be used to add PCIe functionality to the FPGA development board (Xilinx PCIe Logicore will be used on the board) Are there any other cheaper alternatives like generic PCIe daughter cards, or other add in cards that can be used to connect the development board and a PC through PCIe? Thanks, Eshwar "Antti" <Antti.Lukats@xilant.com> wrote in message news:1148584182.115716.17030@j33g2000cwa.googlegroups.com... > V2pro rocket io is not PCIe compliant on the 'lock range' of the CDR so > at least you need an external clock recovery circuit to be added - in > short the answer is no, if you want PCIe functionality with Xilinx FPGA > you should seek some other platform - as V2Pro is 2 families past the > latest and greatest I dont think there will be any new things developed > for it or for ML321 platform. > > Antti >Article: 103297
Un bel giorno Falk Brunner digitò: > In the real system, such > things are often not usefull, since the FPGA interacts in realtime with > external components (RAM, busses, whatever). Since FPGA are static devices, it shouldn't be so hard to support breakpoints by temporarily "disconnecting" the clocks, and watch/change the "variables" through JTAG; if you can do partial reconfiguration, I suppose you can also read/change the BRAM, registers and so on. Of course there are asynchronous signals too, but even with normal software debug there are asynchronous events you can't control. -- asdArticle: 103298
Hi All, I have the following issues while trying to test a sample Aurora core. I generated a core w/ the following specs: HDL: Verilog, Lane: 1, Lane Width: 2, Interface: Streaming, Upper MGT Clock: BREF_CLK, Upper MGT clock on GT_X0Y1 (from ucf file, corresponds to MGT4 for a ML321 board) After using xilperl to compile the design files, I simulated it using Modelsim, and uploaded the bit file using Impact to the board. I'm trying to test the core by feeding a 3.125Gbps (default data rate based on onboard oscillator) PRBS signal onto MGT4(RXP & RXN). I test the output signal from MGT4(TXP & TXN) by connecting it(TX ports)to a oscilloscope and/or spectrum analyzer. Ideally, you would expect the protocol to simply transmit that data that it received at the RX ports, but the protocol fails to do that. I get an extremely weak signal on the spectrum analyzer and bad eye on the scope. I also tried feeding in a clock signal of 50MHz into BREF_CLK and testing the setup w/ 1Gbps PRBS signal, but that didnt work either. Can you tell me where I might be going wrong? Thanks, BilluArticle: 103299
dalai lamah schrieb: >>In the real system, such >>things are often not usefull, since the FPGA interacts in realtime with >>external components (RAM, busses, whatever). > > > Since FPGA are static devices, it shouldn't be so hard to support > breakpoints by temporarily "disconnecting" the clocks, and watch/change the The problem is not the FPGA but the external components. Those are often not static, so this is no option. > "variables" through JTAG; if you can do partial reconfiguration, I suppose > you can also read/change the BRAM, registers and so on. Of course there are > asynchronous signals too, but even with normal software debug there are > asynchronous events you can't control. The key word is real-time monitoring. Regards Falk
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z