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On Feb 8, 12:46 pm, "prakash" <prakash.akkas...@gmail.com> wrote: > hi > i am implementing DCT and IDCT on FPGA can any body give me some > specific Block diagram you can send me the details on the mail id > prakash.akkas...@gmail.com Try these: http://direct.xilinx.com/bvdocs/appnotes/xapp610.pdf http://direct.xilinx.com/bvdocs/appnotes/xapp611.pdfArticle: 115426
Does any one have the VHDL code to transfer ZBT SRAM data to and from the Flash Memory? Seems like it should be a matter of wiggling the control lines since the two memories share the same data and address lines. Also, I noticed Micron now says the Flash memories are obsolete. Is there an easy migration to newer chips? Brad Smallridge AiVisionArticle: 115427
Hi, I looked through the Xilkernel documentation and Xilinx mentions a few times about enabling and disabling interrupts and context switching. I need to be able to do this but can't seem to find anywhere how to do this. Anyone know how? I don't want to just enable and disable a single interrupt. I want to disable other threads from executing for a very short duration and turn off all interrupts. I am using a Power PC on the Virtex 4 FX12 MM. Thanks, -EdArticle: 115428
Hello
I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for
OR gate using JHDL, with a1 and a2 being inputs, and op being the
output.
I also created the following User constraint file: (not sure if the
given constraints are right!)
NET "a1" LOC="AC4";
NET "a2" LOC="AC3";
NET "op" LOC="AA6";
Using Xilinx ISE, i gave the command: (i'm particular abt not using
the GUI, as i need to call the cmds programmatically)
ngdbuild -p xc2vp30-ff896 -uc or_gate.ucf
or_gate.edn
Here i get the following warning:
WARNING:NgdBuild:483 - Attribute "LOC" on "op" is on the wrong type of
object.
Please see the Constraints Guide for more information on this
attribute.
WARNING:NgdBuild:483 - Attribute "LOC" on "a2" is on the wrong type of
object.
Please see the Constraints Guide for more information on this
attribute.
WARNING:NgdBuild:483 - Attribute "LOC" on "a1" is on the wrong type of
object.
Please see the Constraints Guide for more information on this
attribute.
And subsequently, when i tried to map using the command
map or_gate.ngd ( the ngd file created in the
above ngdbuild step) i get the following error.
ERROR:Pack:198 - NCD was not produced. All logic was removed from
design. This
is usually due to having no input or output PAD connections in the
design and
no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE'
attributes to the design, or run 'map -u' to disable logic trimming
in the
mapper.
Please guide me as to how i can correct these errors. Is there some
specific tutorials available for writing user constraint files and to
readback the logic from FPGA and find if they are correct, by some
means?
Thanks
Quad
P.S: I'm pasting the edif file (or_gate.edn) generated by JHDL for
your reference
(edif evolution2_ckt
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2007 2 10 10 28 36)
(program "BYU-CC's JHDL-EDIF netlister by Peter Bellows and Eric
Blake"
(version "0.3.45"))))
(library evolution2_ckt
(edifLevel 0)
(technology (numberDefinition (scale 1 (E 1 -12) (unit
CAPACITANCE))))
(cell (rename or2 "or2")
(cellType GENERIC)
(view view_1
(viewType NETLIST)
(interface
(port i0 (direction INPUT))
(port i1 (direction INPUT))
(port o (direction OUTPUT))
)
))
(cell (rename orX_2 "orX_2")
(cellType GENERIC)
(view view_1
(viewType NETLIST)
(interface
(port (array (rename i "i[1:0]") 2) (direction INPUT))
(port o (direction OUTPUT))
)
(contents
(instance or2
(viewRef view_1 (cellRef or2)))
(net (rename i__0__ "i<0>")
(joined
(portRef i0 (instanceRef or2))
(portRef (member i 0))))
(net (rename i__1__ "i<1>")
(joined
(portRef i1 (instanceRef or2))
(portRef (member i 1))))
(net (rename o "o")
(joined
(portRef o (instanceRef or2))
(portRef o)))
)
))
(cell (rename orX_g_1 "orX_g_1")
(cellType GENERIC)
(view view_1
(viewType NETLIST)
(interface
(port in1 (direction INPUT))
(port in0 (direction INPUT))
(port out (direction OUTPUT))
)
(contents
(instance orX
(viewRef view_1 (cellRef orX_2)))
(net (rename in1 "in1")
(joined
(portRef (member i 0) (instanceRef orX))
(portRef in1)))
(net (rename in0 "in0")
(joined
(portRef (member i 1) (instanceRef orX))
(portRef in0)))
(net (rename out "out")
(joined
(portRef o (instanceRef orX))
(portRef out)))
)
))
(cell (rename evolution2_ckt "evolution2_ckt")
(cellType GENERIC)
(view view_1
(viewType NETLIST)
(interface
(port a1 (direction INPUT))
(port a2 (direction INPUT))
(port op (direction OUTPUT))
)
(contents
(instance orX_g
(viewRef view_1 (cellRef orX_g_1)))
(net (rename op "op")
(joined
(portRef out (instanceRef orX_g))
(portRef op)))
(net (rename a2 "a2")
(joined
(portRef in1 (instanceRef orX_g))
(portRef a2)))
(net (rename a1 "a1")
(joined
(portRef in0 (instanceRef orX_g))
(portRef a1)))
)
))
)
(design ROOT
(cellRef evolution2_ckt
(libraryRef evolution2_ckt)))
)
Article: 115429Hi all, I am having some difficulties working with the DMA of the ethernet mac. I've downloaded a ref. design of web-server over the virtex-2P (with ppc 405) - it works well. However I would like to add a DMA -> which means that every packet that is recieved will be directly written to the DIMM that is on board (xupv2p E.B.). I tried to read the docs explaining the proceadure, BUT GOT LOST. help someone?? thanks, GuyArticle: 115430
On 8 Feb., 18:17, "s...@catalpatechnology.com" <s...@catalpatechnology.com> wrote: > I've read some of the heated discussions regarding Virtex 4 and SATA, > but I'm still not sure what the answers are. My understanding is that > with a modest amount of external circuitry (NOT an external phy) I can > build a SATA interface. Some of the Xilinx answer database links > regarding SATA are dead. Hopefully someone here can give me some > pointers. > > 1) What about V4 fails to work for SATA? > 2) Has anyone made it work, and willing to explain how it was done? > 3) Can 3Gbps speeds be used? > 4) Is there another programable device that would be easier (V5 still > needs to age a bit). > > Thanks > > Sam Hi Sam, unfortunatly V-5 is the only Xilinx device that is claimed to be SATA compliant. V-4 has several issues, some have workarounds some not. the OOB signalling has workaround, the CDR lock range limitation has not. But why are you so sceptic about the V-5 use? I have ML505 on my desk and it has SATA connectors on it. besides V-5 Lattice has promised to verify if the SC/ECP2M is fully SATA compliant it maybe but it is not officially confirmed by Lattice. Antti PS please feel to contact me in private, i have and SATA project underway.Article: 115431
just thought that I would post the solution for all those who might run into the problem in the future. when doing simulation use: "vsim -lib work -unisim_ver <other options> <test bench module>" to make it search for other compiled libraries other than default (work)... eg when it says "Referenced (but uncompiled) modules or primitives:" hope this made someone's life easier.. =)Article: 115432
Thanks for the update on your situation and also for the links to the Answer Records and IBM's PDF. Hopefully, others will fare better than we did. NjuArticle: 115433
Hopefully this won't have to be a lesson in Tcl. Here is my problem. I
am using ModelSim
with Xilinx ISE. I will make a simulation and arrange the signals in
the order I would like them.
If you hit "File" and then "Save" a box pops up asking "Save waveform
formats?" and then it lists
the path to the do file. I click OK and expect the waveform formats to
be saved, and they are not.
The reason they are not is that every time you re-run the simulation
by clicking "Simulate Behavioral
Model" an automatic do file is used and the waveforms revert to the
default order. If you highlight
"Simulate Behavioral Model" and hit "properties" there is an option to
use a custom do file. If I try
that I get to the "VSIM" prompt, but no luck after that. I assume the
"automatic" option does a
bunch of stuff for you. I'm guessing there is a command or set of
commands that will allow
you to run your simulations without making the waveform go back to the
default order.
Can someone help me with this? BTW, what if you wanted to have
multiple do files?
Would the solution be the same?
Thanks
Article: 115434David, Not have a setting is real bad. Last I looked Xilinx's recommended coding styles for coding multiple edge FIFOs uses VHDL-93 shared variables. In VHDL-2002 (the current IEEE revision) shared variables require protected types. Hence Xlinx's coding methodology is illegal in the current standard. Without a switch, what is going to happen to that code that functions just fine, but is illegal? BTW there are 1076.6-2004 recommended coding styles for this structure (a single process with 2 clock edges). I haven't checked recently, does Xilinx support them. Cheers, Jim > Wojtek, > > The XST Users Guide gives specific details on which VHDL standard XST > supports (and those that are conflicts). See the UG located here: > http://toolbox.xilinx.com/docsan/xilinx9/books/docs/xst/xst.pdf > > I do not believe that there is a way to specify the exact standard that you > may want to use. Verilog 2001 appears to be the only HDL standard that is > selectable within the synthesis options. > > -David > > > "wojt" <wojtek.bocer@gmail.com> wrote in message > news:1171033608.993210.85410@a75g2000cwd.googlegroups.com... >> Hi >> >> Does anyone here know, how to explicitly set which VHDL standard >> should be used by Xilinx ISE (actually, by XST I think)? >> >> Cheers >> Wojtek >> > >Article: 115435
pete o. wrote: > I'm guessing there is a command or set of > commands that will allow > you to run your simulations without making the waveform go back to the > default order. try "add wave" from the modelsim prompt. http://groups.google.com/groups/search?q=vhdl+vsim+add+wave http://groups.google.com/groups/search?q=vsim+vcom+vmapArticle: 115436
On Feb 8, 4:40 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > "EEngineer" <mari...@gmail.com> writes: > > I am interested in image processing of 128x128 image using wavelet > > transform compression, 12 bits per pixel, monochrome. > > At what sort of frame rate? > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html Frame rate expected is 30fps. Thanks, DanArticle: 115437
Hi all, I'm having some trouble when trying to work with chipscope and mdm. It goes like this - I have a microblaze design (as sub module) that contains mdm. In the ISE (not inside EDK) I added a chipscope ILA core. When trying to map the design the mapper "screamed" about me trying to use 2 Bscans (where there is only one available). I knows that if using chipscope in EDK flow we can tell the EDK that the system contains MDM and it does the job. What can I do when working in ISE ? any help will be appreciated P.S. - my device is V2P30 Thanks, Mordehay.Article: 115438
On Feb 11, 5:14 am, Mike Treseler <mike_trese...@comcast.net> wrote: > pete o. wrote: > > I'm guessing there is a command or set of > > commands that will allow > > you to run your simulations without making the waveform go back to the > > default order. > > try "add wave" from the modelsim prompt. > > http://groups.google.com/groups/search?q=vhdl+vsim+add+wavehttp://groups.google.com/groups/search?q=vsim+vcom+vmap I would more likely recommend that you tried "run file.do" from modelsim. It will launch your file.do file.Article: 115439
hi, i need a whole matrix to be substracted form another in one clock cycle. and i need to store all the values of these matrices in either distributed or block RAM. i thought this is not possible with block RAM, as these have didicated ports that are fixed in width. so tried to use distributed RAM with the following verilog code. parameter nColumns = 100; parameter nRows = 200; parameter RAM_WIDTH = 8; //matrix 1 data reg [RAM_WIDTH-1:0] data_1[nColumns*nRows-1:0]; //matrix 2 data reg [RAM_WIDTH-1:0] data_2[nColumns*nRows-1:0]; reg [7:0] ix = 0; reg [7:0] iy = 0; reg[10:0] diff = 0; always @ (start) // start will trigger the calculation begin for(ix = 0; ix < 100; ix = ix + 1) begin for(iy = 0; iy < 100; iy = iy + 1) begin diff = diff +data_1[iy] - data_2[ix]; end end end ise webpack completed stege one systhesis of this code after around 10 minutes and did not complete the whole systhesis even after around 3 hrs. any assistance is very much appreciated. thank you.Article: 115440
On 10 Feb 2007 15:16:29 -0800, "pete o." <portisi@comcast.net> wrote: >Hopefully this won't have to be a lesson in Tcl. Here is my problem. I >am using ModelSim >with Xilinx ISE. I will make a simulation and arrange the signals in >the order I would like them. >If you hit "File" and then "Save" a box pops up asking "Save waveform >formats?" and then it lists >the path to the do file. I click OK and expect the waveform formats to >be saved, and they are not. >The reason they are not is that every time you re-run the simulation >by clicking "Simulate Behavioral >Model" an automatic do file is used and the waveforms revert to the >default order. Can't you save the DO file under a different name, and run that Do file later from the Modelsim prompt? - BrianArticle: 115441
On Feb 1, 6:43 pm, "radarman" <jsham...@gmail.com> wrote:
> Hello,
> I am working with an unusual board that has two Xilinx Virtex 4 FX60's
> on it in a top/bottom mirrored configuration. (The BGA's are mounted
> above/below each other, with via's running between select pins to form
> mirrored pairs)
>
> The problem I am running into is that both FPGA's must run identical
> firmware loads, and in some cases, this results in contention due to
> the mirrored pins. I do have a strap bit that can tell the design
> whether it is loaded in the top or bottom fpga, which I use to remap
> the inputs. (ie, in the top part, pin AG30 is used as the input, and
> in the bottom part, AG5 is used instead) These input muxes work fine
> using a similar concept.
>
> The idea is that the fpga ID pin can be used to forcibly tri-state
> certain outputs in either the top or bottom design to prevent the
> contention. Since the fpga ID pin is an external input, the designs
> should be able to remain the same.
>
> So, I created an EDK ip core in VHDL that instantiates an OBUFT, and
> connected it between the user logic and the external net. The VHDL is
> simply a wrapper. (I did implement a for/generate block to handle
> vectors)
>
> The problem is that ISE is turning it into a LUT based AND gate
> instead, so I still get the contention. When I look at the pad in FPGA
> Editor, the T input is not mapped.
>
> I'm using ISE/EDK 8.2.03i for this project.
>
> Any ideas?
>
> Thanks!
Did you check that the "T" input is not always enabled and logic
exists for it to drive active and inactive?
-- Newman
From invalid@dont.spam Sun Feb 11 07:21:09 2007
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From: Phil Hays <invalid@dont.spam>
Subject: Re: substracting a whole array of values at once
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CMOS wrote:
> hi,
> i need a whole matrix to be substracted form another in one clock cycle.
> and i need to store all the values of these matrices in either
> distributed or block RAM.
> i thought this is not possible with block RAM, as these have didicated
> ports that are fixed in width.
> so tried to use distributed RAM with the following verilog code.
>
>
> parameter nColumns = 100;
> parameter nRows = 200;
>
> parameter RAM_WIDTH = 8;
>
> //matrix 1 data
> reg [RAM_WIDTH-1:0] data_1[nColumns*nRows-1:0];
>
> //matrix 2 data
> reg [RAM_WIDTH-1:0] data_2[nColumns*nRows-1:0];
>
> reg [7:0] ix = 0;
> reg [7:0] iy = 0;
>
> reg[10:0] diff = 0;
>
> always @ (start) // start will trigger the calculation begin for(ix = 0;
> ix < 100; ix = ix + 1) begin
> for(iy = 0; iy < 100; iy = iy + 1) begin
> diff = diff +data_1[iy] - data_2[ix];
> end
> end
> end
>
> ise webpack completed stege one systhesis of this code after around 10
> minutes and did not complete the whole systhesis even after around 3
> hrs.
>
> any assistance is very much appreciated.
I'm answering this assuming that it is school homework.
You try simulating this code first. It just might not do what you want it
to do. For example, try the case of data_1 is all x7F and data_2 is all
x81. Calculate the expected value of diff, and see what the simulation
produces.
You might want to try a smaller example. Try to get a 2 X 2 matrix correct
first.
You might want to look at the synthesis templates. RAMs need to be coded
in fairly specific ways to be recognized. Code that is too different
from the template may not produce the expected result. To produce
distributed RAM:
parameter RAM_WIDTH = <ram_width>;
parameter RAM_ADDR_BITS = <ram_addr_bits>;
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
wire [RAM_WIDTH-1:0] <output_data>;
<reg_or_wire> [RAM_ADDR_BITS-1:0] <address>; <reg_or_wire>
[RAM_WIDTH-1:0] <input_data>;
always @(posedge <clock>)
if (<write_enable>)
<ram_name>[<address>] <= <input_data>;
assign <output_data> = <ram_name>[<address>];
--
Phil Hays (Xilinx, always writing for myself)
Article: 115442On Feb 11, 9:21 pm, Phil Hays <inva...@dont.spam> wrote: > CMOS wrote: > > hi, > > i need a whole matrix to be substracted form another in one clock cycle. > > and i need to store all the values of these matrices in either > > distributed or block RAM. > > i thought this is not possible with block RAM, as these have didicated > > ports that are fixed in width. > > so tried to use distributed RAM with the following verilog code. > > > parameter nColumns = 100; > > parameter nRows = 200; > > > parameter RAM_WIDTH = 8; > > > //matrix 1 data > > reg [RAM_WIDTH-1:0] data_1[nColumns*nRows-1:0]; > > > //matrix 2 data > > reg [RAM_WIDTH-1:0] data_2[nColumns*nRows-1:0]; > > > reg [7:0] ix = 0; > > reg [7:0] iy = 0; > > > reg[10:0] diff = 0; > > > always @ (start) // start will trigger the calculation begin for(ix = 0; > > ix < 100; ix = ix + 1) begin > > for(iy = 0; iy < 100; iy = iy + 1) begin > > diff = diff +data_1[iy] - data_2[ix]; > > end > > end > > end > > > ise webpack completed stege one systhesis of this code after around 10 > > minutes and did not complete the whole systhesis even after around 3 > > hrs. > > > any assistance is very much appreciated. > > I'm answering this assuming that it is school homework. > > You try simulating this code first. It just might not do what you want it > to do. For example, try the case of data_1 is all x7F and data_2 is all > x81. Calculate the expected value of diff, and see what the simulation > produces. > > You might want to try a smaller example. Try to get a 2 X 2 matrix correct > first. > > You might want to look at the synthesis templates. RAMs need to be coded > in fairly specific ways to be recognized. Code that is too different > from the template may not produce the expected result. To produce > distributed RAM: > > parameter RAM_WIDTH = <ram_width>; > parameter RAM_ADDR_BITS = <ram_addr_bits>; > > reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0]; > > wire [RAM_WIDTH-1:0] <output_data>; > > <reg_or_wire> [RAM_ADDR_BITS-1:0] <address>; <reg_or_wire> > [RAM_WIDTH-1:0] <input_data>; > > always @(posedge <clock>) > if (<write_enable>) > <ram_name>[<address>] <= <input_data>; > > assign <output_data> = <ram_name>[<address>]; > > -- > Phil Hays (Xilinx, always writing for myself) hi, thanks for the reply. actually its not a school homework. im doing a project in which i need to deduct an image from another. this has to be done several times to get the output. to reduce time for the calculation, i need to do the substraction in one clock cycle. in order to do that i need concurrent access to all pixels of both images. im not sure how this could be acheived with available block or distributed RAM. thank you.Article: 115443
Hi every body I want to creat a VHDL code in order to generate 576 clocks. The range of clocks frequency is [3 kHz to 75 kHz] and each of them has 125 Hz frequency difference. Can any body help me?I would appreciate it.Article: 115444
ok, I see. If you don't know the timing numbers you have two choices: 1. Check the datasheet. It should provide you with the desired information 2. If you don't have the datasheet you can run P&R and get the numbers from the timing report (but only if those paths are violated). If there is no violation there is no need to apply black box timing attributes any way. You could safely ignore Synplify's warnings. Cheers, PhilArticle: 115445
Hello, all
I simulate my design in modelsim and it works fine. But when I put it
on board, the result it wrong. I noticed the following warning in
the .mrp file complaining about DCM and I don't know what it will
affect the result.
The system uses a DCM with "PARAMETER C_CLKDV_DIVIDE = 5.000000" to
generated a 20Mhz signal from the input clk pin (100MHz in ML501
xilinx board) and work as the master clock
for microblaze. A coprocessor is connected with microblaze and part
of the design needs a syncronized 3x clock signals. So I used a DCM to
generated the 3 times clock over the master clock. But when I do the
implementation, the following warning is given:
My question is:
1, will the mean that the syncronized 3x clock generation failed?
Then why it just a warning, but not error?
2, What does it mean and how can I avoid it?
Thanks a lot,
Cathy
--------------------------------------------------------------------------------------------
WARNING:Timing:3234 - Timing Constraint
"TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
TS_sys_clk_pin * 5 HIGH 50%"
fails the maximum period check for input clock
MB0DLMBCntrl_BRAM_PORT_BRAM_Clk to DCM
...../dcm3_inst/DCM_INST because the period
constraint value (50000 ps) exceeds the maximum internal period
limit of
20001 ps. Please reduce the period of the constraint to remove
this timing
failure.
WARNING:Timing:3236 - Timing Constraint
"TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
TS_sys_clk_pin * 5 HIGH 50%"
fails the maximum period check for output clock
..../dcm3_inst/CLKFX_BUF from DCM
....t/dcm3_inst/DCM_INST because the period
constraint value (16666 ps) exceeds the maximum internal period
limit of
10001 ps. Please reduce the period of the constraint to remove
this timing
failure.
WARNING:Timing:3236 - Timing Constraint
"TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
TS_sys_clk_pin * 5 HIGH 50%"
fails the maximum period check for output clock
.../dcm3_inst/CLK0_BUF from DCM
.../dcm3_inst/DCM_INST because the period
constraint value (50000 ps) exceeds the maximum internal period
limit of
31251 ps. Please reduce the period of the constraint to remove
this timing
failure.
WARNING:Timing:3234 - Timing Constraint
"TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
TS_sys_clk_pin * 5 HIGH 50%"
fails the maximum period check for input clock
MB0DLMBCntrl_BRAM_PORT_BRAM_Clk to DCM
...../dcm3_inst/DCM_INST because the period
constraint value (50000 ps) exceeds the maximum internal period
limit of
20001 ps. Please reduce the period of the constraint to remove
this timing
failure.
WARNING:Timing:3236 - Timing Constraint
"TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
TS_sys_clk_pin * 5 HIGH 50%"
fails the maximum period check for output clock
....t/dcm3_inst/CLKFX_BUF from DCM
..../dcm3_inst/DCM_INST because the period
constraint value (16666 ps) exceeds the maximum internal period
limit of
10001 ps. Please reduce the period of the constraint to remove
this timing
failure.
WARNING:Timing:3236 - Timing Constraint
"TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
TS_sys_clk_pin * 5 HIGH 50%"
fails the maximum period check for output clock
..../dcm3_inst/CLK0_BUF from DCM
..../dcm3_inst/DCM_INST because the period
constraint value (50000 ps) exceeds the maximum internal period
limit of
31251 ps. Please reduce the period of the constraint to remove
this timing
failure.K0_BUF from DCM
..../dcm3_inst/DCM_INST because the period
constraint value (50000 ps) exceeds the maximum internal period
limit of
31251 ps. Please reduce the period of the constraint to remove
this timing
failure.
Article: 115446I bet 100 bucks that your design either contains asynchronous logic (gated clocks, ripple clocks) or doesn't meet timing. If design is asynchronous then it's your prob. If it violates timing you should get information from timing analyzer. There is no need to get angry on the Altera guys. Check your design first. Cheers, PhilArticle: 115447
The only way to subtract all values at once (!) is to use registers, not distributed memory or BlockRAM. You will also need one subtractor for each pair of image pixels. Redefine what you consider necessary. Do you have access to all those pixels at once the clock cycle after the subtract? If a new image is overwriting the first image in the clock after the subtract is supposed to happen, read the previous value and take the subtraction the same time the next value is being written. Cycle through all the values you need to subtract *as you read them* rather than requiring the subtraction happen all at once. You can do a bazillion subtracts of width n if you have 3n bazillion registers and n(+1?) bazillion LUTs. If you HAVE to have memory, you do not HAVE to have single-cycle subtracts. Think about the hardware. - John_H CMOS wrote: > hi, > i need a whole matrix to be substracted form another in one clock > cycle. > and i need to store all the values of these matrices in either > distributed or block RAM. > i thought this is not possible with block RAM, as these have didicated > ports that are fixed in width. > so tried to use distributed RAM with the following verilog code. > > > parameter nColumns = 100; > parameter nRows = 200; > > parameter RAM_WIDTH = 8; > > //matrix 1 data > reg [RAM_WIDTH-1:0] data_1[nColumns*nRows-1:0]; > > > //matrix 2 data > reg [RAM_WIDTH-1:0] data_2[nColumns*nRows-1:0]; > > reg [7:0] ix = 0; > reg [7:0] iy = 0; > > reg[10:0] diff = 0; > > always @ (start) // start will trigger the calculation > begin > for(ix = 0; ix < 100; ix = ix + 1) begin > for(iy = 0; iy < 100; iy = iy + 1) begin > diff = diff +data_1[iy] - data_2[ix]; > end > end > end > > ise webpack completed stege one systhesis of this code after around 10 > minutes and did not complete the whole systhesis even after around 3 > hrs. > > any assistance is very much appreciated. > > thank you.Article: 115448
On Feb 11, 9:21 am, "mahdi" <sagha...@gmail.com> wrote: > Hi every body > I want to creat a VHDL code in order to generate 576 clocks. > The range of clocks frequency is [3 kHz to 75 kHz] and each of them > has 125 Hz frequency difference. > Can any body help me?I would appreciate it. Unless you use an analog PLL you will have some output jitter. Let's assume you can tolerate 4 ns of jitter ( one part in 3000 at your top frequency.) Then you build a 20 bit binary accumulator, continuously add the desired multiple of 125 Hz (i.e. the value between 24 and 600, but expressed in binary) to the LSB end of the accumulator. The MSB of the accumulator is your desired output frequency, provided you clock the accumulator with a clock frequency of 250 Hz times 2exp20, which is 262.144 MHz, a reasonable clock frequency which maximizes the jitter to less than 4 ns. If you modify the accumulator to be decimal, you can use a more convenient even clock frequency. Food for thought! This technique is called Direct Digital Synthesis, or DDS. Peter AlfkeArticle: 115449
Hi, My apologies if this has been covered elsewhere - I did look! I am trying to configure a Virtex 4 FPGA from a PLX 9656 using the two Useri/o pins in SelectMAP8 mode. I can use one to monitor the DONE bit and one to drive the RDWR line. My problem is I am not sure how to generate the CCLK to the FPGA so the config data is latched correctly, anybody tried this? thanks, jim
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