Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 119425

Article: 119425
Subject: Re: Seeking the solutions of high speed interconnection for the long
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 18 May 2007 10:13:02 -0800
Links: << >>  << T >>  << A >>
PeteS wrote:

(snip)

> Where a line is significantly longer than some fraction [1] of a 
> transition time (the shortest of rise or fall time) it should be treated 
> as a transmission  line. For the newest parts, that's less than an inch.

Well, there are two conditions for a line to look like a capacitor.
One is that it has to be relatively short, and the other is that it
has to be driven by a higher impedance source and have a higher
impedance load.  That is common in analog audio, and will be for
some time to come.


(snip)

-- glen


Article: 119426
Subject: Re: Power Consumption near Timing Failure Point
From: Peter Alfke <peter@xilinx.com>
Date: 18 May 2007 11:39:24 -0700
Links: << >>  << T >>  << A >>
I cringe whenever I hear the words "metastability" and "oscillation"
used in the same sentence.
In the olden days, when metastability was easily observed in TTL
devices, we saw prolonged oscillations, since the critical feedback
paths ran through several stages.
In modern CMOS flip-flops, the master latch (the only one that we
should care about) is much simpler.
It obviously can create a metastable delay, but I have never seen it
oscillate.
Should we relegate the story of metastable oscillation to the dustbin
of history?
Unpredictable delay? YES!
Oscillation? NO!
Peter Alfke
==================================
On May 18, 10:50 am, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
> fpga_t...@yahoo.com wrote:
>
> (snip)
>
> > Metastability can occur any where we have a feedback path in logic,
> > but it's best understood in terms of FF's. It's generally defined as
> > an event when a FF continues to oscillate longer than a clock period.
>
> The way I think of it is that most people want to put some logic
> between FFs to get something done.  They then want to clock the
> circuit reasonably fast.  The result is that the margin available
> for metastability to resolve might be 1/5 of a clock cycle.  I don't
> think I would design closer than that.  Adding one extra FF gives
> one complete cycle for it to resolve, or five times as long.
>
> (snip)
>
> > This is the state we are in with a synchronous system with setup
> > violations, as the OP specifically questions about. As any number of
> > inputs to FF's hover around the metastable input voltage, the amount
> > of oscillation will increase, and increase dynamic power as a
> > result ... the amount of power increase depends directly on the system
> > design.
>
> If you are close enough to worry about setup times, then you have
> no margin left for temperature or voltage tolerance.  Even without
> metastability the system could easily fail.
>
> (snip)
>
> -- glen



Article: 119427
Subject: I need advice
From: "kemalinmaili@gmail.com" <kemalinmaili@gmail.com>
Date: 18 May 2007 11:43:35 -0700
Links: << >>  << T >>  << A >>
Hi all,

I will be dealing with two fpga projects for school ; instructer has
given some specs about these projects

Could someone please give me some advice on choosing adequate fpga
boards for these projects??

1)
* 200 MHz clock rate
* 48 pin interface( 8 pin ASCII input, 2 pin handshaking, 2pin clock,
6 pin supply and ground , 20 pin data/address multiplexed, 1 pin data/
address mode, 1 pin analog output, 8 pins digital output )
* 1 kbit on-chip ROM/RAM
* 204 Bytes on-chip ROM
* 1 Mbit on-chip/off-chip ROM
* 8 kHz digital output freaquency
* 4000  logic gates



2)

* the minimum clock frequency for real time operation 200 MHz
* Number of transistor: 373000
* Number of pins: 8 data in, 8 data out , 24 pin address. Total 64
pins including overhead
* I/O frequency 200 Mhz
* Off-chip memory minimum 2 MB


I will be so glad if any of you can give me some opinion about

appropriate fpga boards for these specs


Article: 119428
Subject: Re: I need advice
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 18 May 2007 20:01:13 +0100
Links: << >>  << T >>  << A >>

<kemalinmaili@gmail.com> wrote in message 
news:1179513815.256845.101430@n59g2000hsh.googlegroups.com...
> Hi all,

>
> I will be so glad if any of you can give me some opinion about
>
> appropriate fpga boards for these specs
>
http://www.fpga-faq.com/FPGA_Boards.shtml




Article: 119429
Subject: Re: Precision RTL and DesignWare libraries
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 18 May 2007 19:08:45 GMT
Links: << >>  << T >>  << A >>
>> From what I understand from the manual, Precision supports a wide range 
>> of
>> the datapath and logic DesignWare modules. If you use a non-supported 
>> module
>> then you will end up with a blackbox. You then need to provide the 
>> RTL/EDIF
>> for this block before going to P&R.
>
>That's what I would assume, but does it make any sense. If you specify
>a specific adder in the middle of your datapath, how does Precision
>accurately resolve its timing (pre-PNR)?

Not sure I understand you here, we are talking about ASIC prototyping using 
an FPGA right? This is no different than sticking an adder in your FPGA 
design, the timing gets resolved using the (close to useless :-) wireload 
model.

> The other option that I can
>think of, is that Precision automatically converts all the DW
>blackboxes to its own primitives, but that is a flat out guess..

Correct, Precision converts DW blocks to "functional equivalent" FPGA blocks 
and if it can't then you get a blackbox.

>
>> If Precision can translate all your Designware blocks then you can of 
>> course
>> use the Altera primitive libraries for any simulation, however, if you 
>> get
>> any blackboxes then as far as I know the only option you have is to use 
>> VCS
>> but I might be wrong,
>
>That shouldn't be an issue, you can find the DesignWare blocks
>somewhere in $SYNOPSYS/dw and compile them yourself.

Cool, didn't know that. I assume the copyright notice prevents one from 
using it on anything else but Synopsys products?

Hans
www.ht-lab.com

>
>-- Edmond CotÚ 



Article: 119430
Subject: Re: video soltion provider
From: M Ihsan Baig <mirzamihsan@hotmail.com>
Date: 18 May 2007 12:24:15 -0700
Links: << >>  << T >>  << A >>
The application is not specific but it has many uses in industry,eg
oil and gas exploration field areas, telemetry etc.
I am not expert in this area but the solutions which I have seen are
for internet, ethernet application which I think sometimes are not
suitable where customized solution is needed.
Thanks,
Ihsan Baig

On May 18, 2:41 pm, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> M Ihsan Baig <mirzamih...@hotmail.com> writes:
>
> > Hello, Is there any expert who can guide me about the following
> > problem:
>
> > I need video system with following main specifications.
> > 1) Input : standard video formats
>
> File formats, or camera sourced video?
>
> > 2) compression: MPEG4/MPEG2 etc.
> > 3) Output: RS232
>
> You must be working with pretty small frames and/or frame rates to
> expect to get the compressed video down RS232! Even 320x240x10fps @
> 8bpp = 5.8Mbits/sec.  You'd be wanting a compression ratio of about
> 50x to get that down 115kbps RS232, which I guess is feasible with
> H.264.
>
> What's the application?
>
> Cheers,
> Martin
>
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html



Article: 119431
Subject: Re: video soltion provider
From: Peter Alfke <peter@xilinx.com>
Date: 18 May 2007 12:50:04 -0700
Links: << >>  << T >>  << A >>
You wrote: Standard video formats.
(That might mean any one of many standards, B&W, NTSC, PAL?)
Also:
Do you use standard resolution and frame rate? Probably not.
This has a big impact on the design, and the feasibility of the
design.
Peter Alfke

On May 18, 12:24 pm, M Ihsan Baig <mirzamih...@hotmail.com> wrote:
> The application is not specific but it has many uses in industry,eg
> oil and gas exploration field areas, telemetry etc.
> I am not expert in this area but the solutions which I have seen are
> for internet, ethernet application which I think sometimes are not
> suitable where customized solution is needed.
> Thanks,
> Ihsan Baig
>
> On May 18, 2:41 pm, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
> > M Ihsan Baig <mirzamih...@hotmail.com> writes:
>
> > > Hello, Is there any expert who can guide me about the following
> > > problem:
>
> > > I need video system with following main specifications.
> > > 1) Input : standard video formats
>
> > File formats, or camera sourced video?
>
> > > 2) compression: MPEG4/MPEG2 etc.
> > > 3) Output: RS232
>
> > You must be working with pretty small frames and/or frame rates to
> > expect to get the compressed video down RS232! Even 320x240x10fps @
> > 8bpp = 5.8Mbits/sec.  You'd be wanting a compression ratio of about
> > 50x to get that down 115kbps RS232, which I guess is feasible with
> > H.264.
>
> > What's the application?
>
> > Cheers,
> > Martin
>
> > --
> > martin.j.thomp...@trw.com
> > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html



Article: 119432
Subject: Re: Precision RTL and DesignWare libraries
From: =?iso-8859-1?B?RWRtb25kIENvdOk=?= <edmond.cote@gmail.com>
Date: 18 May 2007 12:52:32 -0700
Links: << >>  << T >>  << A >>
On May 18, 3:08 pm, "HT-Lab" <han...@ht-lab.com> wrote:
> Not sure I understand you here, we are talking about ASIC prototyping usi=
ng
> an FPGA right? This is no different than sticking an adder in your FPGA
> design, the timing gets resolved using the (close to useless :-) wireload
> model.

Right, but wouldn't knowing that the blackbox resolves to an adder,
rather than a counter, produce a better timing estimate?... No need to
answer this, I'm simply trying to think through the mechanics of how
this all works.

> Correct, Precision converts DW blocks to "functional equivalent" FPGA blo=
cks
> and if it can't then you get a blackbox.

Ok, that answered my original question, thank you!

> Cool, didn't know that. I assume the copyright notice prevents one from
> using it on anything else but Synopsys products?

My hunch is that their license can't be *that* restrictive. I took a
look at the behavioral models and they seemed pretty standard to me.

-- Edmond Cot=E9


Article: 119433
Subject: Quartus 7.1 Simulations
From: Dan <dgrolem@gpresearch.com>
Date: 18 May 2007 12:55:38 -0700
Links: << >>  << T >>  << A >>
I have a strange issue with Quartus 7.1 simulation. I have a project
with inputs a, b, c, and d. If I include inputs a,b and d in the .vwf
file, the project will simulate in functional mode, but will not
simulate in timing mode. By not simulating, I mean that the outputs do
not toggle.

In both cases a warning appears: WARNING: Can't find signal signal in
vector source file for input pin "c". It is only the timing mode that
does not work.

If I add c to the .vwf, then timing mode corectly simulates. I don't
recall this from previous versions, but do I have to include all
inputs in the .vwf?


Article: 119434
Subject: Re: Xilinx Timing Constraint Questions
From: motty <mottoblatto@yahoo.com>
Date: 18 May 2007 13:43:40 -0700
Links: << >>  << T >>  << A >>
I have a parameterizable generate statement that controls the
inclusion of Chipscope.  So when I said it isn't used, it is not
included in the design at all.  But, I spoke too soon!

I found some problems with my recovery logic.  I was able to make it
fail at low speed and observed in Chipscope what is wrong.  Now I need
to figure out a good way to get recovered bits out of my phase bytes.
My simple algorithm didn't hold up!


Article: 119435
Subject: Re: Power Consumption near Timing Failure Point
From: fpga_toys@yahoo.com
Date: 18 May 2007 14:56:50 -0700
Links: << >>  << T >>  << A >>
On May 18, 12:39 pm, Peter Alfke <p...@xilinx.com> wrote:
> I cringe whenever I hear the words "metastability" and "oscillation"
> used in the same sentence.
> In the olden days, when metastability was easily observed in TTL
> devices, we saw prolonged oscillations, since the critical feedback
> paths ran through several stages.
> In modern CMOS flip-flops, the master latch (the only one that we
> should care about) is much simpler.
> It obviously can create a metastable delay, but I have never seen it
> oscillate.
> Should we relegate the story of metastable oscillation to the dustbin
> of history?
> Unpredictable delay? YES!
> Oscillation? NO!
> Peter Alfke

Thanks Peter ... nice to learn some nightmares are gone :)


Article: 119436
Subject: How to insert tab in Write() function in VHDL
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: 18 May 2007 15:11:24 -0700
Links: << >>  << T >>  << A >>
Hi,
I want to insert tab in write() function in VHDL.

Here is a write() function definition:
    procedure WRITE(L : inout LINE; VALUE : in character;
	      JUSTIFIED: in SIDE := right;
	      FIELD: in WIDTH := 0);

Here is character definition:
package standard is
	type character is (
		nul, soh, stx, etx, eot, enq, ack, bel,
		bs,  ht,  lf,  vt,  ff,  cr,  so,  si,
		dle, dc1, dc2, dc3, dc4, nak, syn, etb,
		can, em,  sub, esc, fsp, gsp, rsp, usp,

		' ', '!', '"', '#', '$', '%', '&', ''',
		'(', ')', '*', '+', ',', '-', '.', '/',
		'0', '1', '2', '3', '4', '5', '6', '7',
		'8', '9', ':', ';', '<', '=', '>', '?',

I want to know which one is tabulator (tab).

Thank you.

Weng


Article: 119437
Subject: Re: How to insert tab in Write() function in VHDL
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Sat, 19 May 2007 00:19:27 +0200
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:
> Hi,
> I want to insert tab in write() function in VHDL.
> 
> Here is a write() function definition:
>     procedure WRITE(L : inout LINE; VALUE : in character;
> 	      JUSTIFIED: in SIDE := right;
> 	      FIELD: in WIDTH := 0);
> 
> Here is character definition:
> package standard is
> 	type character is (
> 		nul, soh, stx, etx, eot, enq, ack, bel,
> 		bs,  ht,  lf,  vt,  ff,  cr,  so,  si,
> 		dle, dc1, dc2, dc3, dc4, nak, syn, etb,
> 		can, em,  sub, esc, fsp, gsp, rsp, usp,
> 
> 		' ', '!', '"', '#', '$', '%', '&', ''',
> 		'(', ')', '*', '+', ',', '-', '.', '/',
> 		'0', '1', '2', '3', '4', '5', '6', '7',
> 		'8', '9', ':', ';', '<', '=', '>', '?',
> 
> I want to know which one is tabulator (tab).

ht

Article: 119438
Subject: How do I constraint multiple clock cycle in Altera?
From: "news reader" <newsreader@google.com>
Date: Sat, 19 May 2007 11:07:55 +0800
Links: << >>  << T >>  << A >>
Hello everybody,

My Altera design uses multiple clock cycle and negative clock edge, how do I 
constraint it?
Here is my code, absolute_addr is generated 1.5 clocks earlier before 
consumption.

I am reading the Quartus II Classic timing analyzer manual, but am not clear 
how to constrain
this logic.

Hope you can help me out.

Many thanks from newsreader.




// My code segment

reg start_sequence;
reg [2:0] addr_en;  // one-hot
reg [31:0] absolute_addr;
reg [1:0] ram_ba;
reg [15:0] ram_row;
reg [7:0] ram_col;

always @(posedge clk_100m or negedge arst_n) begin
if (!arst_n) begin
 addr_en <= 2'd0;
end
else begin
 addr_en <= {addr_en[1:0], start_sequence};
end
end

always @(posedge clk_100m or negedge arst_n) begin
if (!arst_n) begin
 absolute_addr <= 26'd0;
end
else begin
 if (addr_en[0])
  absolute_addr <= complex_addr_gen_func(......);  // Expecting take 12ns
end
end

always @(negedge clk_100m or negedge arst_n) begin
if (!arst_n) begin
 ram_ba <= 2'd0;
 ram_row <= 16'd0;
 ram_col <= 8'd0;
end
else begin
 if (addr_en[2]) begin
  ram_ba <= absolute_addr[25:24];
  ram_row <= absolute_addr[23:8];
  ram_col <= absolute_addr[7:0];
 end
 else begin
  ram_ba <= 2'd0;
  ram_row <= 16'd0;
  ram_col <= 8'd0;
 end
end
end





Article: 119439
Subject: EDK 8.1i to EDK 9.1i UCF file errors
From: Nju Njoroge <njoroge@stanford.edu>
Date: 18 May 2007 20:48:29 -0700
Links: << >>  << T >>  << A >>
Hello,

In our *working* EDK 8.1i project, we locked a DCM in the following
manner in the UCF file (located in <proj_dir>/data/system.ucf):


INST dcm_sys/dcm_sys/DCM_INST       LOC = DCM_X0Y0;
INST ppc405_0/ppc405_0/PPC405_i     LOC = PPC405_X1Y0;

The dcm module, named "dcm_sys" in the MHS file did not give us any
problems in 8.1i. However, taking the same project (i.e. same MHS, UCF
files) and syncing-up to EDK 9.1, I now get the following error during
a bit stream generation (in the file xflow.log):


ERROR:NgdBuild:752 - "system.ucf" Line 19: Could not find instance(s)
    'dcm_sys/dcm_sys/DCM_INST' in the design.  To suppress this error,
specify
    the correct instance name or remove the constraint.  The 'Allow
Unmatched LOC
    Constraints' ISE property can also be set ( -aul switch for
command line

It seems like that the way that EDK looks at the organization of
top-level modules in the MHS file is now different. Any pointers? I
tried changing  "dcm_sys/dcm_sys/DCM_INST" to "dcm_sys/DCM_INST", but
that failed. I suppose I can remove the constrait, but someone else
placed that constraint for a reason....

Thanks,

NN


Article: 119440
Subject: Re: Visio logic symbols
From: joseph2k <quiettechblue@yahoo.com>
Date: Fri, 18 May 2007 21:20:10 -0700
Links: << >>  << T >>  << A >>
Richard Henry wrote:

> Does anyone know of a location from which to download simple logic
> symbol shapes for Visio (and gate, or gate, etc)?
Nothing personal, but why use an inadequate tool to do what LTSpice does
quickly easily and natively, and best of all, for free.
-- 
 JosephKK
 Gegen dummheit kampfen die Gotter Selbst, vergebens.  
  --Schiller

Article: 119441
Subject: releasing some FPGA tools-ip as open-source
From: Antti <Antti.Lukats@googlemail.com>
Date: 18 May 2007 23:48:45 -0700
Links: << >>  << T >>  << A >>
http://code.google.com/p/fpga-tools/downloads/list

released
1) JTAG TAP+BSCAN softcore, can use as BSCAN in fabric to use
chipscope-mdm when FPGA jtag pins not accessible
2) SystemACE tools: dump, compress, player

Why?
mostly because I am sick and tired to even remember of what I have
done, not to mention that I spend again and again time looking for my
own projects, spanned over many PC's harddisks, backup DVDs - ending
up searching with google or rewriting from scratch. So releasing as
open-source makes sense, when the project becomes available and can be
found quick (google search is always faster then "find" on any of my
workstation PC). I plan to release more stuff, when I find it, this
includes projects that I have hoped to be commercial.


Antti


Article: 119442
Subject: Re: How do I constraint multiple clock cycle in Altera?
From: Rajkumar Kadam <shubamshreyas@yahoo.com>
Date: 19 May 2007 00:11:44 -0700
Links: << >>  << T >>  << A >>
Hi!
Create a separate negative clock signal, either as a primary port (do
the inversion outside this module)
and constraint this module by creating 2 clocks, phase shifted by 180,
and adding a multicycle path between these 2 clocks
Let me know if it helps

Rajkumar...

news reader wrote:
> Hello everybody,
>
> My Altera design uses multiple clock cycle and negative clock edge, how do I
> constraint it?
> Here is my code, absolute_addr is generated 1.5 clocks earlier before
> consumption.
>
> I am reading the Quartus II Classic timing analyzer manual, but am not clear
> how to constrain
> this logic.
>
> Hope you can help me out.
>
> Many thanks from newsreader.
>
>
>
>
> // My code segment
>
> reg start_sequence;
> reg [2:0] addr_en;  // one-hot
> reg [31:0] absolute_addr;
> reg [1:0] ram_ba;
> reg [15:0] ram_row;
> reg [7:0] ram_col;
>
> always @(posedge clk_100m or negedge arst_n) begin
> if (!arst_n) begin
>  addr_en <= 2'd0;
> end
> else begin
>  addr_en <= {addr_en[1:0], start_sequence};
> end
> end
>
> always @(posedge clk_100m or negedge arst_n) begin
> if (!arst_n) begin
>  absolute_addr <= 26'd0;
> end
> else begin
>  if (addr_en[0])
>   absolute_addr <= complex_addr_gen_func(......);  // Expecting take 12ns
> end
> end
>
> always @(negedge clk_100m or negedge arst_n) begin
> if (!arst_n) begin
>  ram_ba <= 2'd0;
>  ram_row <= 16'd0;
>  ram_col <= 8'd0;
> end
> else begin
>  if (addr_en[2]) begin
>   ram_ba <= absolute_addr[25:24];
>   ram_row <= absolute_addr[23:8];
>   ram_col <= absolute_addr[7:0];
>  end
>  else begin
>   ram_ba <= 2'd0;
>   ram_row <= 16'd0;
>   ram_col <= 8'd0;
>  end
> end
> end


Article: 119443
Subject: Re: releasing some FPGA tools-ip as open-source
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 19 May 2007 19:28:35 +1200
Links: << >>  << T >>  << A >>
Antti wrote:

> http://code.google.com/p/fpga-tools/downloads/list
> 
> released
> 1) JTAG TAP+BSCAN softcore, can use as BSCAN in fabric to use
> chipscope-mdm when FPGA jtag pins not accessible
> 2) SystemACE tools: dump, compress, player
> 
> Why?
> mostly because I am sick and tired to even remember of what I have
> done, not to mention that I spend again and again time looking for my
> own projects, spanned over many PC's harddisks, backup DVDs - ending
> up searching with google or rewriting from scratch. So releasing as
> open-source makes sense, when the project becomes available and can be
> found quick (google search is always faster then "find" on any of my
> workstation PC). 

:)

> I plan to release more stuff, when I find it, this
> includes projects that I have hoped to be commercial.

I'd imagine it's a treasure trove there....

Good idea, and good luck.

-jg




Article: 119444
Subject: Re: Mutiple MAC on OPB Bus
From: Venu <get2venu@gmail.com>
Date: 19 May 2007 02:25:53 -0700
Links: << >>  << T >>  << A >>
Thanks a lot , that was the error that I was making .


Zara wrote:
> On Wed, 16 May 2007 16:19:40 +0000 (UTC), Matthew Hicks
> <mdhicks2@uiuc.edu> wrote:
>
> >Regenerate the linker script and try again.
> >
> >
> >---Matthew Hicks
> >
> >
> <...>
> >>
> >> Is there any constraint regarding the number of Ethernet MAC that you
> >> can place on the OPB Bus? I have attempting to put 2 MACs on the Bus,
> >> but as soon as a instantiate the second MAC and attempt to generate
> >> bitstream, I get the following error: address space overlap! This
> >> error is generated by PlatGen
> >>
> >> I am certain address overlap that this is not the problem , because I
> >> have gone through the entire address map of my system. No two
> >> peripherals are assigned the same address space.
> >>
> <..>
>
> I don't think regenerating the linker script will work, it has nothing
> to do with PlatGen!
>
> I have tried it, and the problem seems to lie within the opb_ethernet
> core itself. It will not allow me to instantiate neither one nor two
> of them. In fact, every core instantiated has an address overlap with
> itself!
>
> The problem arises when connecting both MSOPB and SOPB, i f you only
> connect SOPB *or* MSOPB there is no address overlap. I had the same
> misunderstanding the firts time I tried: I thought MSOPB was only the
> master part, but it is both parts of the bus at the same time!
>
>
> Best regards,
>
> Zara


Article: 119445
Subject: external clock frequency doubles
From: Venu <get2venu@gmail.com>
Date: 19 May 2007 02:35:38 -0700
Links: << >>  << T >>  << A >>
Hi People,

I am attempting to interface the Xilinx Virtex - II Pro FPGA with a
quad channel codec.

I am using XC2VP30-FF896 FPGA on the Xilinx University Program
Development Board.I had applied a 2.048MHz TDM clock to the FPGA pin
B16, which is the GCLK6S ( Global Clock Input).

My problem is that by the time this clock reaches my IP on the OPB
Bus , its frequency doubles!!  I have confirmed this by checking
pulses generated on the basis of this clock, on a Digital
Oscilloscope.

I have confirmed that I have not instantiated a DCM in the external
clock path . The resource utilisation shows that the system uses only
1 DCM , which is attached to the sys_clk_s.

For now , to make my system work , i have divided the clock frequency
inside my IP and then applied it to the individual block. But the
confusion of why this exactly happened still remains.

Thanks
Venu


Article: 119446
Subject: Re: How to insert tab in Write() function in VHDL
From: "Symon" <symon_brewer@hotmail.com>
Date: Sat, 19 May 2007 12:06:25 +0100
Links: << >>  << T >>  << A >>
"Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote in 
message news:464E266F.2070308@youknowwhattodo.com...
> Weng Tianxiang wrote:
>>
>> I want to know which one is tabulator (tab).
>
> ht
or vt 



Article: 119447
Subject: Re: How to insert tab in Write() function in VHDL
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 19 May 2007 15:09:25 +0100
Links: << >>  << T >>  << A >>
On Sat, 19 May 2007 12:06:25 +0100, 
<symon_brewer@hotmail.com> wrote:

>>> I want to know which one is tabulator (tab).
>>
>> ht

>or vt 

I know what VT did on an ASR33 Teletype, but 
I'm not at all sure what it's supposed to do
these days ...

Tabs of any kind are extremely bad news anyway,
because their appearance is so strongly dependent
on the editor or viewer that you use to do the
rendering.  I hate 'em.  Compute how many spaces
you need and insert the spaces explicitly.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 119448
Subject: Re: releasing some FPGA tools-ip as open-source
From: Antti <Antti.Lukats@googlemail.com>
Date: 19 May 2007 08:57:23 -0700
Links: << >>  << T >>  << A >>
Jim Granville schrieb:
> Antti wrote:
>
> > http://code.google.com/p/fpga-tools/downloads/list
> >
> > released
> > 1) JTAG TAP+BSCAN softcore, can use as BSCAN in fabric to use
> > chipscope-mdm when FPGA jtag pins not accessible
> > 2) SystemACE tools: dump, compress, player
> >
> > Why?
> > mostly because I am sick and tired to even remember of what I have
> > done, not to mention that I spend again and again time looking for my
> > own projects, spanned over many PC's harddisks, backup DVDs - ending
> > up searching with google or rewriting from scratch. So releasing as
> > open-source makes sense, when the project becomes available and can be
> > found quick (google search is always faster then "find" on any of my
> > workstation PC).
>
> :)
>
> > I plan to release more stuff, when I find it, this
> > includes projects that I have hoped to be commercial.
>
> I'd imagine it's a treasure trove there....
>
> Good idea, and good luck.
>
> -jg

Thanks Jim,

I will peek more into the "treasure trove" and upload the findings as
my time permits.
right now i need to port the systemACE player to this tiny module

http://www.dev-kit.org/

of course als need some other JTAG code to be ported, not only
systemace player
so can use the module as jtag loader

Antti


Article: 119449
Subject: Re: external clock frequency doubles
From: Peter Alfke <alfke@sbcglobal.net>
Date: 19 May 2007 09:21:11 -0700
Links: << >>  << T >>  << A >>
Venu,
I am sure that your problem is caused by poor signal integrity at the
clock input to the FPGA. There may be overshoot, undershoot and
ringing, which causes the FPGA to interpret the falling clock edge as
another rising clock edge.
Try to clean up the clock signal, terminate it properly.
2 MHz is a very low clock frequency, and it might have a slow rise/
fall time, which might be another source of double-triggering caused
by noise during the transition.
Peter Alfke, from home.


On May 19, 2:35 am, Venu <get2v...@gmail.com> wrote:
> Hi People,
>
> I am attempting to interface the Xilinx Virtex - II Pro FPGA with a
> quad channel codec.
>
> I am using XC2VP30-FF896 FPGA on the Xilinx University Program
> Development Board.I had applied a 2.048MHz TDM clock to the FPGA pin
> B16, which is the GCLK6S ( Global Clock Input).
>
> My problem is that by the time this clock reaches my IP on the OPB
> Bus , its frequency doubles!!  I have confirmed this by checking
> pulses generated on the basis of this clock, on a Digital
> Oscilloscope.
>
> I have confirmed that I have not instantiated a DCM in the external
> clock path . The resource utilisation shows that the system uses only
> 1 DCM , which is attached to the sys_clk_s.
>
> For now , to make my system work , i have divided the clock frequency
> inside my IP and then applied it to the individual block. But the
> confusion of why this exactly happened still remains.
>
> Thanks
> Venu





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search