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On Tue, 28 Oct 2008 08:55:12 +0000, Martin Thompson <martin.j.thompson@trw.com> wrote: >Paul Boven <p.boven@xs4all.nl> writes: > >> I'm not sure yet whether the input IOBs are clocking in the data >> directly, I will try and find out through the FPGA editor. If not, >> I'll add an extra level of registers, I guess. > >I don't know if you've come across this, but I've found in the past >(ISE9.1) that the extra level of regs *has* to go in the top level for >them to be packed into the IOs. I spent a while putting the extra >level into the module that needed them, with no effect :( I have never done that. I have had to spend some time adding attributes "IOB", "keep" and "equivalent-register-removal" to the appropriate signals, but it worked with the registers where I wanted them. Admittedly I didn't try it in 9.1, but it worked in 7.1 and 10.1. (though 10.1 needed changes to the addributes required; I always had a suspicion it wasn't working correctly in 7.1 but didn't pin the issue down closely enough for a webcase) Oddly the values for "keep" are "true" and "false", but for equivalent-register-removal the values are "yes" and "no"... See for example http://www.xilinx.com/support/answers/21699.htm I'm not arguing against putting the registers at the top level; if it works portably it may be simpler than pushing a piece of string with attributes. - BrianArticle: 136026
On Oct 27, 4:10=A0am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > eubankss...@gmail.com wrote: > > I am fairly new to CPL development, and I need to create an emulation > > of a number of old bipolar Proms (256x4) being used in a very old > > system by using a CPLD and WInCUPL. > [snip] > > Is there by chance a vendor that that you know of that currently > > provides CPLDs that would meet my capacity requirements but packaged > > as a small SOIC or similar? (IOW, something that could easily fit > > within the size of a 16 pin DIP) =A0I have looked around, but most go > > down to 44pin QFP which would still be too large. > > PLCC32 is not far off ? - that would allow a 27E512, which is a curent > device and will exactly emulate your PROM. (unless the last ns matters) > > -jg Cypress makes NV RAMs in very small packages. The 1M parts come in SSOP. 25nS access time and "hands off" power down storage. If you don't need to change the content on the fly you could just program them once and tie the write enable off...Article: 136027
Thank you everyone. I have successfully downloaded the program to the FPGA board. Thanks again PanthoArticle: 136028
Hello! I'm a bit ambitious (crazy?) and trying to get a Spartan-3
design talking to a set of DDR2 ICs. I'm exploring my termination
options, and I've seen the following:
1. The Spartan-3AN Starter kit terminates all of the DDR2 signals by
pulling them to 0.9V through a 50-ohm resistor. The Spartan-3{A, AN,
E} series lack DCI on their IOBs.
2. The Spartan-3 (classic) datasheet shows that the part supports the
SSTL18_I_DCI IO standard, but sets the output impedance of the driver
to be 25 ohms (whereas everyone else seems to be using 50 ohms)
3. I've seen lots of comments suggesting I avoid using DCI in general,
as "it doesn't work" and "it's a power-hog".
So what are people's recommendations with respect to this particular
interface? I'd love to avoid having to manually place termination
resistors everywhere on my PCB, but if DCI doesn't work or if it's
going to conflict with the expected input impedance of my DDR2 ICs, I
may have no other option.
Thanks for any help or insight you can provide, DDR2 on S-3 (classic)
seems to be a bit of a no-mans land.
...Eric
Article: 136029> Please recommend either a book or web reference or learning > VHDL that would be good for someone that is experienced in FPGA architecture > and Verilog. Another good book with examples: VHDL For Designers by Stefan Sjoholm, Lennart LindhArticle: 136030
Hi I have implemented a very simple processor architecture and I was now taking a closer look at the floorplan using the Xilinx toolset. What I saw there is rather strange. It not only seems that all the Registers of the register file are distributed all over the FPGA, even the single bits of the registers are located at completly different locations. So I wonder if there is a chance to tell ISE that it should instantiate a logic block that holds all the registers of the register file in logic cells located next to each other? Many thanks, PhilippArticle: 136031
Hi
I am trying to write a state machine in system verilog. I am using an enum
for the states e.g.
enum logic [1:0] {one, two, three} state, next;
I have a sequential process which init the state to one e.g.
always_ff @(posedge clk)
begin
if (~reset_n) begin
state <= one;
end else begin
state <= next;
end
end
When I try and sythesise it usingg Synplify it complains that :-
Initial value is not supported on state machine state
It doesnt seem to like the state <= one;
I dont understand what is wrong with this, can anybody help?
Cheers
Jon
Article: 136032> There is a constraint called RLOC_RANGE which you might want to look into. > It could probably help you with this. Thanks, I will take a look into this! > However, I would recommend that you look at your timing report to see if > you would actually benefit from trying to optimize the register file at > this point. If your critical path is not located in the register file you > don't gain much by optimizing the register file... Its not about optimizing for speed or area. But for my purposes (we wanna measure the EM of the register file) it would be helpful if the registers are grouped all together!Article: 136033
> Its not about optimizing for speed or area. But for my purposes (we > wanna measure the EM of the register file) it would be helpful if the > registers are grouped all together! In this case you need to look into Synthesis Constraints such as RLOC (as was advised before) or AREA_GROUP. The latter worked for me better - as you can manually forse the design to be located where you want (exact slice coordinates). -- AlexArticle: 136034
Hi All, If you need to drawing timing diagrams or analyze interface timings, try the TimingAnalyzer. www.timing-diagrams.com As always, user feedback is welcome. User suggestions are now listed on the "Features" webpage. Thank you, Dan FabrizioArticle: 136035
Hi Dan, I looked at your TimingAnalyzer, seems to be promizing however I don't see how you capture the signals. Are there any probe ? Not very clear to me... Stupid I should be... lol... pf "timinganalyzer" <timinganalyzer@gmail.com> a écrit dans le message de news: 545f9c00-ec2f-4e3d-8456-d0808d8758e4@t18g2000prt.googlegroups.com... > Hi All, > > If you need to drawing timing diagrams or analyze interface timings, > try the TimingAnalyzer. > > www.timing-diagrams.com > > As always, user feedback is welcome. User suggestions are now listed > on the "Features" webpage. > > Thank you, > Dan FabrizioArticle: 136036
> I see. This sounds pretty interesting, perhaps you could post something to > this newsgroup once you have some results? > > In what context are you trying to measure this? Security research? Yes, exactly. Will keep you up to date as soon as we have obtained some results! Cheerios, PhilippArticle: 136037
> In this case you need to look into Synthesis Constraints such as RLOC > (as was advised before) or AREA_GROUP. > The latter worked for me better - as you can manually forse the design > to be located where you want (exact slice coordinates). Cheers Alex, will have a look at the AREA_GROUP Contrainst. The only problem is, that my register file is not instantiated in the top level of the design and this seems to be a precondition. Cheers, PhilippArticle: 136038
>> In this case you need to look into Synthesis Constraints such as RLOC >> (as was advised before) or AREA_GROUP. >> The latter worked for me better - as you can manually forse the design >> to be located where you want (exact slice coordinates). > > Cheers Alex, will have a look at the AREA_GROUP Contrainst. The only > problem is, that my register file is not instantiated in the top level > of the design and this seems to be a precondition. > > Cheers, > Philipp Don't see any problem with that, as long as you know your hierarchy and the name of the instance you want to constrain. For example AREA_GROUP "AG_reg_file" RANGE = SLICE_X24Y12:SLICE_X25Y12,SLICE_X23Y13:SLICE_X26Y13 INST "top/h1/h2/YOUR_REG_FILE" AREA_GROUP = "AG_reg_file" -- AlexArticle: 136039
On Oct 28, 12:10=A0pm, "Pierre-Fran=E7ois \(f5bqp_pfm\)" <pfmonet_NOSPAM_@_MAPSON_wanadoo.fr> wrote: > Hi Dan, > > I looked at your TimingAnalyzer, seems to be promizing however I don't se= e > how you capture the signals. > Are there any probe ? > Not very clear to me... Stupid I should be... lol... > > pf > > "timinganalyzer" <timinganaly...@gmail.com> a =E9crit dans le message de = news: > 545f9c00-ec2f-4e3d-8456-d0808d875...@t18g2000prt.googlegroups.com... > > > Hi All, > > > If you need to drawing timing diagrams or analyze interface timings, > > try the TimingAnalyzer. > > >www.timing-diagrams.com > > > As always, user feedback is welcome. =A0User suggestions are now listed > > on the "Features" webpage. > > > Thank you, > > Dan Fabrizio Hello pf, You draw the timing diagrams using the graphical user interface (menu selections and mouse control) or by using scripts. In a version coming soon, you will be able to import simulation outputs in the VCD format and quickly build diagrams from simulation waveforms. Also, tools like Xilinx chipscope can save VCD files so you document chipscope waveform displays this way. I hope this answers your questions. You can download the program and use it to see how it works. There is some help built in, but it needs to be updated and expanded. Regards, DanArticle: 136040
On Oct 9, 8:35=A0pm, "Gary Pace" <a...@xyz.com> wrote: > Hello : > > --- > > I am thinking about this :http://www.trainingcity.com/course_outline_deta= il.asp?CourseID=3D3100 > > Anybody have experience with this course or this company ? > > Any suggestions would be appreciated. > > Gary Hi Gary: I work for TrainingCity & I'd be happy to answer any questions you have on our VHDL class. Our instructor is a well known industry vet and has literally hundreds of reference clients who have attended the class from all over North America. If you would like to speak with a reference, give me a call anytime at my office number 613 * 435 * 1170 or drop me a line at John at TrainingCity dot com!Article: 136041
Hi Xilinx gurus,
I've got some code which I've been running on Altera silcon for several
weeks now, used in a number of different projects, synthesized with
Quartus v8.
It's a simple shift register implemented using a variable in a clocked
process...
process (reset, clk, clk_ena)
variable hactive_v_r : std_logic_vector(3 downto 0) := (others => '0');
begin
if reset = '1' then
hactive_v_r := (others => '0');
elsif rising_edge(clk) and clk_ena = '1' then
...
hactive_v_r := hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s;
end if;
end process;
BTW 'h_active_s' is a signal declared in the containing entity, and is
definitely not optimised out.
However, when building the project for Xilix under ISE 9.2.03i, I get the
following warnings during synthesis:
WARNING:Xst:653 - Signal <hactive_v_r<3>> is used but never assigned. Tied
to value 0.
WARNING:Xst:1780 - Signal <hactive_v_r<2:0>> is never used or assigned.
As a result, the code doesn't work - the results suggest that this shift
register has indeed been removed from the design.
As I said, this module is used - exactly as-is, in its entirety, in
several Altera modules.
Any idea what my problem is???
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Article: 136042Mark McDougall wrote: Interesting - if I change the variables to signals, it works! Bug? -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136043
On Oct 29, 10:45=A0am, Mark McDougall <ma...@vl.com.au> wrote: > Mark McDougall wrote: > > Interesting - if I change the variables to signals, it works! > > Bug? > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 My understanding is that VARIABLES are visible only inside the process and hence getting optimised. Is the variable "hactive_v_r" read/used in other part of code and are you able to compile the code? You should get compilation error too. --SandeepArticle: 136044
Hi Dan, Yes this answer my question. Many thanks. Best regards pf "timinganalyzer" <timinganalyzer@gmail.com> a écrit dans le message de news: 0b212725-10d9-4f1f-97a2-93c3544f45cc@m73g2000hsh.googlegroups.com... On Oct 28, 12:10 pm, "Pierre-François \(f5bqp_pfm\)" <pfmonet_NOSPAM_@_MAPSON_wanadoo.fr> wrote: > Hi Dan, > > I looked at your TimingAnalyzer, seems to be promizing however I don't see > how you capture the signals. > Are there any probe ? > Not very clear to me... Stupid I should be... lol... > > pf > > "timinganalyzer" <timinganaly...@gmail.com> a écrit dans le message de > news: > 545f9c00-ec2f-4e3d-8456-d0808d875...@t18g2000prt.googlegroups.com... > > > Hi All, > > > If you need to drawing timing diagrams or analyze interface timings, > > try the TimingAnalyzer. > > >www.timing-diagrams.com > > > As always, user feedback is welcome. User suggestions are now listed > > on the "Features" webpage. > > > Thank you, > > Dan Fabrizio Hello pf, You draw the timing diagrams using the graphical user interface (menu selections and mouse control) or by using scripts. In a version coming soon, you will be able to import simulation outputs in the VCD format and quickly build diagrams from simulation waveforms. Also, tools like Xilinx chipscope can save VCD files so you document chipscope waveform displays this way. I hope this answers your questions. You can download the program and use it to see how it works. There is some help built in, but it needs to be updated and expanded. Regards, DanArticle: 136045
Gabor wrote: > On Oct 27, 4:10 am, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: >>PLCC32 is not far off ? - that would allow a 27E512, which is a curent >>device and will exactly emulate your PROM. (unless the last ns matters) >> >>-jg > > > Cypress makes NV RAMs in very small packages. The 1M parts > come in SSOP. 25nS access time and "hands off" power down storage. > If you don't need to change the content on the fly you could just > program them once and tie the write enable off... Or, I see Jameco lists N82S129, 256X4, DIP-16, 50ns, as stocked - they have 891 pcs!! Could try one of those? or, if you need higher volumes - and are not price sensistive ;) try someone who still makes them : http://www.qpsemi.com/b_prom.asp -jgArticle: 136046
Hi all, I have encountered a problem where I least expected. I am using EDK 10.1.03 and I have build a system with 17 slaves on a PLBv4.6 bus. Well, the plb wrapper XPS reported an error: something like C_NUM_SLAVES = 17 is out of range [0:16] What should I do? Use a bridge and add another PLB or copy plb_v46 core to local dir and expand the range to 17? Cheers, AlesArticle: 136047
On Wed, 29 Oct 2008 13:24:46 +1100, Mark McDougall <markm@vl.com.au> wrote: >Hi Xilinx gurus, > > >I've got some code which I've been running on Altera silcon for several >weeks now, used in a number of different projects, synthesized with >Quartus v8. > >It's a simple shift register implemented using a variable in a clocked >process... > >process (reset, clk, clk_ena) > variable hactive_v_r : std_logic_vector(3 downto 0) := (others => '0'); >begin > if reset = '1' then > hactive_v_r := (others => '0'); > elsif rising_edge(clk) and clk_ena = '1' then > ... > hactive_v_r := hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s; > end if; >end process; >As I said, this module is used - exactly as-is, in its entirety, in >several Altera modules. > >Any idea what my problem is??? As written here, XST appears to be correct. hactive_v_r is a variable, assigned as the last line of the process, and not used anywhere in the process (except in assignment to itself). As a variable local to the process, it has no visibility outside the process, so XST may optimise it out. There is something else going on, that you haven't shown us. - BrianArticle: 136048
On Wed, 29 Oct 2008 04:29:23 -0700 (PDT), ales.gorkic@gmail.com wrote: >Hi all, > >I have encountered a problem where I least expected. >I am using EDK 10.1.03 and I have build a system with 17 slaves on a >PLBv4.6 bus. >Well, the plb wrapper XPS reported an error: >something like C_NUM_SLAVES = 17 is out of range [0:16] > >What should I do? >Use a bridge and add another PLB or copy plb_v46 core to local dir and >expand the range to 17? Expanding the range to 17 may well result in much larger, slower logic being generated. (Which may not be a problem, but without having tried, I wouldn't expect a smooth road this way) I would look at a bridge. Or I would consider if it is easy to combine two of your slaves into one that performs both functions (e.g. 2 memory spaces or register files into one larger one) - BrianArticle: 136049
On 2008-10-29, Philipp <Patrick.Bateman23@gmx.at> wrote: > Alex wrote: >> First make sure that keep hierarchy is on (you might want to try to >> place directly to the UCF file). >> Also check that your register file is still there after synthesis, i.e. >> it has not been optimized or combined with >> something else (in case of memory - it could well be the case). >> To chek it - try >> INST "Testbench/ARC_Ndp/Arc_Reg_File" OPTIMIZE=OFF; >> and see if this helps. > > > Cheers Alex, I have to leave now but will try it tomorrow and let you > know if it helped! Another reason that this doesn't work might be that the hierarchy separator is set to _ instead of /. Take a look in the floorplanner to see what the name of the unit really is if you haven't done so already. /Andreas
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z