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[CUT: my own post] Hey Frank, MK and goli. Well resson to why we aim for the embedded softcore is that we have allot of custom hardware already within the FPGA. Some of this hardware output ALLOT of data which is "easy" to interface to an embedded softcore becuase of the high bandwidth internaly in the FPGA. Interfacing to an external CPU is quite harder (in terms of bandwidth on a standard low cost MCU) and offcourse also give the BOM add. Regards. MMJArticle: 135626
Peter Alfke schrieb: > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote: >> Hi, >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So >> I put around 200 inverters in series and get the desired delay. So I >> did port map the BASIC cell "INV" according to the XST settings. >> But when i place and route I guess the optimizer removes all the >> intermediate buffers and I get very less delay when I do a post route >> simulation. >> How can I get rid of this problem? >> Thanks in advance. >> -Pratap > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns > delay, but that delay is stable over temperature, voltage, and > processing, because it is referenced to a 200 MHz clock (I call that > servo-stabilized). > Peter Alfke, Xilinx Is IDELAY available in any spartan devices? Thanks, ThomasArticle: 135627
Hi, I am a design engineer, i have avnet xcv5lx110t board, it has a ddr2 sdram (mt47h14m16bg-5e, micron) attached, xilinx provides its MIG controller, i installed mig v1.72 , and generated a ddr2 sdram controller, with data width 32, with its provided test bench. when i simulated the design with modelsim 6.1e, there were compiler errors that showed " data_dq runs out of its bounds", when i checked, there was these error in its test bench after generation, 1. ddr2.v ( bus functional model) takes data width data_dq[31:0], in its one instance, but in instantiation it was only given 8 bit data width in all its nine instances. 2. memory_interface_top.v takes [64:0] data width, but during its instantiation in the test bench, it was given 32 bit data width. Please do help me in this regardArticle: 135628
Alright then.7 DUALs means 7 RocketIOs with both RX and TX connected, i.e. 14 lanes? In my application I'd like to have 10 MGTs (both RX + TX) running at 3.125 Gbps, 4 running at 5 Gbps, 2 at 4.25 Gbps and another 4 running at 2.5 Gbps. Which RocketIOs would you recommend to combine, relating to a shared reference MGTCLK input? While we're at it, I've got another question concerning the power supply. On the ML510 eval platform Xilinx used seperate 1.0V supply modules for every MGT reference voltage input. That looks quite exaggerated to me. Is that a mandatory requirement? Saul "Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag news:_MrHk.2845$as4.166@nlpi069.nbdc.sbc.com... > Saul Bernstein wrote: >> >> Same problem - still much worse - with the RocketIO reference clocks! >> Plenty of clock inputs but. much too confusing! For example I'd like to >> take one reference clock for an arrangement of 10 RocketIOs. No problem >> with Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 >> for the clocks can only supply 4 RocketIOs at once... as far as I can >> judge. >> > > The Virtex-5 MGT REFCLK inputs can span up and down 3 of the GTP_DUAL or > GTX_DUAL sites, so you can reach 7 DUALs or 14 lanes. > > Ed McGettigan > -- > Xilinx Inc.Article: 135629
> * Bad documentation on both tools and eval boards. Some stuff will > never work if you don't reverse engineer HW or get correct support. > * Outdated tutorials regarding to tool and HW revisions. > * Poorly integrated and bugy tools. > * Extremely slow JTAG connection to the CPU (19kbit/sec) for SW > debugging/downloading. > * Hard to trouple shot the CPU configuration (e.g. SW debugger cannot > connect to the CPU). > * Tools crashes > * Overall poorly matured product (Mico32 and tools). > > So my questions are: > * Is the stuff (NIOS II and tools) from Altera (or any other vendor) > any better regarding the complaints above? I never used Lattice soft core cpu but with Altera & NIOS it's not so difficult at begin. In NIOS case alway you have to use kind of "system generator" so you can't do it wrong way. Regarding outdated tutorials -> sometimes it happens. Regarding poorly integrated and buggy tools -> Very ,very rare if you have correct buffered JTAG chain. Currently I have 10 FPGA's in chain and I can debug in HW all 10 NIOS at once ! JTag if is also fast in this case (USB based ) It's really nice solution. AdamArticle: 135630
"HT-Lab" <hans64@ht-lab.com> wrote in message news:b6EHk.21676$I31.1428@newsfe24.ams2... > > "Gary Pace" <abc@xyz.com> wrote in message > news:_uqdnVHyM7bGPnPVnZ2dnUVZ_tXinZ2d@comcast.com... >> Hello : >> >> I have been designing for FPGA's for a number of years and have completed >> a number of real-time control / signal processing / communication systems >> in Altera devices (up to about 100K LE's) all using schematic capture and >> Megawizard functions. >> >> I have had a quick try with VHDL on a couple of occasions, but just >> didn't get along with it - I also write a great deal of C/C++ code and >> design hardware (FPGA, DSP, Power Electronics) and found that I kept >> putting my software hat on whenever I use a text editor....getting old >> you see. >> >> Now I need to get up to speed on VHDL - implementing serial link >> protocols, finite state machines and such stuff as a schematic just isn't >> that smart, and I think the synthesis would be better with some form of >> HDL source. >> >> Can anybody recommend some classroom type training suitable for somebody >> who really doesn't need an introduction to FPGA's and digital design >> stuff, just VHDL ? >> >> I am thinking about this : >> http://www.trainingcity.com/course_outline_detail.asp?CourseID=3100 >> >> Anybody have experience with this course or this company ? >> >> Any suggestions would be appreciated. >> >> Gary >> > I would check out Jim Lewis' advance VHDL course at > http://www.synthworks.com/ > > Although I did not attend this course, I know that Jim is a VHDL guru and > he is one of the main drivers behind the VHDL-2008 standard. He wrote some > interesting papers on how to do advance verification (Transaction Level > Modelling, Constraint Random etc) using VHDL. > > Another course to check out is the advance VHDL course from Doulos. > http://www.doulos.com/content/training/advanced_vhdl_training.php > > Not sure about the US but in Europe they are the market leader. I have > enjoyed many of their courses and they are exceptionally good. > > Hans > www.ht-lab.com > > Thanks Hans - Yes, I saw the Doulos courses, but I guess my company would baulk at a trip to Europe. I'll look at the synthworks courses GaryArticle: 135631
I've just ordered my 1600 MIPS XMOS XC-1 design kit. The XMOS chips will replace DSPs and FPGAs in a lot of applications. I haven't been so excited about a new chip since the transputer came out. David May designed them both, of course. Leon leon355@btinternet.comArticle: 135632
On Oct 10, 8:25=A0am, "Saul Bernstein" <jiffyl...@freenet.de> wrote: [snip] > While we're at it, I've got another question concerning the power supply.= On > the ML510 eval platform Xilinx used seperate 1.0V supply modules for ever= y > MGT reference voltage input. That looks quite exaggerated to me. Is that = a > mandatory requirement? > > Saul > The eval board is somewhat overkill. The general rule is to place a filter from a clean 1.0V supply (not the Vccint supply) to each of the MGT blocks used. Unused MGT blocks also need to be powered, but don't require a filter. Also you should have two 1.2V supplies, one for the VTT pins and one for PLL supplies. Again every MGT VTT and PLL pin need a filter when used. My filters consist of a ferrite bead with about 220 Ohms at 100 MHz - BLM21PG221SN1 from Murata, and a 0.22 uF capacitor. I used 0508 low esr ceramics with leads on the long edges of the part, and two vias per pad. This may be overkill, but it didn't cost too much in board space and the results were good. Note that the V5 in the larger packages (which you must have if you've got 10 GTP's) have a lot of internal bypass caps, so you should have room for the MGT bypass given that the other supply high-frequency bypass is mostly in the BGA package. Regards, GaborArticle: 135633
"Gary Pace" <abc@xyz.com> wrote in message news:p9edna9s2OGPz3LVnZ2dnUVZ_uudnZ2d@comcast.com... > > "HT-Lab" <hans64@ht-lab.com> wrote in message > news:b6EHk.21676$I31.1428@newsfe24.ams2... >> >> "Gary Pace" <abc@xyz.com> wrote in message >> news:_uqdnVHyM7bGPnPVnZ2dnUVZ_tXinZ2d@comcast.com... ..snip >> >> > Thanks Hans - > Yes, I saw the Doulos courses, but I guess my company would baulk at a > trip > to Europe. > I'll look at the synthworks courses > Gary > Hi Gary, They also operate in the US, Regards, Hans. www.ht-lab.comArticle: 135634
Hi All,
After working almost an year in the ASIC field i am revisiting
the comp.arch.fpga. I am very nostalgic about this group as i was part
of it in my early career and it realy helped me a lot.
But the question i have is not exactly from the fpga domain. But
you experts must be knowing the answers. Can we get the format for the
"waveform generation language" or is it a protected secret. I searched
through the net but only got directions to the tools not the actual
format. Could you please help me out?
Regards
Sumesh V S
Article: 135635vssumesh wrote: > Hi All, > After working almost an year in the ASIC field i am revisiting > the comp.arch.fpga. I am very nostalgic about this group as i was part > of it in my early career and it realy helped me a lot. > But the question i have is not exactly from the fpga domain. But > you experts must be knowing the answers. Can we get the format for the > "waveform generation language" or is it a protected secret. I searched WGL is essentially a private standard. STIL is a public (IEEE) standard. Why do you want this information? Most modern ATPG tools can write patterns in WGL or STIL (at least 2 flavours of STIL). To process STIL files there are quite a number of commercial software. The STIL software LRM can be purchased from IEE as well. Most of the commercial tools that convert from ATPG tool formats to tester formats support both WGL and STIL. The actual specification for WGL is very complicated. Andy > through the net but only got directions to the tools not the actual > format. Could you please help me out? > Regards > Sumesh V SArticle: 135636
On Oct 10, 9:01=A0pm, Leon <leon...@btinternet.com> wrote: > I've just ordered my 1600 MIPS XMOS XC-1 design kit. > > The XMOS chips will replace DSPs and FPGAs in a lot of applications. > > I haven't been so excited about a new chip since the transputer came > out. David May designed them both, of course. > > Leon > leon...@btinternet.com Is the comparison with the Transputer supposed to imply this is a half thought out design with brain dead execution? :-\ SteveArticle: 135637
On 10 oct, 09:01, Leon <leon...@btinternet.com> wrote: > I've just ordered my 1600 MIPS XMOS XC-1 design kit. > > The XMOS chips will replace DSPs and FPGAs in a lot of applications. > > I haven't been so excited about a new chip since the transputer came > out. David May designed them both, of course. > > Leon > leon...@btinternet.com Don't be surprised if people are skeptical. Remember what happened to the company that made Field-programmable- object arrays?Article: 135638
Gary Pace wrote:
> I have had a quick try with VHDL on a couple of occasions, but just didn't
> get along with it - I also write a great deal of C/C++ code and design
> hardware (FPGA, DSP, Power Electronics) and found that I kept putting my
> software hat on whenever I use a text editor....getting old you see.
If you like writing C, you might consider vhdl descriptions using
single process entities.
It is possible to use variables, functions and procedures
and a C-like style for synthesis code.
Some examples:
http://mysite.verizon.net/miketreseler/
-- Mike Treseler
Article: 135639On 10 Oct, 17:42, ste...@coppice.org wrote: > On Oct 10, 9:01=A0pm, Leon <leon...@btinternet.com> wrote: > > > I've just ordered my 1600 MIPS XMOS XC-1 design kit. > > > The XMOS chips will replace DSPs and FPGAs in a lot of applications. > > > I haven't been so excited about a new chip since the transputer came > > out. David May designed them both, of course. > > > Leon > > leon...@btinternet.com > > Is the comparison with the Transputer supposed to imply this is a half > thought out design with brain dead execution? :-\ > > Steve The transputer was ahead of its time, and really pushed the technology that was available. I sold a lot of systems using it, mostly to universities and research establishments, because there was nothing else around with that sort of performance then. Inmos even had their own fab! LeonArticle: 135640
On 10 Oct, 18:11, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > On 10 oct, 09:01, Leon <leon...@btinternet.com> wrote: > > > I've just ordered my 1600 MIPS XMOS XC-1 design kit. > > > The XMOS chips will replace DSPs and FPGAs in a lot of applications. > > > I haven't been so excited about a new chip since the transputer came > > out. David May designed them both, of course. > > > Leon > > leon...@btinternet.com > > Don't be surprised if people are skeptical. > > Remember what happened to the company that made Field-programmable- > object arrays? These are processors, not FPGAs. LeonArticle: 135641
FreeWheel wrote: > Hi everybody, > > First off all...sorry for cross posting this to both arch.fpga and > arch.embedded, but I think it fits in both places. > > I'm currently in the selection fase of an FPGA vendor. we need a >2M > gate chip with DSP capabilities, SERDES and offcourse the mandatory > low cost. Likewise we need a high performance embedded CPU softcore > for system management. Why does this need to be on the FPGA ? SoftCPUs still need external memory, so are a 2-3 chip solution. Why not use a 32 bit microcontroller, with on chip FLASH ? (it may allow smaller FPGA, or smaller Loader/RAM resource) Some examples: * Infineon have 32bit uC models with Error Correcting FLASH * NXP claims : "At 125 MHz, the NXP LPC2900 series are the fastest ARM968 microcontrollers available on the market," * Atmel's claim 200MHz peak core for their AT91SAM9XE128 with a ARM926EJ-S core ( 15ns memory bandwidth @ 32 bits) * NXP have 100MHz cM3-R2 devices and you get SSI/SPI/ADC/DAC/Timers/RTC/WDOG/Low power, and in some cases USB/CAN/Ethernet > My conclusions on the > Lattice tool chain and the Mico32 system based on the evaluation is as > follows: In the timeline of such things, the Lattice solution is relatively new, so it is expected to have more wrinkles than a more mature system. Have you asked Lattice for a reference design closest to what you are trying to do ? -jgArticle: 135642
Hi MMJ, > * Some stuff will > never work if you don't reverse engineer HW or get correct support. What specifically isn't working? Did you contact Lattice about it? > * Poorly integrated and bugy tools. What problems and bugs do you have? Are they with the IDE, the GNU tools or are you talking about the FPGA tools? > * Tools crashes Ditto. > * Any ways (known fixes to issues, third party stuff etc.) to get > faster to market with the Lattice solution? If you say what the specific bugs are, maybe I can offer some help or advice. > * Is the stuff (NIOS II and tools) from Altera (or any other vendor) > any better regarding the complaints above? MicroBlaze and NIOS II have been around for longer and no doubt have a larger user base, but they are not without their own problems. Don't forget that much of the toolchain is pretty much the same s/w. > * The Mico32 is open source but is the origin of the code made by > Lattice themselves or? It's a mixture. The IDE & toolchain are obviously based on other open source projects (Eclipse / GCC / binutils / GDB), but the Mico32 architecture was designed & implemented by Lattice. Cheers, JonArticle: 135643
Saul Bernstein wrote: > Alright then.7 DUALs means 7 RocketIOs with both RX and TX connected, i.e. > 14 lanes? In my application I'd like to have 10 MGTs (both RX + TX) running > at 3.125 Gbps, 4 running at 5 Gbps, 2 at 4.25 Gbps and another 4 running at > 2.5 Gbps. Which RocketIOs would you recommend to combine, relating to a > shared reference MGTCLK input? > > While we're at it, I've got another question concerning the power supply. On > the ML510 eval platform Xilinx used seperate 1.0V supply modules for every > MGT reference voltage input. That looks quite exaggerated to me. Is that a > mandatory requirement? > > Saul > > > > "Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag > news:_MrHk.2845$as4.166@nlpi069.nbdc.sbc.com... >> Saul Bernstein wrote: >>> Same problem - still much worse - with the RocketIO reference clocks! >>> Plenty of clock inputs but. much too confusing! For example I'd like to >>> take one reference clock for an arrangement of 10 RocketIOs. No problem >>> with Virtex-II pro, no problem with Virtex-4, big problem with Virtex-5 >>> for the clocks can only supply 4 RocketIOs at once... as far as I can >>> judge. >>> >> The Virtex-5 MGT REFCLK inputs can span up and down 3 of the GTP_DUAL or >> GTX_DUAL sites, so you can reach 7 DUALs or 14 lanes. >> >> Ed McGettigan >> -- >> Xilinx Inc. > > A GTP_DUAL site in Virtex-5 is the equivalent of 2 MGTs in the V-II Pro and V-4 FX families, so 7 GTP_DUALs is 14 MGTs, 4 more than you need. Any 5 adjacent GTP_DUALs will meet your needs and use the REFCLK in on the sites in the middle so that you don't violate the +/- 3 GTP_DUAL requirement. The ML510 does not have separate power supplies for each GTP_DUAL, but it does have separate power supplies for each voltage rail, AVCC AVCC_PLL, AVCC, AVTT_TX and AVTT_RX. We did it this way so that we could margin the voltage rails independently if there was a need. Ed McGettigan -- Xilinx Inc.Article: 135644
Gang I'm looking for a simple 32bit softcore processor in VHDL. I dont need a cache or and MMU. I do need interrupts. I also need software tools for the processors. I am happy to program in assembler, a C compiler is a bonus. Any ideas? BobArticle: 135645
Hi Andy,
You mean i need to spend money to get the details?? My intention
is to debugg a bus contention issue. Fast scan gave me a wgl file and
we have our internal tool which converted it and and ported it into
verilog. But that verilog test bench is driving the values where it
should not be. Thus i wanted to know whether it happend from the
fastscan or is it a bug in the conversion tool. Thus i need to
understand the wgl format.
Thanks andy for your reply
Regards
Sumesh v S
Article: 135646On Oct 6, 1:03=A0pm, Allan Herriman <allanherri...@hotmail.com> wrote: > Ali <ali.ar...@gmail.com> wrote in news:e3ebcf87-0420-443e-9f57- > 8318c1fd0...@y29g2000hsf.googlegroups.com: > > > I have a specific query regarding the usage of SelectIO/RocketIO > > SERDES features available in Vertex 4. I want to implement OTU2 with > > Virtex 4 and I wonder if this possible that use RocketIO .What I have > > understood that these features are mainly applicable for high speed > > serial communication protocols like PCI express, SATA etc. They also > > have some special hardware features like 8B/10B encoding/decoding > > logic built into the device for specific high speed serial > > communication applications. > > In my application, I need to add FEC data to STM64 and generate G.709 > > OTU2 data format. > > None of the built-in features will help you with STM64 or OTU2. =A0You'll > have to roll your own framers, etc. using the FPGA fabric. =A0This is not= a > difficult task, since the functions are reasonably well specified. > > I would feel uncomfortable even thinking about trying to meet the various > jitter requirements at 10Gb/s using an on-board SERDES. =A0You might be > better off using an external SERDES made by AMCC, PMC-Sierra, etc. =A0The= se > will typically have a 16 bit LVDS interface to your FPGA. =A0You still ne= ed > to do your own framers, FEC, etc. > > Regards, > Allan Dear Allan Many Thanks for your help. We have two solutions to implement OTU2 frames. In first ASIC solution, we utilize AMCC S3092, S19203 and S3091. For complete assurance, simultaneously, we pursue implement OTU2 frame with FPGA, but the main concerns are finding suitable SERDES and overcoming jitter. Do you think that AMCC SERDES like S3092 works properly with Virtex 4/5 or do you suggest examining another ASIC solution like Broadcom BCM8512. Regards, AliArticle: 135647
vssumesh wrote: > Hi Andy, > You mean i need to spend money to get the details?? My intention To get language details yes. To fix a bus contention issue probably not. > is to debugg a bus contention issue. Fast scan gave me a wgl file and > we have our internal tool which converted it and and ported it into > verilog. But that verilog test bench is driving the values where it The WGL timeplate controls the timing. It does not explicitly say stop driving at this time. > should not be. Thus i wanted to know whether it happend from the > fastscan or is it a bug in the conversion tool. Thus i need to FASTSCAN can write out a testbench and stimulus for your patterns. From memory it is the -verilog qualifier on the save patterns command. Try this and report back. Are you having problems during the shift cycle or the load_unload cycle. > understand the wgl format. > Thanks andy for your reply > Regards > Sumesh v SArticle: 135648
On 11 Oct, 06:00, bzigon <bob.zi...@gmail.com> wrote: > Gang > > I'm looking for a simple 32bit softcore processor in VHDL. I dont need > a cache or > and MMU. I do need interrupts. I also need software tools for the > processors. > I am happy to program in assembler, a C compiler is a bonus. > > Any ideas? > > Bob LEON or MicroBlaze. Maybe you can find a Verilog to VHDL converter and then use Mico32 or OR1200. JonArticle: 135649
"bzigon" <bob.zigon@gmail.com> wrote in message news:62c7a069-d995-415b-a77e-4e0c87cb7e2f@x41g2000hsb.googlegroups.com... > Gang > > I'm looking for a simple 32bit softcore processor in VHDL. I dont need > a cache or > and MMU. I do need interrupts. I also need software tools for the > processors. > I am happy to program in assembler, a C compiler is a bonus. > > Any ideas? > > Bob Google? Why 32bits? Opencores http://www.opencores.org/browse.cgi/filter/category_microprocessor Hans www.ht-lab.com
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Compare FPGA features and resources
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