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Sorry it's "Renesas" now.Article: 102126
c d saunter wrote: > =?ISO-8859-1?Q?Michael_Sch=F6berl?= (MSchoeberl@mailtonne.de) wrote: > > : Do you say that this would still run at full speed? > : has anyone tried this? > No reason to try it myself, also the cost of VM servers used to be prohibitive for play use but the VMWare scene has changed alot with free guest VMs. > : I suspect the emulation takes quite some ressources ... > > Running an x86 virtual PC on an x86 host can use virtualization where most > code (non priveledged stuff etc.) runs nativly, so there is a much less > significant performance hit than with emulation. > > You need a lot of memory though as both the host and guest OS' memory > requirements must be fulfilled. > I wonder if there would be some advantage to running Windows Vm boxes on Linux rather than on WIndows host, or vice versa for memory advantages or to satisfy OS preference while using EDA tool with the vendor supported OS. > Also the old tools will have been used with older, slower PCs so will get > a speed bost from the modern PC which probably offsets the virtualization > overhead. > > Where the VM aproach falls down is where you have software that is locked > to some physical dongle... > Indeed but I am sure that other VM users must be using protected software licenses too so same solution at hand, probably network license. Still its more work to insert another layer. FWIW alot of VM issues get discussed on OSNews since all the vendors are constantly in the news. > cdsArticle: 102127
Antti Lukats wrote: > > Maybe I should buy speakers and hear the audio of the webcast also :) yes :) IIRC, one of the questions was about SDIO, so you could email Jesse Jenkins and ask him. He did say to email any followups... -jgArticle: 102128
I forgot to add this. I have a root file system created by using the "klingauf" mkrootfs script. I placed the root file system on my linux host at /opt/ml300_rootfs. In the kernel .config file i made using make menuconfig, i included the following config cmd line in the "General Setup" section CONFIG_CMDLINE="console=ttyS0,38400 root=/dev/nfs nfsaddrs= 192.168.1.10:192.168.1.5:192.168.1.1:255.255.255.0 rw nfsroot=/opt/ml300_rootfs " I used the compact flash to boot the kernel . The kernel boots prperly. but then the error given above comes in.Article: 102129
In article <1146246311.256472.241490@j73g2000cwa.googlegroups.com>, JJ <johnjakson@gmail.com> wrote: >In comp.arch (and others) there is a thread on this Opteron Virtex4 >coprocessor that sits in socket 940. Here's a similar product from another company, using Altera's Stratix II: http://www.xtremedatainc.com/Products.html -- oleg | The "From" address is temporary. @ | <---- If expired, use this one. sashos | .com | "Can you count to 1023 on your fingers?"Article: 102130
Antti wrote: > easier ride? how much easier? As I said: >> If you're doing windows and need a 'grass-roots' high performance >> driver, prepare yourself for a frustrating and challenging time. > PS actually linux device drivers are fun, I agree, but quick dirty > direct hardware programming on WinXP is simple as well. There's several options these days to make life a lot easier on Windows, for example the Jungo tools, TVICPCI etc. But to some extent it depends on what type of driver you're writing, what performance you need, and what versions of windows you need to support. A big part of the time/effort is simply ramping up on windows device drivers - working out what *type* of driver you need to write (is it WDM? native kernel mode? VxD? upper/lower filter? HID?) - sometimes you even need 2 drivers! - and how it fits into the whole mess. Years and years ago I spent *months* writing a SCSI miniport driver for 95/NT4/2K, which included support calls to M$. Once I'd finished, it took me 3 days get a basic port running on Linux, and I'd *never* written a Linux device driver before. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 102131
I believe the cross-overs would be something like this, although I could be mistaken. CoolRunnerII - MAXII Plus Spartan3/3e - Cyclone/CycloneII VirtexII - Stratix/StratixII I've used both the Virtex II Pro and the Stratix Series devices, and for any of my applications both would have worked. Each mfg has different strengths in each category; but I haven't found (doesn't mean there isn't) any one convincing spec that puts one so much above the other. There have been past posts (ad nauseam) dealing with the topic of whose FPGA rules the world. Some of it is pride, some ignorance, some just marketing magic. Bottom line is both can probably get you where you want to go. I primarily use Altera because the company I work for happened to choose them as a preferred vendor. Our typical applications deal with video processing, and either mfg can doubtless play strong in this arena. The MAXII Plus devices can be clocked at impressive speeds for a PLD, and quite inexpensive in quantity. Rob "Eli Hughes" <emh203@psu.edu> wrote in message news:e3so95$1e3o$1@f04n12.cac.psu.edu... >I have a question for those experienced with Altera devices. Could someone >please identify (roughly) the Brand A equivilents of these brand X parts: > > CoolRunner II > Spartan 3/3e > Virtex II > > I am not trying to be a flame baiter, but I would really like to hear > other people's thoughts of Altera's equivlents. I used to use the Altera > CPLD (MAX7000) a long time ago and had a good experience. What are the > FPGA devices like. > > > Thanks again. > -EliArticle: 102132
Thanks to those who replied. I'll post the results on how the transition went. Keith "Keith Williams" <e_s_p_i_a_n_@insightbb.com> wrote in message news:gMadnZ4JxuPC-fzZnZ2dnUVZ_smdnZ2d@insightbb.com... > I have a fairly large Altera-based design that will soon be updated to > Cyclone II and Quartus (from Flex10K and Max+II). > > Has anyone else been through this migration that would be willing to share > any gotchas? Is the migration tool in Quartus worthwhile? > > Thanks, > > Keith > >Article: 102133
Hi, I am using a DCM in VirtexII which takes a 20 Mhz input and generates a 60 Mhz output. I am synthesizing using Synplify Pro and using Xilinx ISE 7.1 for PAR. After PAR, I am getting a warning that the CLKO output from the DCM is less than 24 MHz. I know that the min. output freq. from the DCM should be 24 Mhz. In my case, I am getting a 60 MHz output from the CLKFX pin of the DCM and I am not using the CLKO pin. So, I would like to know whether this warning will create some problem in the timing of the clocks in the design. Thanks & Regards, Srini.Article: 102134
is it easy to reverse engineer ASIC/FPGA ? do u have any reference for this ?Article: 102135
Jesse did answer Antti provtely vi e-mail. PeterArticle: 102136
That's a different issue. Let's back up a little. You have an event, which you want to create an interrupt. And this event may be announced by a noisy signal. If you have a "master clock" (you should) then the 1st thing to do is synchronize the signal with to the clock. (This is good practice for any signal.) There are dozens of ways of removing noise from a signal. Debouncing is one way, and ony way to debounce is clocked sampling.Article: 102137
The issue boils down to response time. If you can wait, then you can filter out all sorts of noise. If you are in a hurry, then you cannot tolerate too much noise. If you have lots of noise, and want to react immediately, then you have a real problem... Peter Alfke, Xilinx ApplicationsArticle: 102138
Just ignore the warning. You cannot use CLK0, but you are using CLKFX, and you specified multiply by 3 and divide by 1. Sometimes these warnings are over-eager... Peter AlfkeArticle: 102139
binaryboy wrote: > is it easy to reverse engineer ASIC/FPGA ? > do u have any reference for this ? Easy is VERY relative to ones experience and resources. The straight forward answer is that it's probably very very hard for you since you are asking. For most mortals ASICs are also very very hard as well, and relatively easy for those that do it every day for a living (requires some signficant investments in equipment and training). FPGAs with built in crypto are a little tougher nut to crack, but far easier than ASICs .... still takes some special equipment but far less work. Standard FPGA bitstreams for most FPGAs requires a two step process, first finding the map for the device (which may require reverse engineering some vendor tools first) then writing a netlist generator using the map from the bitstream. This requires the least skill, and can be done by most mortals that understand programming at an undergraduate level and basic FPGA architecture in somewhere between a few weeks to a few months for someone fairly bright and skilled, a bit longer if they have a difficult time playing deductive reasoning games or lack programming experience. Turning the extracted netlist into a usable readable design for modification or clean room specification is fairly linear in time by it size ... which can be significantly reduced if your reverse engineering tools can "reverse compile" the netlist into a higher level form, such as good high level VHDL/Verilog or C. There are professionals that do reverse engineering for a living ... we find that the experience from each project greatly helps develop the skills/experience for the next. You might find boomerang on sf.net interesting ... binary ISA streams are about the same difficulty as unencrypted bitstreams, with the minor twist that most FPGA bit streams are undocumented, forcing a two step learning curve.Article: 102140
hello:
I have a small count design, which I want to do functional simlation
in modelsim. the code are following;
module count4(cnt,clk)
output [3:0] cnt;
input clk;
reg [3:0] cnt;
always@(posedge clk)
cnt = cnt +1;
endmodule
This is just a 4 bits simple counter design. and I do not have the
reset signal in it.(just for test).
you see that the modelsim treat "cnt" as x at initial time, so the
result can not be right.
So I want to modify the cnt signal in testbench, I done as follows:
initial
force cnt = 0;
#500 release cnt;
and the clk is 100.
but the reesult is not right either.
My question is : How can I make the cnt to be a specific value in
testbench?
just not using the reset or preset, thanks.
Article: 102141hi : I got another problem. I want to see the internal signal inside a design but the result is not waht i want . I just simulate a distributed selectRAM generated in ISE. And I want to see the signal before reaching the output pads of the viretex II fpga.i.e. just the right output port of the distributed selectRAM. I found these net names in fpga editor and add them to modelsim waves, just to find that they are the same with the output port of the IO pin. Are they should be the same? I just want to see the timing excluding the IOB delay. I hope I explain my problem clearly. thanks everybody.Article: 102142
On Tue, 09 May 2006 23:43:38 +0930, Sanka Piyaratna <jayasanka.piyaratna@gmail.com> wrote: >Hi, > >I am wondering if there is anyone who has worked out a way to use ISE >8.1 projects with Makefiles to compile FPGA images. I am actually >wondering if it would be possible to automatically generate a Makefile >from the project file. > FYI: Taking a look inside an .ise file, I think it is a sequence of FIP files concatenated. If you break the ISE file into lots of smaller files (dividing them by the "PK" flags), you will get lots of zip files whose contents may be peeked with a zip file extractor Best regards, ZaraArticle: 102143
I have one model in which i have sampled interrupt on main clock on both the edges and if the both edged samples match, i take them grated and proceed to initiate action. It gave me some noise immunity. (>2*Fclk) Actually these are related to Power failure and critical fault conditions, when asserted will call for complete system switchover , the criticality is what matters here. Just wanted to know is it a better practice to sample int on 'posedge' and 'negedge' and 'AND' them to get that noise immunity. Thanks you for your inputs.Article: 102144
Ashish wrote: > Hi, > > What is the fair criteria for sampling the interrupt signal? > > For high priority critical interrupts and low priority interrupts, when > should i decide to configure them to be level triggered or edge > triggered. If this is an external signal, one thing to watch on level iterrupts, is you need to wait for the line to release, before re-enable of the interrupt - otherwise you simply re-enter the interrupt again. -jgArticle: 102145
Hi, Was wondering if anyone has used the XCFxxP devices with revision selection controlled via the internal REVSEL bits rather than the external REVSEL pins? I'm assuming the REVSEL bits are, once programmed, persistent (non-volatile), yes? Is it possible to re-write the REVSEL bits without having to download a new bitstream as well? Finally, can anyone see a problem with the FPGA bit-bashing the JTAG on the PROMs to re-program both bitstreams and REVSEL bit settings? And what about the FPGA sending the CONFIG command to the PROM to initiate a re-configuration of itself? TIA Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 102146
Mark McDougall wrote: > Finally, can anyone see a problem with the FPGA bit-bashing the JTAG on > the PROMs to re-program both bitstreams and REVSEL bit settings? And > what about the FPGA sending the CONFIG command to the PROM to initiate a > re-configuration of itself? I haven't used any of the revsel features, so I can't answer that part, but I have used the config command to re-config an fpga (where I forgot to connect the prog line) and it works just fine. But I think it would be better to use the prog line to initiate re-config. Alan NishiokaArticle: 102147
Alan Nishioka wrote: > I haven't used any of the revsel features, so I can't answer that > part, but I have used the config command to re-config an fpga (where > I forgot to connect the prog line) and it works just fine. CONFIG was sent from/via the FPGA itself? > But I think it would be better to use the prog line to initiate > re-config. Momentarily forgot about that option - thanks! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 102148
How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? The signals a and b are 32 bit signed fix point numbers (std_logic_vector (31 downto 0)).Article: 102149
Hi A design engineer asked me if it should be ok to have an 1-bit GPIO in MicroBlaze design, well yes I answered - after a short while. But I am trying to use a single bit GPIO instance to capture the PENIRQ signal from Analog Devices touch screen digitizer and well it all doesnt seem to work. Ok, make then then GPIO port 2 bit wide and use only one? That was yesterday. This morning I looked at the oscillocope capture of the pulse on the PENIRQ - active low level was above 2 Volt. Signal coming directly from Evaluation Board from Analog Devices, FPGA disconnected from the signal! Let me see the eval board schematics! Schematic shows 50K pullup on PENIRQ and no other connections. I guess its fitted with 50ohm I say. (assuming the SMD assembly guy at Analog Devices messed up). No I dont belive this, sure the board has passed testing at Analog Devices, see here is a even label: "Test passed"! Well lets measure! And exactly 50ohm it was! Not even a SMD but old style through hole resistor! Sure a 50 ohm pullup on output specified for 10k-100k pullup would disable the low level driving capability. Why I am writing this to the newsgroup? To give some earned credit to Xilinx - if there are more critical posts about Xilinx chips or software, then it actually means there is huge useage of them, and as we know things happen. So more (angry) posts means more users, not that there is a reason to be angry. Less posts doesnt mean better products or services, just less users. It doesnt mean that I am completly happy with Xilinx software, but OTOH I am not easy to please on tech matters. Would I have posted yesterday, I could have been angry to EDK that doesnt properly implement a GPIO with 1 bit width. Today the situation is different, the issue is not with EDK at all. Hope this 1-bit resistor story triggered a few smiles today :) Antti Lukats
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