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srini, See below, Austin srini wrote: > Hi, > I am using the VirtexII DCM in my design to generate the master clock > for all the modules in my design. The input freq is 20.48 MHz and the > output freq from DCM is 61.44 MHz. The "LOCKED" signal from DCM is > AND'ed with the system reset and given as reset to all the modules in > the design. Make sure that you do not connect anything to CLKFB, CLK0/90/180/270/2X, 2X_b, and CLKDV (these are all DLL outputs and input, and if the DLL is used with the DFS, 20.48 is too low a frequency and it will never lock). > When I generate the DCM using Coregen, there is a option "wait for DCM > lock before DONE signal goes high" when I click the "Advanced" button. This allows the DCM to lock before allowing DONE to go high: do not use it. Rather, it is safer to reset the DCM when you know the input clock is good, and stable. > Can anyone clarify me what will happen if I dont check this option ? DONE goes high without checking that the DCM is locked. > Will it affect the startup operation or the functioning of the FPGA > after startup? Yes. With it checked, the DCM is locked when DONE goes high. Without it, the state of the DCM is under your control. What is the significance of this option? If your clock input to the DCM is always stable, and the CLKFB (if used as a DLL) does not come from an external source, this option is a convenient way to start up the DCM, and never use the RESET to the DCM (simplest mode). It is fraught with difficulties in the real world, as guaranteeing the clocks are good before DONE goes high is not possible in most circumstances. Rather, do not wait for LOCKED before DONE, and instantiate a SRL16 clocked by CLKIN so that when the device DONE goes high, a '1' is shifted into the SRL16 whose output drives the RESET input of the DCM (and also goes back and sends a '0' into the SRL16). This clever shift register reset circuit then clocks 16 times till a 1 comes out which resets the DCM, and then 16 clocks later, reset goes to a '0' again. At that point, LOCKED will go high when the DCM locks, and that should gate all your logic to start up (go to state 0, reset or enable your logic, etc.). I think it is better you trust your own design, and be in control of it, rather than use the "must lock before DONE goes high" backwards compatible feature (this feature was originally in the original first Virtex - which is 7 years old now).Article: 103151
Good luck, everyone! If you fix this without side effects, I would love to see an answer. I believe the problem arises when the two clocks are related and the Xilinx timing tool figures this out. It tracks the clocks from the same DCM and says "aha!, a relationship!" and then does the timing analysis. Telling the user to ignore timing errors is silly. Now I have to peruse the timing report manually each time to be sure the errors are ones I can ignore, or write some complicated script to do it for me. Yes, you can use TIGs, but my experience is weird things happen when you use to many of these. But then, weird things seem to happen in Xilinx timing on complex designs routinely anyway so maybe that doesn't mean anything. Am I a bit frustrated? Yes. I've been fighting these kind of issues in a Virtex 2vp30 design with 99% of slices (but only 60% of LUTs) used for months. Seems like the timing tool should also be smart enough to say "Aha! Coregen version of asynchronous fifo, let's be careful about some paths." On Wed, 24 May 2006 14:30:43 +0100, Ben Jones wrote: > Hi Falk, > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:4dj434F1avlqmU1@individual.net... >> rob.misc@gmail.com schrieb: >> > Thanks, I TIG'ed those nets, but unfortunately some new ones in the >> > FIFOs then had the same issue. I will have to figure out why ISE is >> > confused. >> >> It there somewhere an option to disable cross clock domian timing >> analysis? AFAIK there is such an option in Alteras Quartus-II Software. >> But ISE from Xilinx?? > > The Xilinx timing analyser only examines paths which are constrained, so the > problem here is (I think) that a spurious constraint has found its way into > the system. Usually the constraints are either user-entered or generated by > the synthesis tool (and then used as a guide by the subsequent mapping, > placement and routing stages). > > XST has an option to ignore paths between different clock domains for > timing, and not create constraints based on its analysis of such paths. > > In this case, the paths are within a FIFO module generated from Coregen. It > sounds to me like these constraints have been written out by coregen (into > the .ngc netlist, probably), when they're actually unnecessary. The > workaround is to TIG these paths manually; the solution is to get the IP > fixed so these spurious constraints are not propagated into the design in > the first place. > > Cheers, > > -Ben-Article: 103152
Terry Brown wrote: > Seems like the timing tool should also be smart enough to say "Aha! > Coregen version of asynchronous fifo, let's be careful about some paths." Does your fifo have to be asynchronous? -- Mike TreselerArticle: 103153
>> What did you mean by "which comes with the NiosII processor already in it"? > As soon as you plug the device to power, it configures itself as a nios > processor. this is also confirmed by the nios manual which comes with > the board. >> If so, then the FPGA configuration is controlled by a small CPLD. When the >> board boots up I think this looks for the presence of several images in flash, >> picks one then configures the FPGA. > This seems like what's happening. the safe mode led is on, btw. >> You need to add an output to your design (call it anything you want), set it high >> and assign it to the correct pin. On the CycloneII board with the EP2C35 it's >> pin AA14. >> > I am using a Cyclone EP1C20 chip and not EP2C35 and I couldn't find > where the reconfig_req is located in it. i have the pin list for that > device, but I must say that I am not familiar with most of the acronyms > used there. the previous device I used to work with was a Flex10k and > it was way lot simpler to locate what I needed there. > could you help me with the pin number that should be driven high in my > design? There's no FPGA pin called reconfigreq_n, it's a net on the board that goes from the FPGA to the config device. From the Cyclone schematics I've got on this PC with the EP1C20 it might be connected to pin V8. Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 103154
All, I am getting all the details of what we send, and what control the customer has. The only information we are sending back is the design summary about how many different types of resources are being used by the design - things like how many blkrams are used and in which modes. The user is asked before the data is send back to Xilinx and there is an easy way for the user to opt out of it. More details to follow. AustinArticle: 103155
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:4doltgF1b2to0U1@individual.net... > > > There's no FPGA pin called reconfigreq_n, it's a net on the board that > goes > from the FPGA to the config device. > > From the Cyclone schematics I've got on this PC with the EP1C20 it might > be connected to pin V8. > Correct, pld_reconfigreq_n <='1'; Quartus <design>.csv file: pld_reconfigreq_n,PIN_V8,4,LVTTL,Column I/O,LVDS119p,,,,, Hans www.ht-lab.comArticle: 103156
Ray Andraka wrote: > John, no I haven't found a way to do this for inferred LUTs without > making them a separate entity. If you keep your logic to 4 inputs, then > the PAR software will generally place the LUT with the flip-flop, so you > can usually get away with just placing the flip-flop and letting the > inferred LUT follow it. For my commonly used IP blocks, I have a > library of lut functions, each in its own entity. Synplicity lets you > put an xc_map=LUT property on it that makes it into a LUT component. For > example: > > --FMAP'd or2 > library IEEE; > use IEEE.std_logic_1164.all; > > entity fmap_or2 is > port ( a, b : in std_logic; > z : out std_logic); > end fmap_or2; > architecture rtl of fmap_or2 is > attribute xc_map : STRING; > attribute xc_map of rtl : architecture is "lut"; > attribute syn_hier: string; > attribute syn_hier of rtl:architecture is "hard"; > begin > z <= a or b; > end rtl; > > produces a 2 input OR in a LUT. You can put an RLOC on the > instantiation of this component, and it passes through the tools > properly so that it winds up being a placed LUT. > > It obviously isn't as clean as putting z <= a or b; inline in your > code, but it is still an RTL inference. Hope this helps. Thanks, Ray. I've been instantiating LUT4 primitives and INITing the LUTs with the appropriate equations. Maybe I can get creative and figure a way to get the xc_map=lut attribute to parameterize well in Verilog. I appreciate the help, - John_HArticle: 103157
I have a design from ISE that I have been trying to create a peripheral out of. I have created peripherals before using the wizard, but all the logic was directly implemented in the user_logic.v stub that is provided. This time I have a few files that comprise my design and don't want to/can't implement everything in user_logic.v. I was able to use the ISE project that is created with the peripheral (via the wizard) to implement my design. Essentially brought copies of my already completed .v files to this new project and instantiated what I needed into user_logic.v. I was then able to successfully synthesize the design in that ISE project. Now when I try and use that IP in a system in XPS, synthesis fails because the module I instantiate in user_logic.v can't be found. I have looked for documentation on how to do this properly, but everything I have seen assumes everything the user adds is contained completely in user_logic.v. I have looked at all the .prj files and tried to manipulate those with no luck--synthesis fails the same way each time. Am I missing something obvious? Has anyone done what I am describing? Any pointers to documentation on this? I can provide more info if it helps... Any help/advice appreciated, Thanks, JoeyArticle: 103158
Hi Joseph, Look in: peripheral repository/my_peripheral/data/my_peripheral.mpd for I/O peripheral declaration and in peripheral repository/my_peripheral/data/my_peripheral.pao for correct file linking (that's what you are probably looking for) Have fun, GuruArticle: 103159
You should about the PAO syntax. This defines the set of files used for synthesis in the EDK world. It's just point of organizing your files in the EDK directory structure and using the PAO to list the files in use. Joseph wrote: > I have a design from ISE that I have been trying to create a peripheral > out of. I have created peripherals before using the wizard, but all > the logic was directly implemented in the user_logic.v stub that is > provided. This time I have a few files that comprise my design and > don't want to/can't implement everything in user_logic.v. I was able > to use the ISE project that is created with the peripheral (via the > wizard) to implement my design. Essentially brought copies of my > already completed .v files to this new project and instantiated what I > needed into user_logic.v. I was then able to successfully synthesize > the design in that ISE project. Now when I try and use that IP in a > system in XPS, synthesis fails because the module I instantiate in > user_logic.v can't be found. I have looked for documentation on how to > do this properly, but everything I have seen assumes everything the > user adds is contained completely in user_logic.v. I have looked at > all the .prj files and tried to manipulate those with no > luck--synthesis fails the same way each time. Am I missing something > obvious? Has anyone done what I am describing? Any pointers to > documentation on this? I can provide more info if it helps... > > Any help/advice appreciated, > Thanks, > Joey >Article: 103160
Thanks for the quick response, Guru. That .pao was what I needed. Synthesis gets further now and it moved me to a new error that I was sort of expecting. In my design I am using a coregen module (a block ram). What do I need to include (and where)? To get the IP design to synthesize before (in the provided ISE project template), all I did was add the .xco file I had to the new project and that was enough to get things to work. The .pao seems only for HDL files... Thanks again for the help... JoeyArticle: 103161
More, The last posting is actually a new feature, that isn't out yet (sorry). So, the only information we plan on sending back is what I described below. The purpose of this is to see what people use, so that we make sure we provide the right resources for the right applications (research ). This is non-specific (we don't keep track of the 'who', just the 'what'). For this thread, the subject is (I believe) what happens presently when you click on the generated link for the error. So, this is called Error Navigation and searches the Answer Database for an Answer Record giving you more information on your ERROR or WARNING. Let me show you what is sent in Error Navigation. Let's say I run XST and get a warning in the ISE transcript window. The word WARNING will be blue and underlined indicating it's a URL. If I click on it, a browser opens and I find myself on support.xilinx.com on a google results page. Here's an example of the URL for the hyper link: http://xgoogle.xilinx.com/search?ie=UTF-8&client=xilinx&oe=UTF-8&output=xml_no_dtd&proxystylesheet=xilinx&site=AnswersDatabase_Errornav&requiredfields=status:active&filter=0&errornavquery=ERROR:HDLCompilers:26%20-%20%22%2Fhome%2Fkpatel%2Ftr&q=%22HDLCompilers%3A26%22&version=8.1i&build=I.27 Now if you break this URL down, you can see that part of the message includes a path, which is simply just the path to the source file with the error. Here's a typical example of what we send in an error nav to xgoogle.xilinx.com: ie=UTF-8 client=xilinx oe=UTF-8 output=xml_no_dtd proxystylesheet=xilinx site=AnswersDatabase_Errornav requiredfields=status:active filter=0 errornavquery=ERROR:HDLCompilers:26 - /home/austin/tracking.v q=HDLCompilers:26 version=8.1i build=I.27 If the customer is concerned that sensitive information was sent, it's because that sensitive information was stored in the path to the project and/or source file. Perhaps someone can suggest a better solution? All we are trying to do here is help. Austin Austin Lesea wrote: > All, > > I am getting all the details of what we send, and what control the > customer has. > > The only information we are sending back is the design summary about how > many different types of resources are being used by the design - things > like how many blkrams are used and in which modes. > > The user is asked before the data is send back to Xilinx and there is > an easy way for the user to opt out of it. > > More details to follow. > > AustinArticle: 103162
<http://www.andraka.com/files/crdcsrvy.pdf> kind regards, timArticle: 103163
All- On pg 498 of the 8.1i XST Users Guide, it says "Since initial blocks are ignored during synthesis...". But our FAE has sent Verilog examples showing initial block examples for RAMs, FSMs, and FFs, saying it's not just for simulation, but also used during synthesis. Can I ask Xilinx persons to confirm that XST 8.1 is doing this synthesis inside initial blocks, and this behavior isn't going to go away, even though it's not Verilog 2001 complaint? Steve (Knapp), can you help? Thanks. -JeffArticle: 103164
Henry Wong wrote: > alpha wrote: > > Uncle Noah wrote: > >> Xilinx block RAM is synchronous read. Is this the source of your > >> problem? > > > > [YES, design was based on Altera Apex chip when it got started. This is > > why I need a newer altera board. Too expensive. Does anyone know if > > there is any chance to borrow one form Altera ? :) ] > > > > As far as I know, the newer Altera chips also use synchronous RAM > blocks. (Input registers are mandatory, output registers are optional) [YES, Xilinx's sync read give me trouble.] Guys, Thank you all for the comment and concern on my processor. I will rework my ISA to a totally customed one, then open source to avoid any potential issue. My core has a very small and generic internal instructuction set(total 16). Each of them takes 3 source operands and one destination. Then all external instruction set will be mapped into the internal one by hardware (note: not microcode). I can modified the mapping logic to traget any ISA essentially (not x86). I can post all current supported instructions if anyone is interested in creating an ISA. My assembler is created by myself, It is easy to change it, just software thing.Article: 103165
Austing wrote: > errornavquery=ERROR:HDLCompilers:26 - /home/austin/tracking.v > q=HDLCompilers:26 > version=8.1i > build=I.27 > > If the customer is concerned that sensitive information was sent, it's > because that sensitive information was stored in the path to the project > and/or source file. > > Perhaps someone can suggest a better solution? All we are trying to do > here is help. Hi Austin, It's a tough one. For most people it doesn't matter, other than being a bit paranoid. I, and probably others, regularly work on projects which "don't exist", so any data collection for those projects is an unacceptable leak. Path names frequently disclose projects names, and file names frequently disclose intent. Even the data you do want to collect, regarding part usage, discloses what type and size part, all of which can inadvertently disclose the existance of an FPGA project (which doesn't exist) using certain parts, which for very strict non-disclosure projects would be an unacceptable breach. Even asking, is just asking a tech or QA or Build person to disclose information that they might not entirely aware is much more restricted that they expect .... IE the person that answers "yes" may not have the authority to do so. Lastly, it's probably best to clearly document other aspects, like web linked help, which will also disclose projects which don't exist, and allow the IT and Project admins to firewall all Xilinx access for those projects machines and developers. The old way of includeing doc's and error messages on the CD really is the correct way to do this.Article: 103166
In article <44755bcf$0$295$7a628cd7@news.club-internet.fr>, John@nospam.com says... > Thanks guys for these interesting posts... > > Why is ISA still out there ? Look at the PowerPC architecture, there's ISA > in it. Where? I certainly don't see it anywhere. <snip> -- KeithArticle: 103167
John_H wrote: > Ray Andraka wrote: > >> John, no I haven't found a way to do this for inferred LUTs without >> making them a separate entity. If you keep your logic to 4 inputs, >> then the PAR software will generally place the LUT with the flip-flop, >> so you can usually get away with just placing the flip-flop and >> letting the inferred LUT follow it. For my commonly used IP blocks, I >> have a library of lut functions, each in its own entity. Synplicity >> lets you put an xc_map=LUT property on it that makes it into a LUT >> component. For example: >> >> --FMAP'd or2 >> library IEEE; >> use IEEE.std_logic_1164.all; >> >> entity fmap_or2 is >> port ( a, b : in std_logic; >> z : out std_logic); >> end fmap_or2; >> architecture rtl of fmap_or2 is >> attribute xc_map : STRING; >> attribute xc_map of rtl : architecture is "lut"; >> attribute syn_hier: string; >> attribute syn_hier of rtl:architecture is "hard"; >> begin >> z <= a or b; >> end rtl; >> >> produces a 2 input OR in a LUT. You can put an RLOC on the >> instantiation of this component, and it passes through the tools >> properly so that it winds up being a placed LUT. >> >> It obviously isn't as clean as putting z <= a or b; inline in your >> code, but it is still an RTL inference. Hope this helps. > > > Thanks, Ray. > > I've been instantiating LUT4 primitives and INITing the LUTs with the > appropriate equations. Maybe I can get creative and figure a way to get > the xc_map=lut attribute to parameterize well in Verilog. > > I appreciate the help, > - John_H John, a long while back (>5 years), someone wrote a VHDL function and posted it here for creating the INITs for LUTs. As I recall, it accepted a boolean equation as a string for input and returned the hex string for the LUT init as the output. The advantage, of course, is that it makes your code a heck of a lot more readable and less error-prone. If you can't get the xc_map to work out for verilog (not sure how much good it does in verilog anyway because you can't generate the RLOC values with a verilog generate without some sort of pre-processor), then perhaps you can use a boolean equation to INIT string parser function to do that conversion. That is my back-up position should synplicity ever take away the xc_map attribute. I gotta say, instantiating LUTs and using the INITs directly is not a fun way to do any design. I guess you get pretty good at memorizing the hex strings for common function, but Oh, the pain!Article: 103168
I moved an EDK project I have from V8.1i back to V7.1i When I compiled my software, the elf was twice the size and overflowed the BRAM. I fixed the problem with the "-ffunction-sections -Wl,--gc-sections" options documented in Xilinx AnswerRecord 21533. But I found no references to a change of this sort from V7 -> V8. Is this to be expected? Anyone else notice this? It seems odd, given that the GNU compiler version is the same (3.4.1)Article: 103169
Hi Austin, maybe I am not parnoid enough to be seriously concerned about this filename-issue, but I still do not understand why Xilinx needs to filename to provide help about an error-message. However, I think it would be much more important to really get a useful help, mostly I get just some more or less unrelated links. (Your competition does a much better job here...). Thomas "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:e57gfi$8a76@xco-news.xilinx.com... > More, > > The last posting is actually a new feature, that isn't out yet (sorry). > > So, the only information we plan on sending back is what I described > below. The purpose of this is to see what people use, so that we make > sure we provide the right resources for the right applications (research > ). This is non-specific (we don't keep track of the 'who', just the > 'what'). > > For this thread, the subject is (I believe) what happens presently when > you click on the generated link for the error. > > So, this is called Error Navigation and searches the Answer Database for > an Answer Record giving you more information on your ERROR or WARNING. > > Let me show you what is sent in Error Navigation. > > Let's say I run XST and get a warning in the ISE transcript window. The > word WARNING will be blue and underlined indicating it's a URL. If I > click on it, a browser opens and I find myself on support.xilinx.com on > a google results page. Here's an example of the URL for the hyper link: > > http://xgoogle.xilinx.com/search?ie=UTF-8&client=xilinx&oe=UTF-8&output=xml_no_dtd&proxystylesheet=xilinx&site=AnswersDatabase_Errornav&requiredfields=status:active&filter=0&errornavquery=ERROR:HDLCompilers:26%20-%20%22%2Fhome%2Fkpatel%2Ftr&q=%22HDLCompilers%3A26%22&version=8.1i&build=I.27 > > Now if you break this URL down, you can see that part of the message > includes a path, which is simply just the path to the source file with > the error. Here's a typical example of what we send in an error nav to > xgoogle.xilinx.com: > > ie=UTF-8 > client=xilinx > oe=UTF-8 > output=xml_no_dtd > proxystylesheet=xilinx > site=AnswersDatabase_Errornav > requiredfields=status:active > filter=0 > errornavquery=ERROR:HDLCompilers:26 - /home/austin/tracking.v > q=HDLCompilers:26 > version=8.1i > build=I.27 > > If the customer is concerned that sensitive information was sent, it's > because that sensitive information was stored in the path to the project > and/or source file. > > Perhaps someone can suggest a better solution? All we are trying to do > here is help. > > Austin > > Austin Lesea wrote: >> All, >> >> I am getting all the details of what we send, and what control the >> customer has. >> >> The only information we are sending back is the design summary about how >> many different types of resources are being used by the design - things >> like how many blkrams are used and in which modes. >> >> The user is asked before the data is send back to Xilinx and there is >> an easy way for the user to opt out of it. >> >> More details to follow. >> >> AustinArticle: 103170
Hello everyone, I am in process of designing my own Spartan-3 board capable of running uClinux. On board, I have SDRAM, FLASH, ETHERNET and EXPANSION port with connection to free I/O pins on XC3S1000. Please, could anyone help me with implementation of TFT controller that will work with uClinux frame buffer driver. I tried to find it in EDK 8.1 but there is nothing in it, when I choose SPARTAN-3 and microblaze... I read one of the earlier posts (from antti lukats) that he succeeded to implement TFT on spartan-3 that will work under uClinux. Any one know something more about this? Thank you in advance Branko Karaklajic www.orpid.co.yuArticle: 103171
This was just posted in c.a.e, but could have potential for fast simulation times in FPGA developments ? :) I presume the delay-simulations are OK with single precision 32 bit floats ? PDF article: http://www.cs.berkeley.edu/%7Esamw/projects/cell/CF06.pdf web article: http://www.hpcwire.com/hpc/671376.html With these speeds, it also looks like a nice device to put alongside a FPGA.... -jgArticle: 103172
Austin Lesea wrote: > More, > > The last posting is actually a new feature, that isn't out yet (sorry). > > So, the only information we plan on sending back is what I described > below. The purpose of this is to see what people use, so that we make > sure we provide the right resources for the right applications (research > ). This is non-specific (we don't keep track of the 'who', just the > 'what'). > > For this thread, the subject is (I believe) what happens presently when > you click on the generated link for the error. > > So, this is called Error Navigation and searches the Answer Database for > an Answer Record giving you more information on your ERROR or WARNING. > > Let me show you what is sent in Error Navigation. > > Let's say I run XST and get a warning in the ISE transcript window. The > word WARNING will be blue and underlined indicating it's a URL. If I > click on it, a browser opens and I find myself on support.xilinx.com on > a google results page. Here's an example of the URL for the hyper link: > > http://xgoogle.xilinx.com/search?ie=UTF-8&client=xilinx&oe=UTF-8&output=xml_no_dtd&proxystylesheet=xilinx&site=AnswersDatabase_Errornav&requiredfields=status:active&filter=0&errornavquery=ERROR:HDLCompilers:26%20-%20%22%2Fhome%2Fkpatel%2Ftr&q=%22HDLCompilers%3A26%22&version=8.1i&build=I.27 > > Now if you break this URL down, you can see that part of the message > includes a path, which is simply just the path to the source file with > the error. Here's a typical example of what we send in an error nav to > xgoogle.xilinx.com: > > ie=UTF-8 > client=xilinx > oe=UTF-8 > output=xml_no_dtd > proxystylesheet=xilinx > site=AnswersDatabase_Errornav > requiredfields=status:active > filter=0 > errornavquery=ERROR:HDLCompilers:26 - /home/austin/tracking.v > q=HDLCompilers:26 > version=8.1i > build=I.27 > > If the customer is concerned that sensitive information was sent, it's > because that sensitive information was stored in the path to the project > and/or source file. > > Perhaps someone can suggest a better solution? All we are trying to do > here is help. > > Austin I'd suggest that there's no help provided by including the filename in the information sent back to Xilinx. The part of the tool that spits out the URL can simply strip the filename information. If there's a need to know filetype, my competitors won't care if I'm working in Verilog or VHDL so include filetype if desired. My opinion: it's bad form to include the filenames. Thanks for helping with the issue, Austin, - John_HArticle: 103173
Ray Andraka wrote: > John, a long while back (>5 years), someone wrote a VHDL function and > posted it here for creating the INITs for LUTs. As I recall, it > accepted a boolean equation as a string for input and returned the hex > string for the LUT init as the output. The advantage, of course, is > that it makes your code a heck of a lot more readable and less > error-prone. If you can't get the xc_map to work out for verilog (not > sure how much good it does in verilog anyway because you can't generate > the RLOC values with a verilog generate without some sort of > pre-processor), then perhaps you can use a boolean equation to INIT > string parser function to do that conversion. That is my back-up > position should synplicity ever take away the xc_map attribute. > > I gotta say, instantiating LUTs and using the INITs directly is not a > fun way to do any design. I guess you get pretty good at memorizing the > hex strings for common function, but Oh, the pain! I actually do things rather well with the existing INIT, I'd just like to do it cleaner. localparam I0 = 16'haaaa; localparam I1 = 16'hcccc; localparam I2 = 16'hf0f0; localparam I3 = 16'hff00; LUT3 #( .INIT( I0 & I1 | ~I0 & I2 ) ) MyMux( .O(Y), .I0(Sel), .I1(Ahi), .I2(Blo) ); I put the localparams at the head of the Verilog module I'm creating and the rest flows. I end up with 120 characters of width to instantiate a dozen LUTs each in a single line so it isn't as pretty a simple 4-input equation but it works. I can sometimes work it in for arrays of instances. Thank goodness I don't have to memorize the INIT tables. I just need to avoid using the conditional operator (I0 ? I1 : I2) because it's really 16 bit numbers in that init, not 1-bit ports. Using 16-bit numbers for the 8-bit INIT in the LUT3 example above is harmless with a simple truncation providing the functionality I need. I think I may have started that coding style after one of your posts about 3 years ago. I look forward to the far-off day when the primitive driving a wire is named after that wire in some predictable way. - John_HArticle: 103174
branek <orpid.yu@gmail.com> wrote: >I am in process of designing my own Spartan-3 board capable of running >uClinux. On board, I have SDRAM, FLASH, ETHERNET and EXPANSION port >with connection to free I/O pins on XC3S1000. >Please, could anyone help me with implementation of TFT controller that >will work with uClinux frame buffer driver. I tried to find it in EDK >8.1 but there is nothing in it, when I choose SPARTAN-3 and >microblaze... What TFT screen model do you use ..? Voltage level it requires ..? Data format ..?
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