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rickman wrote: > John_H wrote: > > "rickman" <gnuarm@gmail.com> wrote in message > > news:1158605643.208484.113710@m7g2000cwm.googlegroups.com... > > > > > > The pricing I have gotten on the ECP2 line is attractive, but in the > > > grand scheme of things I don't see where it is a significant difference > > > with the other players in the field. I think that optimizing any given > > > parameter in the FPGA market is a matter of timing. A couple of years > > > ago Spartan 3s were the low cost chips, then when the Cyclone II parts > > > came out they were a bit cheaper. Now that ECP2 parts are starting to > > > show, they will be cheaper... until the Spartan 4/5 parts make it to > > > the scene. > > > > > > If only there was something that actually distinguished the different > > > families of parts! > > > > > > The ECP2 line is nice but not terribly remarkable. > > > > The ECP2M parts, on the other hand, blow past the Brand A and Brand X > > low-cost offerings on memory to logic ratios *and* are the first low-cost > > devices to include SERDES functionality and at *very* attractive per-channel > > power levels. > > > > My attention was attracted to the offering because of the memory. Adding > > PCI express would be quite a bonus for me. > > Please don't get me wrong, I am not knocking any of these parts. But I > don't see a serdes and being a valuable addition to a low cost FPGA. > Normally the items you are interfacing to with a serdes are not so > cheap, but maybe I am not current and serdes are more popular now. But > I see it as similar to the conversation where someone was complaining > about needing to use $0.09 FETs for a high current interface rather > than the low cost $0.03 cent 7002 FETs because the 3.3 volt interface > on the FPGA would not drive the FET fully. Even a cheap FPGA is around > $20 in most designs, so what is the diff on a few cents on the FETs? > LIkewise, what is the diff on a $40 FPGA rather than a $20 FPGA if it > interfaced to a $200+ fiber interface? > > Personally what I want is a good $10 FPGA with 260 IOs. So far they > are all about $20. If it has more memory to support an imbedded MCU, > all the better! Not all SERDES go into optics, and in fact many never leave the printed circuit board. Low-cost devices with SERDES can help with multi-device designs, where extra devices are more cost-effective than a single device with the required number of I/O's. Using high- speed SERDES from chip to chip reduces the interconnect pin count giving you more of the I/O you added the parts for. I would think the ASIC simulation guys would snap these parts up...Article: 108926
David Ashley wrote: [snip] > I want to get rid of one of the DCM's, 2 seems excessive. Is it common > to use > an fddr to get a clock to the outside this way? That is, an fddr has > fixed inputs > (input0 <= '0', input1 <= '1') and so the fddr output is really just a > data selector, > when the input clock is low you get input0, when high you get output1. Why > not route the clock through to the outside directly? > > I've tried hanging the DDR's clock off of bufg1 (still going through fddr) > but it doesn't work reliably, I get flaky data. > > Where can I find info about clock generation issues, specifically > related to ddr. The FDDR is used to generate the external signal with the same clock to output delay as the associated data lines. Routing a clock to an output buffer requires non-clock resources in the Xilinx parts. The FDDR takes the global clock (very low skew) directly from the dedicated routing. Its delay is matched to the clock to out delay of the DDR flops on the DQ bus. So if you us a DCM and global clock resources to generate the internal clocks for DQ and clock, you directly set the phase relationship between the clock output and DQ. When you try to route the clock through an output buffer you are at the mercy of the router, and even if you get the design to work the timing may change if you re-build due to chenges of seemingly unrelated sections of the design.Article: 108927
Hi all, I've heard that a good rule of thumb is to not to use a global clock as an enable for flops or RAMs. Even though static timing numbers might look ok, are there any consequences of doing this?Article: 108928
One more doubt Ray, I am an FPGA based designer also a beginer. My doubt is if due to some reasons i want a reset signal for a RAM block for which i am ready to sacrifice the area and fanout problem is it possible to create one in ASIC. Sumesh Ray Andraka wrote: > vssumesh wrote: > > > Why there is such a limitation. Why cant we pass a rest to all ram > > cells. Please advice me. > > Thanks and regards > > Sumesh V S > > > > The reason is the silicon does not support it, there is no reset line > that clears the RAM. The reason it is not designed into the silicon is > that adding a reset just about doubles the size of a RAM cell, plus > requires a very high fan-out signal. The area and speed implications > are both strong disincentives to including a reset that clears the whole > array at once.Article: 108929
Hello all, In my design i am using a 32 bit adder and some combinational logic after that. The full path i want to constrain to double the clock period (20ns) and it is not constraing. When analysed the critical path observed that there is big carry chain for the adder and a big routing delay between the combinational logic (which i never expected). Is the big carry chain is causing the trouble in the router. I am thinking of buffering the output of the adder with a -ve edge (constrain that path to 5ns). And then constrain the other path that is after the buffer to next stage FF to 16ns. Will this buffering ease the routing effort. Please advice. Thanks and regards Sumesh V SArticle: 108930
Jim, First, Virtex customers often do not use eeprom, or flash (one per chip), but load all FPGAs from some other 'source of all knowledge'. Virtex would not be looking at a FPGA+Flash until there was sufficient business for such a model. Second, Spartan customers are the perfect target for such a product. So if it happens, expect it to happen there. Yes, the question is when. And, the question is also, how? As everyone knows, flash lags the leading process edge by a year (or more), and flash and the highest speed bulk cmos process don't live well together. The result is that the best leading edge flash, and the best leading edge FPGA is always a cheaper, and more capable solution. As I said, I am not in marketing, and I can not talk about what the next products are, nor what features they have. However, once the technology issue is solved, then having a FPGA with FLASH memory is definitely something that will happen. Again, the key is to have the latest FPGA, and the latest flash, without the penalty of having to fabricate them both in the same process. So, stay tuned. AustinArticle: 108931
Karl, http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&category=-1212267&sGlobalNavPick=&sSecondaryNavPick= How easy is that? AustinArticle: 108932
What kind of device are you using? 20 ns for a 32-bit adder (using dedicated carry) would be ridiculously slow... Dedicated carry, available in all Xilinx FPGA devices, uses less than 50 ps per bit (plus some basic delay). Peter Alfke =========== vssumesh wrote: > Hello all, > In my design i am using a 32 bit adder and some combinational logic > after that. The full path i want to constrain to double the clock > period (20ns) and it is not constraing. When analysed the critical path > observed that there is big carry chain for the adder and a big routing > delay between the combinational logic (which i never expected). Is the > big carry chain is causing the trouble in the router. I am thinking of > buffering the output of the adder with a -ve edge (constrain that path > to 5ns). And then constrain the other path that is after the buffer to > next stage FF to 16ns. Will this buffering ease the routing effort. > Please advice. > Thanks and regards > Sumesh V SArticle: 108933
Ray Andraka wrote: > Andreas Ehliar wrote: > > > On 2006-09-07, Ray Andraka <ray@andraka.com> wrote: > > > >>It will help tremendously if the timing constraints are not pushing the > >>envelope for your design. > > > > > > For fun I just created some graphs that show this at > > http://www.da.isy.liu.se/~ehliar/stuff/place_and_route.html . The design > > is a floating point adder and the timing constraint is varied in > > steps of .05 ns between 1 and 10 nanoseconds. The runtime of par and the > > performance of the design is shown in the graphs. > > > > I do feel quite lucky that I have not yet created a design which takes > > 30 hours to route though :) > > > > /Andreas > > When you get into the region where the propagation delay is getting > close to the constraints, floorplanning can make a huge difference in > the run time, as well as in the ability for the design to meet timing at > all. A good floorplan essentially narrows the region on your second > graph where the run time is greatly increased. > > The design I have that is running 30 hours is slowly decreasing in run > time as I make adjustments to the floorplanning to improve the timing. I also have such an experiance with a design with which some 8 hrs efforts the router will say that it is impossibel to route; after a good floor planning will route with in 1/2 hr. Also time driven mapping will do good to the routing, Ray, Is there any conventions that i can use while floor planning. I think i have found one - dont know whether it is true. "Dont separate a block which is very big ino two parts of FPGA because the interconnections between the two parts will cuase problem with the routing of the intermediate logic". Also i think it is good practise to always separte FFs that uses two clocks. Is there any pdf or books available in this topic? regards Sumesh V SArticle: 108934
My collegue just done that ... his id is subin.82@gmail.com szumu@poczta.onet.pl wrote: > Hi, > > I wonder if anybody has a positive experience with Xilinx MIG1.6 (or > earlier version) as a controller for DDR2 memory for Spartan3 family. > Has anybody implemented successfully the controller on his project and > verified it in the hardware? I would be glad to exchange any insights > regarding this controller. > > thanks, > Robert SzumowiczArticle: 108935
Hello all, I am quite confused about the Ethernet MAC wrapper IP core. In the documentation is written (if I understand correctly) that I have to provide clk_gtx_clk, clk_phy_tx_clk0, clk_phy_rx_clk0, all are 125 MHz clocks when I am using only EMAC0 and 1Gbps operation. But inside the vhdl files I found hostclk and refclk and information that hostclk must always be connected and refclk (200 MHz). So the question is what clocks I really have to connect when I would like to operate at 1 Gbps and only EMAC0 and do I have to introduce some DCM to make that IP running on Xilinx ML403 board? Regards, BartekArticle: 108936
Roger schrieb: > How does a BUF component increase the drive strength of a signal? Almost all buffers are two inverters in a chain. The last inverter may have bigger transistors. But even with standard size transistors a buffer is useful: If a weak signal is only capable of driving the first inverter of a buffer, the output inverter will be capable of driving much more gates. The cost for all this: a delay. RalfArticle: 108937
I would greatly appreciate if someone could explain the behavior I'm
seeing for me.
In the inner most if-state, where I write to bDATA_OUT ---- if I run
the program as written, it does nothing (my DATA_OUT lines remain in
the state they were previously). If I remove the "else, bDATA_OUT <=
"11000000"" segment, it properly outputs 00001010. I don't understand
why it would work w/o the else, but not w/.
This is a snippet of a larger VHDL, trimmed down for debugging.
Thank you.
Alex McHale
entity driver is
Port ( CLOCK : in STD_LOGIC;
ACTIVE : in STD_LOGIC;
CLOCK_IN : in STD_LOGIC;
LATCH_IN : in STD_LOGIC;
DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0);
DATA_CLOCK_OUT : out STD_LOGIC;
CLOCK_OUT : out STD_LOGIC;
LATCH_OUT : out STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) );
end driver;
architecture Behavioral of driver is
signal mode : STD_LOGIC := '0';
signal column_out : STD_LOGIC_VECTOR(9 downto 0) := "0000000000";
signal bDATA_OUT : STD_LOGIC_VECTOR(7 downto 0);
begin
process( CLOCK )
begin
if( rising_edge( CLOCK ) ) then
if mode='0' then
CLOCK_OUT <= '0';
LATCH_OUT <= '0';
mode <= '1';
elsif mode='1' then -- DATA INCOMING
if column_out(0)='0' then
bDATA_OUT <= "00001010";
else
bDATA_OUT <= "11000000";
end if;
CLOCK_OUT <= '1';
LATCH_OUT <= '1';
column_out <= column_out + 1;
mode <= '0';
end if;
end if;
end process;
DATA_OUT <= bDATA_OUT;
end Behavioral;
Article: 108938Ralf Hildebrandt wrote: > Roger schrieb: > >> How does a BUF component increase the drive strength of a signal? > > Almost all buffers are two inverters in a chain. The last inverter may > have bigger transistors. > > But even with standard size transistors a buffer is useful: If a weak > signal is only capable of driving the first inverter of a buffer, the > output inverter will be capable of driving much more gates. The cost for > all this: a delay. > > Ralf More, If the load is large, a buffer will improve the delay (as it can charge and discharge the capacitive load faster than a weak driver). So, the cost for a buffer is that you may need one to meet your speed requirements, and reduce delay. AustinArticle: 108939
On 2006-09-19, vssumesh <vssumesh_asic@yahoo.com> wrote: > One more doubt Ray, I am an FPGA based designer also a beginer. My > doubt is if due to some reasons i want a reset signal for a RAM block > for which i am ready to sacrifice the area and fanout problem is it > possible to create one in ASIC. > Sumesh Suppose you want to reset a RAM memory of 512 kilowords with one reset signal and you are writing to it in chunks of 32 bits. You could design a wrapper around it where you could have one flip flop per word that signifies if that particular word is valid or not. Once the wrapper gets the reset signal, all flip flops are set to zero. As soon as you write to a certain word, the corresponding flip flop is set to 1. Once you read from the RAM memory, the wrapper will output all zeroes if the signal from the valid flip flop corresponding to the read address is zero, otherwise it will output the value from the RAM memory. This is of course rather hardware intensive because you have to keep track of 512 flip flops. It will also increase the critical path of your memory readout by quite much. But it will work regardless of how often your reset signal is asserted. If you don't want to reset your RAM memory very often you have many more design alternatives. The easiest would be to double buffer your RAM memory. While you are working on data in one RAM memory you are clearing the other. /AndreasArticle: 108940
We are designing a comunication system on a Spartan3 with a lot of data
processing and buffering.
We have several simulation mismatches:
behavioral simulation gives results identical to Post-translate (with
XST8.2.02 and option Keep Hierarchy: yes)
But simulation of Post-translate with XST and option Keep Hierarchy
off, gives different results; it's only a few different vectors over a
thousand, but still unexplicable to me.
We tried to compile with Synplify Pro, default settings; we did another
post-translate simulation and the results are still different from all
previous cases (again only a few vectors over a thousand).
Any experience with that ?
We paid attention to signed logic issues (see thread "behavioral vs
post-P&R simulation mismatch" on Aug 30, 2006).
We paid attention to crossing the clock domains. The clock structure
is (in Verilog)
/////////////////////////////////////////
...
input clk80, // 80 MHz clock.
...
always @(posedge clk80) CE40 <= ~CE40;
BUFG BUFG_clk40 (.O(clk40), .I(CE40));
//////////////////////////////////////////////////////
the reason for doing that, is we need a 40 MHz signal (CE40) to be used
as an enable in the 80MHz domain. This signal must be in phase with
clk40, and must not creates setup/hold violations when clocked by clk80
(this could happen using a DCM).
Article: 108941Alex, column_out is a 10 bit bus, and you are trying to compare it with a single bit. I think you forgot the 'others' keyword to force the compare to match the constant with the thing being compared? If this variable is a 6 bit counter: (signal mhertz_count : std_logic_vector(5 downto 0) ;) mhertz_count <= (others => '0') ; is the proper way to see if it is 0. Austin Alex wrote: > I would greatly appreciate if someone could explain the behavior I'm > seeing for me. > > In the inner most if-state, where I write to bDATA_OUT ---- if I run > the program as written, it does nothing (my DATA_OUT lines remain in > the state they were previously). If I remove the "else, bDATA_OUT <= > "11000000"" segment, it properly outputs 00001010. I don't understand > why it would work w/o the else, but not w/. > > This is a snippet of a larger VHDL, trimmed down for debugging. > > Thank you. > > Alex McHale > > entity driver is > Port ( CLOCK : in STD_LOGIC; > ACTIVE : in STD_LOGIC; > CLOCK_IN : in STD_LOGIC; > LATCH_IN : in STD_LOGIC; > DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); > ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0); > DATA_CLOCK_OUT : out STD_LOGIC; > CLOCK_OUT : out STD_LOGIC; > LATCH_OUT : out STD_LOGIC; > DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) ); > end driver; > > architecture Behavioral of driver is > signal mode : STD_LOGIC := '0'; > signal column_out : STD_LOGIC_VECTOR(9 downto 0) := "0000000000"; > signal bDATA_OUT : STD_LOGIC_VECTOR(7 downto 0); > begin > process( CLOCK ) > begin > if( rising_edge( CLOCK ) ) then > if mode='0' then > CLOCK_OUT <= '0'; > LATCH_OUT <= '0'; > > mode <= '1'; > elsif mode='1' then -- DATA INCOMING > if column_out(0)='0' then > bDATA_OUT <= "00001010"; > else > bDATA_OUT <= "11000000"; > end if; > > CLOCK_OUT <= '1'; > LATCH_OUT <= '1'; > column_out <= column_out + 1; > > mode <= '0'; > end if; > end if; > end process; > > DATA_OUT <= bDATA_OUT; > end Behavioral; >Article: 108942
Don't do it man. Just don't. The delay from the clock signal leaving the global network to your flip flop is unknown and large. Hence it is impossible to syncronize your enable with your clock signal in that situation. There is no reason to do this. Post your circuit and we'll help you find a better way. I've thought that I needed this functionality in the past, but I've always found a way around it. I have occasionally seen uses for driving the clock with logic rather than a global clock. This situation shows up in input IOBs or the JTAG connection lines. mav1101 wrote: > Hi all, > > I've heard that a good rule of thumb is to not to use a global clock as > an enable for flops or RAMs. Even though static timing numbers might > look ok, are there any consequences of doing this?Article: 108943
Brian Drummond wrote: > On Mon, 18 Sep 2006 14:50:42 -0700, David Ashley > <dash@nowhere.net.dont.email.me> wrote: > > >>Mostly for xilinx people, >> >>xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes >>Available here: >>http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf#search=%22xilinx%20ddr%20fae%22 >> >>On page 3 is figure 2. There is an FDDR shown on the diagram that has >>left and right data going into the D0 and D1 inputs, but both clocks >>are coming from the same source (CLK0 from the DCM). Shouldn't >>C1 be coming from the CLK180? > > > Notice the clock inversion circle on one of the clock input pins. > > (I hope Xilinx explain their schematic conventions somewhere - not > everyone still has those fat orange (sorry Peter - red) books on their > shelves!) > > - Brian > After I posted I did notice that but I wanted confirmation. I think of a solid round dot as a connection. An inversion bubble is usually a circle. Also their dot seems embedded in the device, it should stand out more. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108944
Oops, You are comparing a single bit (one element) so I am wrong... Austin Austin Lesea wrote: > Alex, > > column_out is a 10 bit bus, and you are trying to compare it with a > single bit. > > I think you forgot the 'others' keyword to force the compare to match > the constant with the thing being compared? > > If this variable is a 6 bit counter: > (signal mhertz_count : std_logic_vector(5 downto 0) ;) > > mhertz_count <= (others => '0') ; > > is the proper way to see if it is 0. > > Austin > > Alex wrote: >> I would greatly appreciate if someone could explain the behavior I'm >> seeing for me. >> >> In the inner most if-state, where I write to bDATA_OUT ---- if I run >> the program as written, it does nothing (my DATA_OUT lines remain in >> the state they were previously). If I remove the "else, bDATA_OUT <= >> "11000000"" segment, it properly outputs 00001010. I don't understand >> why it would work w/o the else, but not w/. >> >> This is a snippet of a larger VHDL, trimmed down for debugging. >> >> Thank you. >> >> Alex McHale >> >> entity driver is >> Port ( CLOCK : in STD_LOGIC; >> ACTIVE : in STD_LOGIC; >> CLOCK_IN : in STD_LOGIC; >> LATCH_IN : in STD_LOGIC; >> DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); >> ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0); >> DATA_CLOCK_OUT : out STD_LOGIC; >> CLOCK_OUT : out STD_LOGIC; >> LATCH_OUT : out STD_LOGIC; >> DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) ); >> end driver; >> >> architecture Behavioral of driver is >> signal mode : STD_LOGIC := '0'; >> signal column_out : STD_LOGIC_VECTOR(9 downto 0) := "0000000000"; >> signal bDATA_OUT : STD_LOGIC_VECTOR(7 downto 0); >> begin >> process( CLOCK ) >> begin >> if( rising_edge( CLOCK ) ) then >> if mode='0' then >> CLOCK_OUT <= '0'; >> LATCH_OUT <= '0'; >> >> mode <= '1'; >> elsif mode='1' then -- DATA INCOMING >> if column_out(0)='0' then >> bDATA_OUT <= "00001010"; >> else >> bDATA_OUT <= "11000000"; >> end if; >> >> CLOCK_OUT <= '1'; >> LATCH_OUT <= '1'; >> column_out <= column_out + 1; >> >> mode <= '0'; >> end if; >> end if; >> end process; >> >> DATA_OUT <= bDATA_OUT; >> end Behavioral; >>Article: 108945
Hi Alex, I modeled this with ISE 7.1 and ModelSimXE III 6.0d and the DATA_OUT alternates between 00001010 and 11000000 as I expected. I am not sure what you expected to see. Brad Smallridge aivision "Alex" <alexmchale@gmail.com> wrote in message news:1158680022.780556.64880@e3g2000cwe.googlegroups.com... >I would greatly appreciate if someone could explain the behavior I'm > seeing for me. > > In the inner most if-state, where I write to bDATA_OUT ---- if I run > the program as written, it does nothing (my DATA_OUT lines remain in > the state they were previously). If I remove the "else, bDATA_OUT <= > "11000000"" segment, it properly outputs 00001010. I don't understand > why it would work w/o the else, but not w/. > > This is a snippet of a larger VHDL, trimmed down for debugging. > > Thank you. > > Alex McHale > > entity driver is > Port ( CLOCK : in STD_LOGIC; > ACTIVE : in STD_LOGIC; > CLOCK_IN : in STD_LOGIC; > LATCH_IN : in STD_LOGIC; > DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); > ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0); > DATA_CLOCK_OUT : out STD_LOGIC; > CLOCK_OUT : out STD_LOGIC; > LATCH_OUT : out STD_LOGIC; > DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) ); > end driver; > > architecture Behavioral of driver is > signal mode : STD_LOGIC := '0'; > signal column_out : STD_LOGIC_VECTOR(9 downto 0) := "0000000000"; > signal bDATA_OUT : STD_LOGIC_VECTOR(7 downto 0); > begin > process( CLOCK ) > begin > if( rising_edge( CLOCK ) ) then > if mode='0' then > CLOCK_OUT <= '0'; > LATCH_OUT <= '0'; > > mode <= '1'; > elsif mode='1' then -- DATA INCOMING > if column_out(0)='0' then > bDATA_OUT <= "00001010"; > else > bDATA_OUT <= "11000000"; > end if; > > CLOCK_OUT <= '1'; > LATCH_OUT <= '1'; > column_out <= column_out + 1; > > mode <= '0'; > end if; > end if; > end process; > > DATA_OUT <= bDATA_OUT; > end Behavioral; >Article: 108946
Gabor wrote: > David Ashley wrote: > [snip] > >>I want to get rid of one of the DCM's, 2 seems excessive. Is it common >>to use >>an fddr to get a clock to the outside this way? That is, an fddr has >>fixed inputs >>(input0 <= '0', input1 <= '1') and so the fddr output is really just a >>data selector, >>when the input clock is low you get input0, when high you get output1. Why >>not route the clock through to the outside directly? >> >>I've tried hanging the DDR's clock off of bufg1 (still going through fddr) >>but it doesn't work reliably, I get flaky data. >> >>Where can I find info about clock generation issues, specifically >>related to ddr. > > > The FDDR is used to generate the external signal with the same > clock to output delay as the associated data lines. Routing > a clock to an output buffer requires non-clock resources in > the Xilinx parts. The FDDR takes the global clock (very low > skew) directly from the dedicated routing. Its delay is matched > to the clock to out delay of the DDR flops on the DQ bus. So > if you us a DCM and global clock resources to generate the > internal clocks for DQ and clock, you directly set the phase > relationship between the clock output and DQ. When you > try to route the clock through an output buffer you are at the > mercy of the router, and even if you get the design to work > the timing may change if you re-build due to chenges of > seemingly unrelated sections of the design. > In experiments I had been able to get rid of the fddr's on the true + inverted DDR clock outputs, but I just did that to see if it would work. It's pointless since the FDDR's are part of the IOB's anyway and conserving them doesn't make them available for any other function. However I wasn't able to get rid of the 2nd DCM, and I'm running out of ideas to try. One thing of note -- this is on the spartan-3e starter board. It supplies a 50 mhz clock. I run this through a DCM to produce 100 mhz, and that's use to feed the other 2 DCM's. I kind of remember this is not a good idea? Unfortunately (according to my understanding of the DCM's) you can't both get a multiplied output clock from a DCM and have the 0, 90, 180 and 270 phases of that clock. So I don't know how to accomplish this other than stringing DCM's together. Or get an external 100mhz crystal oscillator and put it into the socket. Thanks-- Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108947
Chris, One of the comments made by Dave: "Next challenge for most software developers is coming to terms with the parallel nature of a HDL." represents a significant divergence between software implementation of logic and hardware implementation of logic. In software, with a single processor, all logic is evaluated sequentially from the start of the program to the end of the program. In hardware, if you think about it, the whole FPGA is operating simultaneously. You have to describe the logic sequentially because that's the nature of the physical media (eg the text file), but the hardware it describes is all present once the power is turned on. That dimensional shift can take a little getting used to.Article: 108948
> If you don't want to reset your RAM memory very often you have many more > design alternatives. The easiest would be to double buffer your RAM memory. > While you are working on data in one RAM memory you are clearing the other. > 'Easy' being a relative term another relatively easy approach is to simply add a wrapper around your inferred memory that receives the reset signal and then sequences through the memory writing it with 0. After a reset, it means that the memory would not be available for reading or writing until the initialization has been completed. Alternatively it could mean that the wrapper has a relatively l--o--n--g reset time requirement (with the initialization being kicked off by the leading edge of reset) where the user is expected to keep reset asserted for a long enough period of time for the memory initialization to be completed. KJArticle: 108949
Yes, I hadn't yet modeled it. It works fine in the simulator for me as well. The problem appears when I run it on our hardware. So now I'm left even more stumped. Brad Smallridge wrote: > Hi Alex, > > I modeled this with ISE 7.1 and ModelSimXE III 6.0d and the > DATA_OUT alternates between 00001010 and 11000000 as I expected. > > I am not sure what you expected to see. > > Brad Smallridge > aivision > > > > "Alex" <alexmchale@gmail.com> wrote in message > news:1158680022.780556.64880@e3g2000cwe.googlegroups.com... > >I would greatly appreciate if someone could explain the behavior I'm > > seeing for me. > > > > In the inner most if-state, where I write to bDATA_OUT ---- if I run > > the program as written, it does nothing (my DATA_OUT lines remain in > > the state they were previously). If I remove the "else, bDATA_OUT <= > > "11000000"" segment, it properly outputs 00001010. I don't understand > > why it would work w/o the else, but not w/. > > > > This is a snippet of a larger VHDL, trimmed down for debugging. > > > > Thank you. > > > > Alex McHale > > > > entity driver is > > Port ( CLOCK : in STD_LOGIC; > > ACTIVE : in STD_LOGIC; > > CLOCK_IN : in STD_LOGIC; > > LATCH_IN : in STD_LOGIC; > > DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); > > ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto 0); > > DATA_CLOCK_OUT : out STD_LOGIC; > > CLOCK_OUT : out STD_LOGIC; > > LATCH_OUT : out STD_LOGIC; > > DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0) ); > > end driver; > > > > architecture Behavioral of driver is > > signal mode : STD_LOGIC := '0'; > > signal column_out : STD_LOGIC_VECTOR(9 downto 0) := "0000000000"; > > signal bDATA_OUT : STD_LOGIC_VECTOR(7 downto 0); > > begin > > process( CLOCK ) > > begin > > if( rising_edge( CLOCK ) ) then > > if mode='0' then > > CLOCK_OUT <= '0'; > > LATCH_OUT <= '0'; > > > > mode <= '1'; > > elsif mode='1' then -- DATA INCOMING > > if column_out(0)='0' then > > bDATA_OUT <= "00001010"; > > else > > bDATA_OUT <= "11000000"; > > end if; > > > > CLOCK_OUT <= '1'; > > LATCH_OUT <= '1'; > > column_out <= column_out + 1; > > > > mode <= '0'; > > end if; > > end if; > > end process; > > > > DATA_OUT <= bDATA_OUT; > > end Behavioral; > >
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