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Hmm, I've just read that a read operation on the OPB Bus costs 3 clock cycles, while a read operation costs 4 clock cycles. So my try to get, the output of my peripheral every clock cycle without having to stop the device till the data is read seems not to be able to work... Or does anybody know something different? Regards, Peter Peter Kampmann schrieb: > Hi, > > I've designed a PowerPC C++ Application (as standalone configuration) > that communicates with an custom peripheral. > The custom peripheral, simply counts up a std_logic_vector until it > reaches the decimal value 100. > This increment is done every clock cycle, the design is made up as an > FSM. > > Now I send a start signal to the peripheral, the peripheral starts > counting. > The PowerPC now waits for the peripheral, that sends a "ready" signal, > indicating that it puts the first increment to the output register. > > Now I want to read every clock cycle from this output register, so that > the powerPC gets something like (1,2,3...,100) as input from the > peripheral. > > Therefore the PowerPC waits for the ready signal and then continously > reads the output register. > > Unfortunately, all I get as an input from the peripheral is the last > value of the counting :( > > The peripheral is connected via the OPB bus to the PowerPC, I've > learned that this Bus runs at 100 Mhz when configuring the PowerPC to > run at 300 Mhz. The clock of the peripheral is connected to the > sys_clk_s. > > I expect that the PowerPC reads data much faster from the Bus than the > peripheral writes them onto the bus. I even build up a clock divider, > slowing down the peripheral to sys_clk_s/4 but all I get is the last > value. > > What is missing in my configuration or do you have an assumption what I > am doing wrong? > > Any help is highly appreciated, regards > PeterArticle: 109226
Joerg wrote: > Hello Uwe, > >> >>> My suggestion would be to pay a little more and get a laptop with a >>> genuine parallel port. >> >> PCMCIA Cards might be another option... > > > Yes. Although I was cautioned by TI that the MSP430 JTAG programmer > might show some quirks if I did that. In the end I switched all tools to > USB. Certainly the OpenTV tools which make heavy use of a parallel port do not work with USB or PCMCIA parallel port devices - I've tried. We went with a Dell M60 in the end (which is new a couple of years old) as it had serial and parallel as standard. DArticle: 109227
Chris Carlen wrote: > Howard Long wrote:[edit] >> If the port replicator is a Dell unit designed specifically for the >> laptop and does _not_ simply replicate parallel ports via a USB port, >> then you will probably be OK. Forget it if it's a USB-type replicator. >> >> Good luck, Howard > > The tough part is finding out what it has before I buy it. Check the Dell images of the product, specifically the underside. If, towards the back of the bottom, probably in the middle, there are 2 little flaps then that is where the docking station connects - which is a multiway connector (lots of connectors!) which usually is more than just a USB device which gives you the extra ports. For example, they'll run VGA and DVI over it as well. DArticle: 109228
John Williams wrote: > Hi Chris, > > Chris Carlen wrote: > >> I'm considering to buy a Dell Precision M90 laptop to replace a regular >> PC on a cart that was used to wheel around and program various embedded >> devices. >> >> The new laptops of course don't offer old-fashioned ports like parallel >> and RS-232. Well, some have serial, but the M90 doesn't. > > I use "the world's most expensive parallel port" (TM) - a Quatech SPP-100 in my > Dell Laptop. Paying $200 for a PCMCIA interface + voltage drivers is painful, > but the thing works just fine with the Xilinx tools. You do need to override > the ECP base address, there's an environment variable you can set. Google > comp.arch.fpga's history for this topic, you'll find it discussed at length over > the years. > > Regards, > > John We tried one of these in the past, but they didn't work with the OpenTV tools we were using which used the parallel port. DArticle: 109229
Chris Carlen wrote: > Brad Griffis wrote:[edit] > > A co-worker of mine has the M90 (or maybe M70?) and I know he does work > > through the comm port on the docking station and I haven't heard him > > make any complaints. In fact, he's been quite happy with the > > performance of his laptop. It runs Linux through VMware faster than his > > old desktop could run it natively! > > Any chance you could ask your coworker if he's used the parallel port, > and what for? > > > By the way, USB JTAG emulators for TI DSPs have been out for quite a > > while. A good low-cost emulator for c2000 DSPs is JTAGjet from Signum. > > Spectrum Digital also now sells newer versions of the eZdsp with a USB > > interface rather than the parallel port interface. > > > Hmm, I didn't see that yet. I have about 3 of the parallel port ones :-(. > > But I could order some new ones if they have USB. > > It seems the cheap $345 one is still parallel. > > http://www.spectrumdigital.com/product_info.php?cPath=30&products_id=137&osCsid=2435023cbd79a909060037c302e5298b > > Need to spend $1800 to get a JTAG emulator. I'll likely do this at some > point anyway, but I'd still like a working parallel port. > > -- > Good day! > > ________________________________________ > Christopher R. Carlen > Principal Laser&Electronics Technologist > Sandia National Laboratories CA USA > crcarleRemoveThis@BOGUSsandia.gov > NOTE, delete texts: "RemoveThis" and > "BOGUS" from email address to reply. If you are using your 2812 for controling any kind of switching power supply, take into account that PP emulators are far less susceptible to EMI than USB kind. This way you also do not have any problems connecting and disconnecting target while CCS is active. MitjaArticle: 109230
Another remark:
If I am using the mentioned clock divider, which shoud slow down my own
designed Processes to 25 Mhz, assuming that the OPB runs at 100 Mhz, I
should get clock-wise signal outputs in regard to the 25 Mhz clock.
The read and write processes are clocked by the BusIP_Clk, so they are
running at 100 Mhz.
In the following, I'm posting my test code, perhaps then it is easier
to understand what I mean :)
--USER logic implementation added here
my_rst <= slv_reg0(1);
start <= slv_reg0(0);
my_Clock : PROCESS(Bus2IP_Clk,Bus2IP_Reset)
begin
if(Bus2IP_Reset = '1') then
clk_counter <= (others => '0');
clk_50Mhz <= '0';
elsif(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
clk_counter <= clk_counter + 1;
if (clk_counter = "100") then
clk_50Mhz <= not clk_50Mhz;
clk_counter <= (others => '0');
end if;
end if;
end process;
FSM : PROCESS(clk_50Mhz, my_rst)
begin
slv_reg1(2) <= clk_50Mhz;
if(my_rst = '1') then
ctrlState <= idle;
slv_reg2 <= (others => '0');
counter <= (others => '0');
elsif (clk_50Mhz'event and clk_50Mhz = '1') then
case ctrlState is
when idle =>
if(start = '1') then
ctrlState <= count;
else
ctrlState <= idle;
end if;
when count =>
result <= '0';
counter <= counter + 1;
ctrlState <= output;
when output =>
slv_reg2 <= counter;
slv_reg0(2) <= '1';
if (counter <= "00000000000000000000000001100100") then
ctrlState <= count;
else
ctrlState <= finish;
end if;
when finish =>
ctrlState <= finish;
end case;
end if;
end process fsm;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible
registers
--
-- Note:
-- The example code presented here is to show you one way of
reading/writing
-- software accessible registers implemented in the user logic slave
model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
-- to one software accessible register by the top level template. For
example,
-- if you have four 32 bit software accessible registers in the user
logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 2);
slv_reg_read_select <= Bus2IP_RdCE(0 to 2);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or
Bus2IP_WrCE(2);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or
Bus2IP_RdCE(2);
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_select is
when "100" => slv_reg0 <= Bus2IP_Data(0 to C_DWIDTH-1);
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1, slv_reg2 ) is
begin
case slv_reg_read_select is
when "100" => slv_ip2bus_data <= slv_reg0;
when "010" => slv_ip2bus_data <= slv_reg1;
when "001" => slv_ip2bus_data <= slv_reg2;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
Regards,
Peter
Peter Kampmann schrieb:
> Hmm, I've just read that a read operation on the OPB Bus costs 3 clock
> cycles, while a read operation costs 4 clock cycles. So my try to get,
> the output of my peripheral every clock cycle without having to stop
> the device till the data is read seems not to be able to work...
>
> Or does anybody know something different?
>
> Regards,
> Peter
>
>
> Peter Kampmann schrieb:
>
> > Hi,
> >
> > I've designed a PowerPC C++ Application (as standalone configuration)
> > that communicates with an custom peripheral.
> > The custom peripheral, simply counts up a std_logic_vector until it
> > reaches the decimal value 100.
> > This increment is done every clock cycle, the design is made up as an
> > FSM.
> >
> > Now I send a start signal to the peripheral, the peripheral starts
> > counting.
> > The PowerPC now waits for the peripheral, that sends a "ready" signal,
> > indicating that it puts the first increment to the output register.
> >
> > Now I want to read every clock cycle from this output register, so that
> > the powerPC gets something like (1,2,3...,100) as input from the
> > peripheral.
> >
> > Therefore the PowerPC waits for the ready signal and then continously
> > reads the output register.
> >
> > Unfortunately, all I get as an input from the peripheral is the last
> > value of the counting :(
> >
> > The peripheral is connected via the OPB bus to the PowerPC, I've
> > learned that this Bus runs at 100 Mhz when configuring the PowerPC to
> > run at 300 Mhz. The clock of the peripheral is connected to the
> > sys_clk_s.
> >
> > I expect that the PowerPC reads data much faster from the Bus than the
> > peripheral writes them onto the bus. I even build up a clock divider,
> > slowing down the peripheral to sys_clk_s/4 but all I get is the last
> > value.
> >
> > What is missing in my configuration or do you have an assumption what I
> > am doing wrong?
> >
> > Any help is highly appreciated, regards
> > Peter
Article: 109231Josep Duran schrieb: > Antti wrote: > > FPGA is not a MicroController? > > ...or is it !? > > > > MicroFpga makes an FPGA to look like an MCU, and makes it programmable > > as it would be a normal MCU without requiring any HDL knowledge or FPGA > > implementation tools. > > > > More details will be available from the product website > > http://www.microfpga.com > > ..soon > > > Hi Antti, > > I take it that this is some kind of microblaze derivative, stripping > out the Xilinx software flow, and thus making the whole design flow > much more simple. > > I can think of a lot of products where the whole microblaze thing might > be overkill (not that I have tried it myself), and this could be a > solution. > > It could also be interesting as a first step to microblaze, and once > you get comfortable with the software side of it step to the real > version. > > My questions would be : > - is there any external Bus ? > - Max ROM/RAM available. > - Peripherals : counters, UART, VGA controller, etc > > I just can't wait till you make the details available at the website. > > > Regards > > Josep Duran Hi Josep, the toplevel ports of *ALL* MicroFpga/Generic look the same: entity mf_top is Generic ( C_GP_WIDTH : integer := CFG_GP_WIDTH ); Port ( GP : inout STD_LOGIC_VECTOR (0 to C_GP_WIDTH-1) ); end mf_top; where CFG_GP_WIDTH = "number of total FPGA IO pins" and yes, you can connect VGA signal to GP(x) but the VGA controller would be limited to use only on-chip block RAMs. Maximum pixel clock and color depth depend on the FPGA being used and MicroFpga configuration being used. 3-bit pro color should be possible, or even 4 bits pro color. There are always some compromises. being able to handle ANY and all available FPGA pins exactly the same, and being able to run on ANY design and board makes it not possible to support everything. But quite a many things are possible within the given constraints that the design must run in any hardware platform without customization that is one bit stream is useable without changes in all boards that have a compatible FPGA on it. The types of external memories supported is somewhat limited, but all effort will be given to support as many different external memories as possible. Thanks for interest, AnttiArticle: 109232
mk wrote: > On 21 Sep 2006 08:52:34 -0700, "Jon Beniston" <jon@beniston.com> > wrote: > > >> - "Core 2 duo 4M cache" might be even better > > > >I just bought one of these. Bloody quick. Sped up my P&R 4x compared to > >the Pentium 4 I was using. Well worth the money. > > Could you give some spec, memory, cpu frequency on both machines? E6600 Dual Core - 2.6 GHz, with DDRII 667 memory. Pentium 4 was 3 GHz, with 400 MHz memory, I think. (So a little old, but not exactly ancient) Cheers, JonArticle: 109233
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:newscache$qwvy5j$bb5$1@lbox.itee.uq.edu.au... > I use "the world's most expensive parallel port" (TM) - a Quatech SPP-100 > in my > Dell Laptop. Paying $200 for a PCMCIA interface + voltage drivers is > painful, > but the thing works just fine with the Xilinx tools. You do need to > override > the ECP base address, there's an environment variable you can set. Google > comp.arch.fpga's history for this topic, you'll find it discussed at > length over > the years. I use the Quatech SPP-100 too. However to get it to work on a low port (ie, < 0x0400), I had to move the internal parallel port to 0x278, then hack the SPP-100n.inf file and reinstall the driver (I am using XP) to get it to install and behave at 0x378. SPP-100n.inf: ... [LptportXP.LogConfigOverride] LogConfig =LptportXP.Override0,LptportXP.Override1,LptportXP.Override2,LptportXP.Override3,LptportXP.Override4,LptportXP.Override5,LptportXP.Override6,LptportXP.Override7,LptportXP.Override8 ... ... [LptportXP.Override8] ConfigPriority=NORMAL IOConfig=378-37f(3ff::) IRQConfig=3,4,5,7,14 PcCardConfig = 9 ... HowardArticle: 109234
> I need a new ISE machine and today our "regular PC" would > have a Pentium D 930 @ 3GHz > can I expect any speedup with a core2duo? with Athlon64? Not entirely representitive, but.. http://www.tomshardware.co.uk/cpu/charts.html?modelx=33&model1=432&model2=439&chart=188 Cheers, JonArticle: 109235
vits wrote: > Hi, > I came across these buses i2c ,ahb,apb.What is the difference between > them. i2c is an off-chip serial bus. AHB and APB are on-chip interconnects. AHB & APB are both part of the AMBA standard from ARM. Cheers, JonArticle: 109236
Zyan,
can you please send me a zip file with the following files
design.ngd
design.ucf
ngdbuild.log
map.log (or design.mrp)
par.log
I would like to take a look
Aurash
zyan wrote:
>I only used DIFF_SSTL18_II_DCI and SSTL18_II_DCI in bank 7. This satisfy the rules. But ISE didn't assign DIFF_SSTL18_II_DCI for the pins. It turned out to assign the default LVCOMS25 on those pin, which had violated the rules. It seems like I was not allowed to specify DIFF_SSTL18_II_DCI. So how should I fix this problem? Thanks.
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 109237
I got the following procedure from the mentioned reference design:
%LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd
MODULE.lpc INSTANTIATION_NAME
%LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd
FPGA_PROJECT.bit FPGA_PROJECT.prf
This takes about 1 minute compared to 8 minutes for the whole FPGA
design.
I made a conversion utility which converts from a standard Intel
HEX file to the .mem format ('addressed hex'). You can download
it from here:
http://diycalculator.pcl.at/images/a/a3/Hex2mem-1.0.tar.gz
Thanks again for the fast help!
Johannes
Kevin wrote:
> Yes, it can be run via commandline. In the ispLEVER help do a search
> for 'memedit', this is the memory initialization tool executable. In
> the search results select 'Running MEMEDIT from the Command Line' to
> open the MEMEDIT help page.
>
> Kevin
>
>
> Antti wrote:
>> Kevin schrieb:
>>
>>> Johannes,
>>>
>>> Lattice's current software, ispLEVER 6.0 does offer the ability to
>>> reinitialize your memory contents without recompiling your design.
>>> Using the Memory Initialization tool, accessed from the tools menu, a
>>> new, or modified memory file .mem can be written to the designs
>>> database file .ncd. After this is done all that needs to be rerun is
>>> the 'Generate Bitstream Data' process. This feature is only available
>>> for use on memory blocks that are implemented in the devices EBR blocks
>>> and created using the software's IPExpress module generation tool.
>> is the memory init available from commandline also?
>> the GUI tool is known to exist for some time, the commandline
>> bit file merging is far less documented
>>
>> Antti
>
Article: 109238Yes you can use other applications/code (ie libusb on linux) to download new config files. When I have looked at the board and ohm'd out different signals between the FX2, CPLD, FPGA, etc there are few connections between the FX2 and the FPGA. Mainly the JTAG signals (TDO, TDI, TMS, TCLK) are connected. To do any decent I/O transfer the FIFO data signals (slave FIFO or GPIF) would have to be wired to the CPLD or FPGA, which I believe they are not. Best I can tell it is only for simplified configuration, ie don't need an additional programming cable. If you google "USB FPGA" you will find many USB FPGA boards that provide USB I/O connectivity that you are looking for.Article: 109239
Dennis wrote: > Isaac Bosompem wrote: > >> You can get an IBM Thinkpad (I have a P3 1.13Ghz T23, very happy >> with it). These laptops have very good reputations. The newer >> models (T60) seems to have dropped the parallel port for the extra >> vent. But if you don't mind a used/slightly older model you can >> pick up the Thinkpad T42 which has a parallel port. Also >> considering that my ol' T23 was released in like 2001 and is still >> working without any defects is amazing! Built like tanks these >> laptops are. > > Go to www.ibm.com and click on IBM Certified Used Equipment in the > Shop for column. I picked up a T30 with serial and parallel ports > that I am very happy with for about $500. It looked like new. I took a look there and none of the models seem to include a floppy. Also, none describe the presence or absence of serial and parallel ports. I have heard horror stories about the parallel port compatibility in IBMs, which I need for my laser printer. Any comments? -- Some informative links: news:news.announce.newusers http://www.geocities.com/nnqweb/ http://www.catb.org/~esr/faqs/smart-questions.html http://www.caliburn.nl/topposting.html http://www.netmeister.org/news/learn2quote.html -- Posted via a free Usenet account from http://www.teranews.comArticle: 109240
chris.felton@gmail.com schrieb: > Yes you can use other applications/code (ie libusb on linux) to > download new config files. When I have looked at the board and ohm'd > out different signals between the FX2, CPLD, FPGA, etc there are few > connections between the FX2 and the FPGA. > > Mainly the JTAG signals (TDO, TDI, TMS, TCLK) are connected. To do any > decent I/O transfer the FIFO data signals (slave FIFO or GPIF) would > have to be wired to the CPLD or FPGA, which I believe they are not. > Best I can tell it is only for simplified configuration, ie don't need > an additional programming cable. > > If you google "USB FPGA" you will find many USB FPGA boards that > provide USB I/O connectivity that you are looking for. JTAG is sufficient, it always is on all FPGAs that have internal JTAG TAP access primitives FX2 can use the JTAG pins for synced serial comm with the cores in the FPGA. peak transfer speed should be possible at few megabit/sec when the transfer loop is fully optimized in the FX2 code AnttiArticle: 109241
Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> wrote in news:eevb3n02d2p@news4.newsguy.com: > Unfortunately, my company has a "permitted" set of laptop models If you have special needs, any IT department should recognize it and let you get what you need. -- Scott Reverse name to replyArticle: 109242
who can give me source code about ISA BUS ?thxArticle: 109243
lzh08 schrieb: > who can give me source code about ISA BUS ?thx http://www.mesanet.com/ browse there, look into all ZIP archives I think there are some ISA related stuff inside AnttiArticle: 109244
Hi all. Please, what are main steps to try programming in C++ on uBlaze ? It's mandatory use a XilKernel (little Kernel) provided by Xilinx? In fact some built-in C++ command like new are unavailable... Please refer here any other possible suggestion and any issues using C++ in uBlaze environment. Thanks in advance. Cheers, Al.Article: 109245
Chris Carlen wrote:
...
> Unfortunately, my company has a "permitted" set of laptop models.
...
Is that horseshit still going around? Many many years ago, I was part of
a team developing a demonstration interactive on-demand cable TV system.
My company even bought a cable TV company to serve as a test bed. We
needed a computer to be the heart of it, and the most suitable for our
purpose was a Data General Nova 1200. At the time, computers were
considered the province of the Data Processing Department. They had a
(small) approved list and the Nova wasn't on it.
In exasperation, I said to my boss that if we needed two 5,000 scopes,
we'd have the order signed in an hour, but one 10,000 computer, also a
piece of lab equipment, was out of bounds. My remark got kicked up three
management levels*, and the next meeting of the board of directors
agreed that lab equipment didn't come under Data Processing's edict.
Jerry
_________________________________________
* Me. Group leader. Lab director (to whom I griped). VP Research, a
member of the Board. The board itself.
--
"The rights of the best of men are secured only as the
rights of the vilest and most abhorrent are protected."
- Chief Justice Charles Evans Hughes, 1927
ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
Article: 109246On 2006-09-22, Johannes Hausensteiner <johannes.hausensteiner@pcl.at> wrote: > I got the following procedure from the mentioned reference design: > > %LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd > MODULE.lpc INSTANTIATION_NAME > > %LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd > FPGA_PROJECT.bit FPGA_PROJECT.prf Is it just me or are the file extensions, commands and options very similar to the ones used in Xilinx' ISE flow? /AndreasArticle: 109247
Thanks. I overlooked that part. This is extremely frustrating because the installer said everything installed OK. kjhales GaLaKtIkUs=99 wrote: > MIG runs only on windows, on MIG's page they say that in future > versions Linux will be supported. > I also faced this problem. I use VMWARE only for this!!!! > > Cheers > Mehdi > > kjhales@catalpatechnology.com wrote: > > I cannot get the MIG to work in Core Generator. I've written Xilinx, > > but hope I can get a faster answer here. > > > > I used the Tools->Updates Installer in coregen to install MIG. > > Help->About now says I have IP updates 1 and MIG 1.6 installed. It also > > says I have MIG 1.5 installed. > > > > Xilinx says to list available cores by function, select > > Memories&Storage Elements, then select MIG. However MIG simply does not > > appear as an option. Does anyone have any idea why the insallation > > (apparantly) failed? I am running under Fedora 4, and using ISE 8.1 sp > > 3. > >=20 > > Thanks > > kjhalesArticle: 109248
All my bad components had been delivered in tape. I had noproblem with parts delivered in sticks. Is there any reason for tape-delivered parts to worse ? My bad components seemed to be older. Is there a way to derive fabrication date from markings, for example XC4010E PC84CKM0141 A2083146A 3C ? Thanks for any help JAGArticle: 109249
Andreas Ehliar schrieb: > On 2006-09-22, Johannes Hausensteiner <johannes.hausensteiner@pcl.at> wrote: > > I got the following procedure from the mentioned reference design: > > > > %LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd > > MODULE.lpc INSTANTIATION_NAME > > > > %LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd > > FPGA_PROJECT.bit FPGA_PROJECT.prf > > Is it just me or are the file extensions, commands and options very > similar to the ones used in Xilinx' ISE flow? > > /Andreas no, its not you. in all file name extensions in both Lattice and Xilinx flows *.N?? the N stands for NeoCad it is surprising how much similarity there is. what I found surprising was that even the file format that holds the actual location of fuses in the bitstream is inherited from NeoCad, that both by Lattice and Xilinx Antti
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