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I have a single input clock in my design, and it is used to drive clock enables to the entire design. The clock enables are user-programmable as a divider function of the input clock frequency. A second clock is generated on-chip by a hand-coded divider circuit (not a DCM), and this clock needs to be declared as synchronous to the input clock. Additionally I want the tool to time paths between flops across these synchronous domains - it is not doing this by default. I understand it is not a recommended design practice to build your own divider, we're supposed to use a DCM, but we are prototping an ASIC, and the divider is a part of that logic that needs to be proto-typed. Does anyone know how I can tell the ISE tool that: (1) these two clocks are synchronous (2) the tool should minimize the skew between these clocks, i.e. balance the clock tree (3) the tool should time paths crossing the two synchronous clock domains Thanks.Article: 109001
Antti wrote: > Jim Granville schrieb: > > > betterone11@gmail.com wrote: > > > fpgaman wrote: > > > > > >>"http://www.latticesemi.com/products/intellectualproperty/latticemico32" > > > > finally - a 100% Eclipse-+GNU based SoC system with open-source RTL > that just works. > > Antti I worked before with the NIOSII and a price tag was on the tool. As I can see it here there is not much difference with the Lattice approach. Even if someone finds later a 3rd party low cost board and debugger you still need to buy the ispLEVER software for $595. Or is there a complete free solution with the LatticeMico32? ..richardArticle: 109002
rickman wrote: > Currently I wanted to look at how fast it might run if I redid it for a > current FPGA architecture using synchronous memories. I compiled it > for a Spartan 3 and got the speed up to 77 MHz using less than 10% of > an XC3S400 (315 slices). I am not impressed with the speed. I > expected a much larger increase and had hoped for operation at over 100 > MHz. I checked the timing analyzer output and the signal paths are > pretty much what I expected, no oddball logic generation and I got > carry chains where I wanted them. The slow paths have a few long route > times, so although it may approach 100 MHz with careful floorplanning, > I don't think this is worth the effort compared to the >> 100 MHz CPU > cores you can get from the FPGA vendors. This does not surprise me. Xilinx seems to have emphasized size over speed of Spartan as they update it. It is very difficult to get Microblaze to run at 100MHz in a Spartan 3E, so 77MHz without trying is about what I would expect. Alan NishiokaArticle: 109003
zohair wrote: > I have a single input clock in my design, and it is used to drive clock enables to the entire design. The clock enables are user-programmable as a divider function of the input clock frequency. A second clock is generated on-chip by a hand-coded divider circuit (not a DCM), and this clock needs to be declared as synchronous to the input clock. Additionally I want the tool to time paths between flops across these synchronous domains - it is not doing this by default. > > I understand it is not a recommended design practice to build your own divider, we're supposed to use a DCM, but we are prototping an ASIC, and the divider is a part of that logic that needs to be proto-typed. > > Does anyone know how I can tell the ISE tool that: (1) these two clocks are synchronous (2) the tool should minimize the skew between these clocks, i.e. balance the clock tree (3) the tool should time paths crossing the two synchronous clock domains > > Thanks. ====================== If you use a clock to drive a divider (let's hope it is a synchronous divider) then the output of this divider will be one clock-to-Q flip-flop delay delayed from the original clock. Only a DCM or PLL can do anything about that fact. The question is, can you live with two clock domains, one of which is delayed from the other? At best, the delay cuts into your timing margin, and thus lowers the max possible clock frequency. At worst, a flip-flop driven by the late clock receives input data from a flip-flop driven by the early clock. That can (will) create a hold-time violation, which in turn can lead to a race condition and upset your circuit hopelessly, and it would do that at any clock frequency, even a very low one. So, beware of mixing clock domains, even in an ASIC. There are tricks around this, like clocking on the opposite clock dge, but they require a good undestanding of all the timing relationships. Peter Alfke, Xilinx ApplicationsArticle: 109004
S "Austin Lesea" <austin@xilinx.com> ??????:eeef5i$i5l4@cnn.xsj.xilinx.com... > Mike, > > Heavens No! The S3 family is very alive, and doing very well. Now that > the Spartan Business Group is well into providing a large part of the > consumer electronics programmable logic, and because of their previous > business models, and their original customers, they plan on having a > longer product life than the Virtex group. > > Spartan still has its original family member, based on the 4KXLA device > family, as well as a 5V 4K device! Still shipping. > > Even with the new Spartan 3E, and perhaps more new Spartan parts, there > is no plan to stop selling what is probably the most successful FPGA out > there (>>10 million shipped, and still shipping strong). > > Xilinx in general obsoletes very few products. The 2000 family was > available for 20 years. The 3000 family is still available (some family > members). Selected members of the 4, 4E, 4X, 4XL, 4XLA families are > discontinued, but not all. 4XV was completely discontinued, as Virtex > was a better solution, and cost less (so 4XV never 'took off' anyway). > Virtex, Virtex E, Virtex II, Virtex II Pro, Virtex II Pro-X, Virtex 4 > are all doing very well, and we have no plans to obsolete any of them. > > Old version of software are archived so that people with old parts may > continue to support those products. > > Of course, we recommend only those parts for new designs which are > prominently displayed on the documentation web pages, and those that are > not recommended are also so indicated. > > AustinArticle: 109005
Peter Alfke wrote: > And they are available, as I posted yesterday > (funny, neither praise nor outrage in the ng. Everyone asleep?) Well, we can't have that, so ... congratulations! I look forward to having a chance to play with them, but it will not happen until the XC5VLX50 is supported by the ISE WebPACK and the ML501 becomes available. LUT6s are nice and will help combinational-heavy designs. The logic functions in the DSP may come in handy if they are flexible enough (haven't checked yet). The biggest surprise in the Virtex-5 though was the new routing network. I can only hope that the more regular structure translates into shorter P&R times. Oh, and kudos for the ML501. The specs looks outstanding and I'm really happy to see a DDR2 SODIMM slot and just just some soldered down part. Regards, TommyArticle: 109006
What id the defference between CPLD and FPGA ? Except Speed ?Article: 109007
Ali wrote: > What id the defference between CPLD and FPGA ? > > Except Speed ? > CPLD's smaller than FPGA's CPLD's non-volatile, FPGA's need to be programmed on power up CPLD's take longer to program, FPGA's can be programmed quickly The above is just my impression. I've only worked with FPGA's. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109008
hi Manufacturers claim that SRAM based FPGAs can be used in state of the art products and perform well over a long period of time, but my experience negates that. Two years ago, we developed a "real time face recognition system" using xilinx XC2V6000 on AVNET development kit and delivered the final working product to end user; Who Recently came up with a complaint that the product is not functioning properly. Our technical staff identified that the DCM output (2X clock) is no more in synch with other clocks on the board. same old bitstream was working when we changed the board , and we concluded that the board is faulty. The faulty board was again working perfectly fine when we used phase shifted DCM output clock. (CLK2X180_OUT) 1-- Maximum working life of FPGA based products is dependant on the device and oscillator characteristics? 2-- What if the same problem arise in commercially manufactured product (whose millions of pieces have been sold) ? any comments from more experienced users?? regards MHArticle: 109009
Hi Austin,
I am currently working with an avnet board. It is based on V4LX60.
Prviously i have worked with a development boards from ARM. Compared to
that the support for this board was very poor. Also the build quality
was poor. Some switches are showing contact problems. Also the parallel
cable IV from Xilinx was also found to giving prolems. Its because the
quality of the ribbon cable is very poor we replaced it two times. But
they are charging 8$ for that. Also configuring the avnet board for
programming and normal operation is very tricky business. We need to
change 5 jumpers and the ribbon cable each time. I found that very
intresting comparade to a single jumper setting in two stack of ARM
boards.
Sumesh V S
Austin Lesea wrote:
> Sumesh,
>
> I think that there are a number of folks who post here who provide
> hardware. I am sure they will reply to this posting (after all, they
> are in the business of providing pcbs with Xilinx parts on them that do
> useful things).
>
> A good inexpensive source is: http://digilentinc.com for the small stuff
> (Spartan).
>
> For the bigger parts, there is:
>
> http://www.xilinx.com/xlnx/xebiz/onlinestore.jsp?BV_SessionID=@@@@0352022448.1158692340@@@@&BV_EngineID=cccfaddikmdkkhhcefeceihdffhdfjf.0
>
> (see development boards)
>
> and
>
> Avnet and Nu-Horizons have a ton of pcbs.
>
> Austin
Article: 109010On 19 Sep 2006 20:58:07 -0700, "Peter Alfke" <alfke@sbcglobal.net> wrote: > >zohair wrote: >> I have a single input clock in my design, and it is used to drive clock enables to the entire design. The clock enables are user-programmable as a divider function of the input clock frequency. A second clock is generated on-chip by a hand-coded divider circuit (not a DCM), and this clock needs to be declared as synchronous to the input clock. Additionally I want the tool to time paths between flops across these synchronous domains - it is not doing this by default. >> >> I understand it is not a recommended design practice to build your own divider, we're supposed to use a DCM, but we are prototping an ASIC, and the divider is a part of that logic that needs to be proto-typed. >> >> Does anyone know how I can tell the ISE tool that: (1) these two clocks are synchronous (2) the tool should minimize the skew between these clocks, i.e. balance the clock tree (3) the tool should time paths crossing the two synchronous clock domains >> >> Thanks. >====================== >If you use a clock to drive a divider (let's hope it is a synchronous >divider) then the output of this divider will be one clock-to-Q >flip-flop delay delayed from the original clock. Only a DCM or PLL can >do anything about that fact. >The question is, can you live with two clock domains, one of which is >delayed from the other? > >At best, the delay cuts into your timing margin, and thus lowers the >max possible clock frequency. >At worst, a flip-flop driven by the late clock receives input data from >a flip-flop driven by the early clock. That can (will) create a >hold-time violation, which in turn can lead to a race condition and >upset your circuit hopelessly, and it would do that at any clock >frequency, even a very low one. >So, beware of mixing clock domains, even in an ASIC. >There are tricks around this, like clocking on the opposite clock dge, >but they require a good undestanding of all the timing relationships. Not necessarily true. The standard solution in an ASIC is to tell your clock tree synthesis tool the structure of your clock divider and let it balance the clock for you. There are some CTS tools which are really good in the sense that they can understand pretty complicated clock generation schemes ie not only straight dividers but a counter which generates clocks at different edges etc (500 MHz to 10, 20, 50, 100 MHz clocks etc) and move all the necessary registers in the clock tree to get a nice balanced clock tree. Even if your CTS doesn't support this automatically you can get it done manually after CTS. Another issue with your description is that any STA tool worth its salt would trace both source and receiver clocks and tell you if you're hitting any of these problems which is necessary to do even with no divided clocks. Of course in an FPGA things are more complicated as the clock tree is already generated and clk->Q delays are quite a bit worse than an ASIC at the same process.Article: 109011
betterone11@gmail.com schrieb: > Antti wrote: > > Jim Granville schrieb: > > > > > betterone11@gmail.com wrote: > > > > fpgaman wrote: > > > > > > > >>"http://www.latticesemi.com/products/intellectualproperty/latticemico32" > > > > > > finally - a 100% Eclipse-+GNU based SoC system with open-source RTL > > that just works. > > > > Antti > > I worked before with the NIOSII and a price tag was on the tool. As I > can see it here there is not much difference with the Lattice approach. > Even if someone finds later a 3rd party low cost board and debugger you > still need to buy the ispLEVER software for $595. > Or is there a complete free solution with the LatticeMico32? > ..richard http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter.cfm look at the list of supported devices, if you use any of them then you can use the free ispLever starter and do not need to pay a dime. I havent looked at the debugger yet, but all the rtl for the jtag-debug is open so it wouldnt be so hard to make a open-source debugger if there isnt any solution yet. AnttiArticle: 109012
vssumesh wrote: >>Peter Alfke wrote: >> >>>Vessumesh, if you refuse to answer specific helpful questions, then I >>>suggest you figure this out yourself, and do not bother this newsgroup. >>>Peter > > Sorry Peter, but i did not mean that. Sorry for the confusion. > I am using v4LX60 for my design. And there is a requirement of adding > two 37 bit no and doing some combinational logic based on that. The > total time is 20ns. The adder is taking very little time, the full > logic itself is taking around 4ns delay. But the main problem is with > routing delay. I forgot to tell you that it is a block RAM based > design. And it uses 128 BRAM frm v4lx60(implemented a 16 port RAM). > Also it uses the block RAMS in a scattered manner. So now i have placed > this block in the central region. So the last routing to the block > RAMis taking lot of delays. > In the previous version there was no combinational logic after the > adder and i got the timig correctly. But not now. > What i was asking is to add registers to latch the output of adder.I > thought like it would be good for the PAR to see two paths insted of 1 > path from a source FF to destination FF. Also Ray there is 32*16 such > signals. Is it possible to manually route all those signals. I think > the pipeling is not possible since this is part of a pipeline stage of > a processor. Which expects the result in the same cycle. So pipelining > is not an option. > >>It isn't the carry chain causing the problem. The problem comes about >>from using many levels of logic (ie the signal goes through lots of >>LUTs) between the flip-flops plus the propagation delay associated with >>the carry chain. > > Ray i was asking that if we brake the above long line into separate > parts using the +ve and -ve edge of the clocks is it possible to help > tool for a better PAR. > Thanks and regards > Sumesh V S > What are the logic you do after the addition? If the logic is any related to the carry-out of the addition, I tend to extend the carry-chain with more logic instead of doing it after the addition. It's easy to do AND/OR boolean expression using the carry-chain. I would also look at the synthesis schematics to see if the design generated by the synthesis tool is correct. Sometimes just rewrite the RTL can improve both area and speed. Also since routing is a big issue, maybe trying to make the design smaller might improve routing delays. But without specific details on the design, I can only give you very rough tips. You might also try to run the xplorer tool and see if that will give you some more speed. The result from different runs within xplorer can vary up to 20%. GöranArticle: 109013
Ali schrieb: > What id the defference between CPLD and FPGA ? > > Except Speed ? This is a FAQ. Indeed its also a FWAQ (Frequently Wrong Answered Question). http://groups.google.de/groups?as_q=fpga+cpld+difference&as_ugroup=comp.arch.fpga&as_uauthors=andraka (I choose one autor out of the regulars, who knows what he's writing. If you like, you should read all messages found with http://groups.google.de/groups?as_q=fpga+cpld+difference ) bye ThomasArticle: 109014
This may be the result of a silicon mask change that came in. Contact your FAE and they should be able to advise in more detail. I believe that for customers that need this feature there may be a special order code to use. John Adair Enterpoint Ltd. mh wrote: > hi > > Manufacturers claim that SRAM based FPGAs can be used in state of the > art products and perform well over a long period of time, but my > experience negates that. > > Two years ago, we developed a "real time face recognition system" using > xilinx XC2V6000 on AVNET development kit and delivered the final > working product to end user; Who Recently came up with a complaint that > the product is not functioning properly. Our technical staff identified > that the DCM output (2X clock) is no more in synch with other clocks on > the board. same old bitstream was working when we changed the board , > and we concluded that the board is faulty. > > The faulty board was again working perfectly fine when we used phase > shifted DCM output clock. (CLK2X180_OUT) > > > > 1-- Maximum working life of FPGA based products is dependant on the > device and oscillator characteristics? > > 2-- What if the same problem arise in commercially manufactured product > (whose millions of pieces have been sold) ? > > > any comments from more experienced users?? > > > regards > MHArticle: 109015
We had specified IOSTANDARD = DIFF_SSTL18_II_DCI in the UCF file. We got this type of error during place and route for several pins: ERROR:Place:311 - The IOB DDR_DQS<1> is locked to site IOB_X0Y5 in bank 7. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. It was found that the IOSTANDARD created by ISE was LVCOMS25 instead of the desired DIFF_SSTL18_II_DCI. We were using ISE8.1i and Virtex-4 XC4VFX60. Please advice. Thanks.Article: 109016
Hi, Does anybody know the internal structure of a Lattice .bit file? I do a CPU design including RAM and ROM for the CPU inside the FPGA. I am currently working on the firmware and every time I make a new version of the CPU program I have to integrate it into ispLEVER and recompile the whole FPGA to generate the .bit file, which takes about 8 minutes on my PC, which is a real pain. Is there any way to insert the contents of the ROM (implemented as EBR blocks) into the .bit file directly? Or is there any other way to do this? I am using a LFECP33E chip on an "HPEmini" development board. Thanks a lot, JohannesArticle: 109017
Johannes Hausensteiner schrieb: > Hi, > > Does anybody know the internal structure of a Lattice .bit file? I > do a CPU design including RAM and ROM for the CPU inside the FPGA. > I am currently working on the firmware and every time I make a new > version of the CPU program I have to integrate it into ispLEVER and > recompile the whole FPGA to generate the .bit file, which takes > about 8 minutes on my PC, which is a real pain. > Is there any way to insert the contents of the ROM (implemented as > EBR blocks) into the .bit file directly? > Or is there any other way to do this? > I am using a LFECP33E chip on an "HPEmini" development board. > > Thanks a lot, > > Johannes there is a network reference design at lattice website with Z80 cpu a networking stuff, I think it includes some script to update the bt file as well. AnttiArticle: 109018
Well ... the message is pretty clear I think ... > We got this type of error during place and route for several pins: ERROR:Place:311 - The IOB DDR_DQS<1> is locked to site IOB_X0Y5 in bank 7. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. "Other incompatible IOBs may be locked to the same bank," Well ... If you have a IOB in the same bank with a io standard requiring 2.5V voltage that would be bad. So check the IO standard for all the other pins of the same bank. They _at_ least should be set to some IO standard using a 1.8v vccio. "may be illegally locked to a Vref site." If you read the User Guide about SelectIO and the part about DIFF_SSTLII standard, you should know that the vref pins must be connected to the ... vref ... So obviously you can't use them as data/dqs pins. Check that your board doesn't do that. SylvainArticle: 109019
Thanks. I only have 2 types of IOSTANDARD in the same bank, SSTL18_II_DCI and DIFF_SSTL18_II_DCI. Both requires 1.8V. However, it was found that ISE had assigned LVCOMS25 to the pin that I had specified to be DIFF_SSTL18_II_DCI. This ended up with both 2.5V and 1.8V in the same bank. How can I fix this problem? Thanks.Article: 109020
Hi, Thank you for your hint. Unfortunately I am not able to find the mentioned reference design. Can you provide a link? Thanks again, Johannes Antti wrote: > Johannes Hausensteiner schrieb: > >> Hi, >> >> Does anybody know the internal structure of a Lattice .bit file? I >> do a CPU design including RAM and ROM for the CPU inside the FPGA. >> I am currently working on the firmware and every time I make a new >> version of the CPU program I have to integrate it into ispLEVER and >> recompile the whole FPGA to generate the .bit file, which takes >> about 8 minutes on my PC, which is a real pain. >> Is there any way to insert the contents of the ROM (implemented as >> EBR blocks) into the .bit file directly? >> Or is there any other way to do this? >> I am using a LFECP33E chip on an "HPEmini" development board. >> >> Thanks a lot, >> >> Johannes > > there is a network reference design at lattice website with Z80 > cpu a networking stuff, I think it includes some script to update > the bt file as well. > > Antti >Article: 109021
For those who have the same problems with XPS 8.2i to understand the tutorials which can be found in the internet that use XPS 6.x: There's a tutorial which shows step by step the custom peripheral import in XPS 8.1i which is similar to XPS 8.2i. http://www.eecs.wsu.edu/~jamie/research/designs/howto/EDK8.1/add_custom_ip.htm Regards, Peter Peter Kampmann wrote: > Hi everyone, > > after I have imported my custom peripheral into XPS 8.2i, I added the > Design to my System (XC2VP30). > The custom peripheral should be attached to the PowerPC using the > Onchip peripheral Bus, which is created using the Create/Import Custom > Peripheral Wizard. > > I download my Design to the board with no errors. > When I now try to run a C++ File in XPS SDK by pressing the run Button, > the XMD exits with the error: > "Failed Loading Project, Check if MHS/MSS files are correct > (Errors ocurred while creating Hardware System) > Initialization Failed: E02 Failed to load XMP file" > > When I use the "manual" way: open XMD in Command Shell, connect ppc hw > -> dow file.elf -> con. > The xmd tells me the processor is running, but I get not the results > that I expect to see (outputs on RS232). > I open the XMD Debugger and the program rests in the first line of the > code with no further debugging possible. > > I get this error when I connect my custom peripheral to PPC, when I use > the MicroBlaze, I get no errors. > I assume this might have something to do with the address space of the > custom peripheral. > In the address tab on the right hand side of the XPS Gui I tried to set > a address space manually, for example from 0x4200000 to 0x4200ffff. > I also tried the "generate address" button, I get the message that > "address generation is only supported for single processor desings". > But I need both processors in a next step and I just tried to delete > one of the ppcs in the design, which leads to more errors. > At last I tried to simply leave my custom peripheral without address > space, as some of the components in the address tab also do not seem to > have one. > > So has anybody a solution for my problem? How do I succesfully connect > my custom peripheral to the PPC? > > Thanks and Regards, > PeterArticle: 109022
Johannes Hausensteiner schrieb: > Hi, > Thank you for your hint. Unfortunately I am not able to find the > mentioned reference design. Can you provide a link? > Thanks again, > > Johannes > > Antti wrote: > > Johannes Hausensteiner schrieb: > > > >> Hi, > >> > >> Does anybody know the internal structure of a Lattice .bit file? I > >> do a CPU design including RAM and ROM for the CPU inside the FPGA. > >> I am currently working on the firmware and every time I make a new > >> version of the CPU program I have to integrate it into ispLEVER and > >> recompile the whole FPGA to generate the .bit file, which takes > >> about 8 minutes on my PC, which is a real pain. > >> Is there any way to insert the contents of the ROM (implemented as > >> EBR blocks) into the .bit file directly? > >> Or is there any other way to do this? > >> I am using a LFECP33E chip on an "HPEmini" development board. > >> > >> Thanks a lot, > >> > >> Johannes > > > > there is a network reference design at lattice website with Z80 > > cpu a networking stuff, I think it includes some script to update > > the bt file as well. > > > > Antti > > http://www.latticesemi.com/products/intellectualproperty/ipcores/trispeedethernetmediaacce/trispeedethernetmacdemofo.cfm AnttiArticle: 109023
zyan wrote: > Thanks. > > I only have 2 types of IOSTANDARD in the same bank, SSTL18_II_DCI and DIFF_SSTL18_II_DCI. Both requires 1.8V. However, it was found that ISE had assigned LVCOMS25 to the pin that I had specified to be DIFF_SSTL18_II_DCI. This ended up with both 2.5V and 1.8V in the same bank. How can I fix this problem? > > Thanks. Did you use a differential output buffer for DQS ?Article: 109024
HI,
Can anyone tell me the tools that support ECO (Engineering Change
Order).
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