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"rickman" <gnuarm@gmail.com> writes: > I checked on the web page for the Xilinx tools and this is what I > found... > > "The memory requirements for both RAM and hard disk space will vary > depending on your target device family and size as well as the unique > characteristics of your design. " > > Anyone have an idea of how much hard drive space is needed for the full > toolset? I don't get why they don't provide some sort of figure either > a base or a maximum. I guess if you have to ask, you don't have enough > space? > My current 8.2 setup is (as reported by Windows Explorer): ISE: 2.58GB EDK: 785MB I removed Virtex-5 support for now to save space. Apparantly, ISE consists of over 52,000 files! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 108851
chadland@online.no wrote: > I have a couple of questions regarding VHDL and FPGAs as I am starting > a project on them shortly0. Before I start I would like to apologize > for my lack of knowledge on them. I am a software developer not a > hardware so you might have to take this into consideration when > explaining. > > I know VHDL is a hardware description language, but what is the biggest > challenge when writing code in VHDL compared to for example C. > Firstly, don't link HDL and software in this Newgroup. HDL purists are very fanatical about maintaining a distinction between the two. However, you do write VHDL in text files. Oh, and not all HDL's are "written". The biggest challenge developing with VHDL is it's verbose nature (which stems from it's root language: ADA). If you have written in C and find that language easy, may I suggest Verilog instead of VHDL. BTW VHDL is the favourite with the US/UK Military. Next challenge for most software developers is coming to terms with the parallel nature of a HDL. > Is it writing your code as close to elemtary logic as possible(that > will result in efficiency)?? Not an easy question... As a programmer maybe this answer will better fit you: Not all compilers produce efficient object/machine code from the same source code. Also, describing your system with elementary VHDL behaviours (in most cases today) will waste resources on the target programmable logic device. Thus: A 8Kbit memory module described in HDL would be portable between vendor silicon, but resource hungry. A more resource efficient implementation is gained using vendor specific HDL functions, that in turn use existing PLD onchip memory (BlockRam SelectRAM etc). > Or is it perhaps timing challenges? > Timing challenges are the most involved aspect of digital electronics, no less the PLD field. Especially when autorouting results in domain skew on your system (synchronisation) clock. > As you can see I am pretty fresh and I will dig down in VHDL literature > pretty soon but I would appreaciate a little input from people who are > experienced in it before I start. > I would suggest a $99-$199 dev kit from Altera or Xilinx. They both have free downloadable tools: http://www.altera.com/products/devkits/partners/kit-alt-live-design.html http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US > Cheers, > ChrisArticle: 108852
Craignell family are are a set of DIL style 5V tolerant modules based on Spartan-3E. Mainly aimed at obsolete component replacement they can also be used for hobby electronics due to their mechanical pitch. I should have said there are actually 3 members of this family to release supporting DIL28, DIL32 and DIL40. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Simon" <news@gornall.net> wrote in message news:2006091710251416807-news@gornallnet... > On 2006-09-17 01:03:05 -0700, "John Adair" <g1@enterpoint.co.uk> said: > >> Did you mean the Tarfessock1? >> >> We have slipped a little due to the amount of customer work that has >> come in over the summer but will like be available in approximately 3-4 >> weeks. Our main limitation is the arrival of the cardbus frames and >> covers which we are waiting for. > > No, I meant the Darnaw1 (S3S1200E module, yes ?) - it's for a different > project than the V4FX board :-) > >> Darnaw1 and Craignell1/2 are roughly on the same timescale. > > I'm assuming the casual mention of a completely unknown (at least to me, > and I can't find it on your site :-) board is a marketing ploy designed to > tease out the question: "What is Craignell1 and 2 ?". Ok then [grin], > dish! > > Simon >Article: 108853
Yuri schrieb: > Hi guys, > Now my recursive mutex stopped to work. I guess I will have to > patch the patch? :-) Hi, adding "else break;" after line 206 in mutex.c should fix it. If the mutex is of the RECURSIVE type and owned by the calling thread, the while loop is immediately left. Regards AndreasArticle: 108854
I am just finishing my verilog code on a project.And I am absolutely new to this field. And i got no clue how to do a synthesis and how to use the software I get. I got Xilinx edk 7.1 and xilinx ise7.1 on a linux PC. but i cant find the XPS stuff as the user guide says.Article: 108855
Why not run through the tutorials? Under 'Help'. ;-) HTH, Syms. "Tea" <windingson@gmail.com> wrote in message news:1158591912.186445.180210@b28g2000cwb.googlegroups.com... >I am just finishing my verilog code on a project.And I am absolutely > new to this field. > And i got no clue how to do a synthesis and how to use the software I > get. > I got Xilinx edk 7.1 and xilinx ise7.1 on a linux PC. > but i cant find the XPS stuff as the user guide says. >Article: 108856
.....the problem is i cant find the executable file. Btw, do I need ISE for synthesis? is EDK enough? Symon wrote: > Why not run through the tutorials? Under 'Help'. ;-) > HTH, Syms. > "Tea" <windingson@gmail.com> wrote in message > news:1158591912.186445.180210@b28g2000cwb.googlegroups.com... > >I am just finishing my verilog code on a project.And I am absolutely > > new to this field. > > And i got no clue how to do a synthesis and how to use the software I > > get. > > I got Xilinx edk 7.1 and xilinx ise7.1 on a linux PC. > > but i cant find the XPS stuff as the user guide says. > >Article: 108857
"alterauser" <fpgaengineerfrankfurt@arcor.de> wrote: >Can't you use a multi cycle constraint ? > No, I really need the answer in the same cycle and there is no way around it. However, if I use a speed grade 5 device instead, the circuit will meet timing. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 108858
Cudos to lattice on the "inexpensive" SERDES and the plentiful memory! Serious contention for designs previously out of reach. http://tinyurl.com/hadhe or http://www.latticesemi.com/corporate/newscenter/productnews/2006/r060918new90nmecp2mfpgasf.cfm?jsessionid=ba30ded8ae34$3F$3F$1Article: 108859
John_H schrieb: > Cudos to lattice on the "inexpensive" SERDES and the plentiful memory! > Serious contention for designs previously out of reach. > > http://tinyurl.com/hadhe > > or > > http://www.latticesemi.com/corporate/newscenter/productnews/2006/r060918new90nmecp2mfpgasf.cfm?jsessionid=ba30ded8ae34$3F$3F$1 WAU - the XP2 will also have SERDES (but comes maybe later this year), but having the super ECP2 lowcost family extended with 3GBs SERDES was defenetly a good move !! AnttiArticle: 108860
On Mon, Sep 18, 2006 at 08:26:09AM -0700, Tea wrote: > .....the problem is i cant find the executable file. I assume that you are running Linux. Replace $XILINX by the path where you installed ISE to, $XILINX_EDK by that for the EDK. Enter the following . $XILINX/settings.sh . $XILINX_EDK/settings. Now either "ise" to start ISE or "xps" to start Xilinx Platform Studio. > Btw, do I need ISE for synthesis? Yes. > is EDK enough? No. -- GPG-Key 1024D/E32C4F4B | www.gnupg.org | http://enigmail.mozdev.org Fingerprint = 9C03 86B5 CA59 F7A3 D976 AD2C 02D6 ED21 E32C 4F4B Mit freundlichen Gruessen | Kun afablaj salutoj (www.esperanto.org) May the tux be with you. :wq 73Article: 108861
Hello, Have anyone successfully implemented a working 10G Ethernet PCS in Virtex-II Pro devices using Xilinx XAPP775? If yes, were there any modifications in the PCS submodules? I understand that XAPP775 was written as a supplement to the RocketPHY chips. It appears that Xilinx no longer supports this application note, due to the fact that RocketPHY chips are no longer in production. However, I believe that there is value in XAPP775, as it can be used for non-RocketPHY chips (e.g. AMCC, Broadcom, and Marvell PHYs). Thanks, -MarkusArticle: 108862
Hello, I have a question concerning the maximum sample rate using Quartus' Signal Tap, I've heard that the maximum rate is 270Mhz, is that correct? Also, if you wanted to use a higher sample clock would you simply use a PLL to generate the clock and then route the clock to an output pin, which I think is a requirement of Signal Tap? If anyone has some experience using Signal Tap, could you share your thoughts on the matter. Thanks, joeArticle: 108863
Being former employees of ST Microeletronics and from the size of the device, and the number of EPROM/RAM sockets I would hazard a guess that it is a INMOS (give credit where credit is due) transputer, T801 but not the standard TRAM module. Any body from the transputer recognize it? Derek ziggy wrote: > Ok, so a link to these people came across my mail box today. and its > supposedly a Open Source 64bit sparc core.. > > Anyone that has seen this before want to comment? > > Oh, and the little piece of hardware they show on their pages, anyone > know what that is and where it came from?Article: 108864
Nico Coesel wrote: > "alterauser" <fpgaengineerfrankfurt@arcor.de> wrote: > > >Can't you use a multi cycle constraint ? > > > > No, I really need the answer in the same cycle and there is no way > around it. However, if I use a speed grade 5 device instead, the > circuit will meet timing. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U op www.adresboekje.nl Any chance that the sign doesn't change on a given input? Hardwiring sign bits to 1 or 0 would help timing a lot vs. connecting them to the high order bit.Article: 108865
Antti wrote: > John_H schrieb: > > > Cudos to lattice on the "inexpensive" SERDES and the plentiful memory! > > Serious contention for designs previously out of reach. > > > > http://tinyurl.com/hadhe > > > > or > > > > http://www.latticesemi.com/corporate/newscenter/productnews/2006/r060918new90nmecp2mfpgasf.cfm?jsessionid=ba30ded8ae34$3F$3F$1 > > WAU - the XP2 will also have SERDES (but comes maybe later this year), > but having the super ECP2 lowcost family extended with 3GBs SERDES was > defenetly a good move !! The pricing I have gotten on the ECP2 line is attractive, but in the grand scheme of things I don't see where it is a significant difference with the other players in the field. I think that optimizing any given parameter in the FPGA market is a matter of timing. A couple of years ago Spartan 3s were the low cost chips, then when the Cyclone II parts came out they were a bit cheaper. Now that ECP2 parts are starting to show, they will be cheaper... until the Spartan 4/5 parts make it to the scene. If only there was something that actually distinguished the different families of parts!Article: 108866
Rick, Have you ever seen a high speed serdes and plenty of mem blocks on any of the low cost families of either Xilinx, Altera? I definitely believe that these features are distinguishing this family from the other players! Of course, I haven't seen anything from Xilinx or Altera yet that would prove the opposite, maybe you have... but don't want/can't share with us due to NDA's Regards, Luc On 18 Sep 2006 11:54:03 -0700, "rickman" <gnuarm@gmail.com> wrote: >Antti wrote: >> John_H schrieb: >> >> > Cudos to lattice on the "inexpensive" SERDES and the plentiful memory! >> > Serious contention for designs previously out of reach. >> > >> > http://tinyurl.com/hadhe >> > >> > or >> > >> > http://www.latticesemi.com/corporate/newscenter/productnews/2006/r060918new90nmecp2mfpgasf.cfm?jsessionid=ba30ded8ae34$3F$3F$1 >> >> WAU - the XP2 will also have SERDES (but comes maybe later this year), >> but having the super ECP2 lowcost family extended with 3GBs SERDES was >> defenetly a good move !! > >The pricing I have gotten on the ECP2 line is attractive, but in the >grand scheme of things I don't see where it is a significant difference >with the other players in the field. I think that optimizing any given >parameter in the FPGA market is a matter of timing. A couple of years >ago Spartan 3s were the low cost chips, then when the Cyclone II parts >came out they were a bit cheaper. Now that ECP2 parts are starting to >show, they will be cheaper... until the Spartan 4/5 parts make it to >the scene. > >If only there was something that actually distinguished the different >families of parts!Article: 108867
Hi, Have you looked at the release notes for the MPMC2 core? There are a few known issues there, which might be related to your problem, and which unfortunately I don't fully understand... I am myself debugging a read cycle and having problems as well. I tried 4 and 8-word reads and in both cases the last double-word never shows up on the PI_RdFIFO_Data bus. When I do a few read cycles in sequence, the result is even more confusing: some data is lost, some is late, etc... I haven't tried the latest MPMC2 release (8/31) yet, but I don't have much hope, as it doesn't seem from the release notes that they did any related changes... /Mikhail "ivo" <ivo@ideas.no> wrote in message news:ee9ed97.-1@webx.sUN8CHnE... > This is a follow-up from my previous discussion. ivo, "MPMC2 : npi issues" #, 31 Aug 2006 1:44 am </cgi-bin/forum?50@@.ee9e44c> > > I am now able to get addrAck back from the MPMC2, but it seems like the FIFO never dumps data to the DDR. After a number of acks (depending on the size of the FIFO) followed by WrFIFO_push the FIFO_almostfull signal is asserted and no more acks are received. The FIFO_almostfull signal never goes low again. > > Someone have an idea what is wrong ? I assume that my npi never gets prioritized by the arbiter, but my arbiter algorithm is quite simple(round robin). The PPC which is also attached onto the MPMC2 works as expected.Article: 108868
> I installed chipscope 8.1i instead of 8.2i. but It's the same. > Make sure you rebuild everything. If you work entirely in XPS environment do Hardware/Clean Hardware before rebuilding. /MikhailArticle: 108869
"Gabor" <gabor@alacron.com> wrote: > >Nico Coesel wrote: >> "alterauser" <fpgaengineerfrankfurt@arcor.de> wrote: >> >> >Can't you use a multi cycle constraint ? >> > >> >> No, I really need the answer in the same cycle and there is no way >> around it. However, if I use a speed grade 5 device instead, the >> circuit will meet timing. >> > >Any chance that the sign doesn't change on a given input? >Hardwiring sign bits to 1 or 0 would help timing a lot vs. >connecting them to the high order bit. No, unfortunately both inputs may be positive or negative. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 108870
Open Cores DDR controller uses 2 DCM's to generate the clocks.
clk -> dcm0 -> clock used for fddr to produce true + negative ddr clocks
feedback comes from true ddr clock
fddr has hard wired 01 inputs for true clock,
10 inputs for negative clock
clk -> dcm1 -> (0 clock) bufg1 -> clock used for all ddr related
internal logic
-> (270 clock) bufg2 -> clock used for fddr's for
DDR's data in lines
feedback comes from the output of bufg1
dcm0 has a tunable parameter, phase shift of 30 ps. I've moved this all
the way
to -530ps with no failure. It seems irrelevant.
I want to get rid of one of the DCM's, 2 seems excessive. Is it common
to use
an fddr to get a clock to the outside this way? That is, an fddr has
fixed inputs
(input0 <= '0', input1 <= '1') and so the fddr output is really just a
data selector,
when the input clock is low you get input0, when high you get output1. Why
not route the clock through to the outside directly?
I've tried hanging the DDR's clock off of bufg1 (still going through fddr)
but it doesn't work reliably, I get flaky data.
Where can I find info about clock generation issues, specifically
related to ddr.
I never would have come up with the scheme that seems to actually work in
this case. Is it possible to do with just one DCM?
Thanks--
Dave
--
David Ashley http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Article: 108871"rickman" <gnuarm@gmail.com> wrote in message news:1158605643.208484.113710@m7g2000cwm.googlegroups.com... > > The pricing I have gotten on the ECP2 line is attractive, but in the > grand scheme of things I don't see where it is a significant difference > with the other players in the field. I think that optimizing any given > parameter in the FPGA market is a matter of timing. A couple of years > ago Spartan 3s were the low cost chips, then when the Cyclone II parts > came out they were a bit cheaper. Now that ECP2 parts are starting to > show, they will be cheaper... until the Spartan 4/5 parts make it to > the scene. > > If only there was something that actually distinguished the different > families of parts! The ECP2 line is nice but not terribly remarkable. The ECP2M parts, on the other hand, blow past the Brand A and Brand X low-cost offerings on memory to logic ratios *and* are the first low-cost devices to include SERDES functionality and at *very* attractive per-channel power levels. My attention was attracted to the offering because of the memory. Adding PCI express would be quite a bonus for me.Article: 108872
I checked with our CPLD folks in Xilinx, and here is their answer: "Absolutely no planned obsolescence for XPLA3. We never made a widely circulated XPLA3 development board that we sold. We had a few hundred that we gave away. XPLA3 has gained significant volume, with design wins in handheld computers etc. It has also been designed in at a major consumer house. It will be around for quite a while. The single 3.3V power supply has been a big plus for it." Peter Alfke =============================== rickman wrote: > I am looking at using the XPLA3 in a new design and am having trouble > finding an evaluation board. So I started looking around and see that > Xilinx seems to be severely curtailing support of these parts. There > Xilinx no longer offers evaluation boards and I can't find many third > party boards that are still offered. > > On the bright side, when I did a search at Nuhorizons for XCR3128, I > got lots of hits. That alone would not give me confidence, but not > only did I get the XCR3128XL that I need to use, I found the XCR3128 > without the XL which is an even older part. If they are still selling > those parts, I guess I can expect to see the XCR3128XL around for quite > a while. > > The Coolrunner II may be a bit lower power, but the XPLA3 parts are > nearly as low power for our application and only require a single power > voltage. That makes them *more* power efficient. I just wish Xilinx > provided as much support for the XPLA3 parts as they do for the > Coolrunner II. > > Are there any advantages of the Coolrunner II parts that I am missing? > I see they have input hysteresis, but otherwise they seem pretty much > the same as the Coolrunner XPLA3.Article: 108873
Nico, I looked into this, and haven't heard back yet for the whole story. But, so far: V4 and V5 delay is flat (doesn't matter how many bits are used). S3, V2 and V2 Pro may be the only way to get fastest speed is to sign extend (but I am still checking). AustinArticle: 108874
Just curious, does Virtex4 has its own built-in configuration ROM? as in it will automaticaly has the chip configured on power up?
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