Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 109250

Article: 109250
Subject: Re: Lattice .bit file format
From: "Gabor" <gabor@alacron.com>
Date: 22 Sep 2006 07:04:15 -0700
Links: << >>  << T >>  << A >>

Andreas Ehliar wrote:
> On 2006-09-22, Johannes Hausensteiner <johannes.hausensteiner@pcl.at> wrote:
> > I got the following procedure from the mentioned reference design:
> >
> > %LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd
> > MODULE.lpc INSTANTIATION_NAME
> >
> > %LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd
> > FPGA_PROJECT.bit FPGA_PROJECT.prf
>
> Is it just me or are the file extensions, commands and options very
> similar to the ones used in Xilinx' ISE flow?
>
> /Andreas

This is not a secret.  The neocad people developed both tool sets.


Article: 109251
Subject: Re: X4000 bad configuration
From: "Gabor" <gabor@alacron.com>
Date: 22 Sep 2006 07:08:32 -0700
Links: << >>  << T >>  << A >>

Jacques GENIN wrote:
> All my bad components had been delivered in tape.
> I had noproblem with parts delivered in sticks.
> Is there any reason for tape-delivered parts to
> worse ?
> My bad components seemed to be older. Is there a
> way to derive fabrication date from markings,
> for example XC4010E PC84CKM0141 A2083146A 3C ?
>
> Thanks for any help
>
> JAG

The date code is after the package type on line 2,
in the above case 0141 or 41st week of 2001.

See answer record #1067

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067


Article: 109252
Subject: Re: Dell Laptop for Embedded Work
From: Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov>
Date: Fri, 22 Sep 2006 07:32:16 -0700
Links: << >>  << T >>  << A >>
Brad Griffis wrote:
> No, you don't need to spend that much for c2000:
> 
> http://www.signum.com/Signum.htm?p=jtagjet.htm


Thanks for the link.


-- 
Good day!

________________________________________
Christopher R. Carlen
Principal Laser&Electronics Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and
"BOGUS" from email address to reply.

Article: 109253
Subject: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
From: "John McGrath" <tails4e@gmail.com>
Date: 22 Sep 2006 07:34:19 -0700
Links: << >>  << T >>  << A >>

Jon Beniston wrote:
> > I don't understand the idea of using post syn timing.  Is that at all
> > accurate?
>
> Sometimes it is close, sometimes it is woefully inaccurate.
>
> > Why not let it do a PAR and see what kind of real results you get?
>
> It's the only way to know.
>
> Cheers,
> Jon


True - and as soon as I know you will know! - I left it PARing as I
left the office, and won't see the result myself until I am back
monday. However, from the post MAP timing, it looked good. I also put a
clock constraint of 200MHz on it (just to see). I'm curious myself. I
think the result would be more useful if I included a few more of the
core features, like debug logic, jtag, multiplier support etc. I just
left it with the defaults.

Regarding the verilog2001 support - XST seems to have clogb2 support,
but just there seemed to be some restrictions on where it can be used -
it could be because the RTL code is using it in a way that violates the
strict rules on the LRM, or it could be XST simply needs to allow the
use of this function more liberally (like in a preprocessing function
when reading the RTL, as its used as a constant), who knows. All I know
is it was not much effort to make it work, so hardly makes XST unsable
for synthesis of this core. This info mught help a few people out who
do not have access to alternatives....but if you really want to knock
synthesizers..check out design compiler in an asic context *shudder*.


Article: 109254
Subject: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 Sep 2006 07:41:58 -0700
Links: << >>  << T >>  << A >>
John McGrath schrieb:

> Jon Beniston wrote:
> > > I don't understand the idea of using post syn timing.  Is that at all
> > > accurate?
> >
> > Sometimes it is close, sometimes it is woefully inaccurate.
> >
> > > Why not let it do a PAR and see what kind of real results you get?
> >
> > It's the only way to know.
> >
> > Cheers,
> > Jon
>
>
> True - and as soon as I know you will know! - I left it PARing as I
> left the office, and won't see the result myself until I am back
> monday. However, from the post MAP timing, it looked good. I also put a
> clock constraint of 200MHz on it (just to see). I'm curious myself. I
> think the result would be more useful if I included a few more of the
> core features, like debug logic, jtag, multiplier support etc. I just
> left it with the defaults.
>
> Regarding the verilog2001 support - XST seems to have clogb2 support,
> but just there seemed to be some restrictions on where it can be used -
> it could be because the RTL code is using it in a way that violates the
> strict rules on the LRM, or it could be XST simply needs to allow the
> use of this function more liberally (like in a preprocessing function
> when reading the RTL, as its used as a constant), who knows. All I know
> is it was not much effort to make it work, so hardly makes XST unsable
> for synthesis of this core. This info mught help a few people out who
> do not have access to alternatives....but if you really want to knock
> synthesizers..check out design compiler in an asic context *shudder*.

whah? it hasnt finished? you should have used relaxed timing
constraints.

A microblaze design with all CPU options enabled and with Floating
Point unit included, targetting XC3S4000 using 489 IO's and having
192KB used local memory runs within some minutes until bitstream done.
(takes 14% BTW from s3-4000)

I bet your LM32 test desing is far less complex

getting 200MHz in slowest speed V5 seems unlikely, OpenFire demo design
did pass 200MHz in fastest V5 after a few xplorer runs.

so I bet the LatticeMico32 want pass timing on 200Mhz
 
Antti


Article: 109255
Subject: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
From: "Jon Beniston" <jon@beniston.com>
Date: 22 Sep 2006 07:58:44 -0700
Links: << >>  << T >>  << A >>

> True - and as soon as I know you will know! - I left it PARing as I
> left the office, and won't see the result myself until I am back
> monday. However, from the post MAP timing, it looked good. I also put a
> clock constraint of 200MHz on it (just to see).

Sometimes overconstraining the design too much will mean the tool will
give up earlier than it otherwise would if it was quite close, or so
I've been led to believe.

> I'm curious myself. I
> think the result would be more useful if I included a few more of the
> core features, like debug logic, jtag, multiplier support etc. I just
> left it with the defaults.

The JTAG logic requires Lattice specific cells, so you wouldn't be able
to use that, unless you converted it to work with the Xilinx JTAG
primitive.

> Regarding the verilog2001 support - XST seems to have clogb2 support,

clogb2 is a function defined in the Mico32 source.

> but just there seemed to be some restrictions on where it can be used
> it could be because the RTL code is using it in a way that violates the
> strict rules on the LRM, or it could be XST simply needs to allow the
> use of this function more liberally (like in a preprocessing function
> when reading the RTL, as its used as a constant), who knows.

I do :-)  XST doesn't support Verilog 2001 constant functions, which is
what is being used here.

Cheers,
Jon


Article: 109256
Subject: Re: Interrupts in Microblaze
From: "jerzy.zielinski" <jerzy.zielinski@gmail.com>
Date: 22 Sep 2006 08:13:00 -0700
Links: << >>  << T >>  << A >>

Siva Velusamy wrote:
> jerzy.zielinski wrote:
> > Hi,
> >
> > I wanted to deal with interrupts in Microblaze project. I would like to
> > procesor react to int from swich or a button sending a led blik on
> > GPIO. Can someone tell me how to do it.
> >
>
> Create a MicroBlaze + GPIO (w/ interrupts) design using BSB. It will
> create a TestApp_Peripheral s/w project which does exactly what you want.
>
> /Siva

Hi,

Thanks for your help, I created a project, and in TestApp there is only
Interrupt initialization and SelfTestIntC function. Initialization is
easy, because it is the same as in GPIO, selftest is not very helpfull
because it does nothing special. In Data sheet it is said that I have
to set some register, and masks, to make it work... The quastion is how
and where can I find listing of all the procedures located in IntC.h.

Thanks for help...

Jerzy


Article: 109257
Subject: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
From: jasimpson@gmail.com
Date: 22 Sep 2006 08:28:03 -0700
Links: << >>  << T >>  << A >>
I want to configure/program an Altera FLEX EPF10K30ETC144-3 + EPC2LC20
using files I've generated using Quartus for the same devices. I want
to use JTAG to interface to the devices using my ByteBlaster II. I have
carefully followed all Altera directions in generating the files and
designing the circuit with the devices on a PCB. My 2 questions are:

1) What is the difference between "configuring" and "programming" in
this context?

2) What file should I use to configure/program? .sof or .pof or both?

Any help would be greatly appreciated. I inherited the code and PCB
from another team that were using everything successfully. All I'm
trying to do is reprogram a new FPGA on the same PCB with the same
files. Unfortunately I do not have any contact with that team any more
for help.

-Jim


Article: 109258
Subject: Help with webpack/ISE 8.2
From: scott moore <nospam@nowhere.com>
Date: Fri, 22 Sep 2006 08:40:46 -0700
Links: << >>  << T >>  << A >>
Hi,

I could use a bit of help with Webpack/ISE 8.2 from Xilinx. I am
learning Verilog by constructing a small project in it, in fact
an 8080 CPU core.

I have completed the project, and am debugging it, but I can't seem
to get the ISE 8.2 simulator to display signal traces down inside the
module instantiations. After searches on this group's old messages,
I gather that in older versions, 7.x and back, this was simply a
matter of right clicking the signal in the signal names list and
choosing the "add to wave" option. However, this does not appear
to exist for 8.2, or was changed. I guess it is possible that the
free webpack does not have that capability, but the Xilinx website
seems to claim that the free version of the simulator "modelsim"
is not limited in an way but speed.

Right now, the only way I appear to have to get signals out to
the waveform pane is by routing them out to pins on my testbench,
a tedious procedure at best.

Thanks in advance,

Scott Moore

Article: 109259
Subject: Re: uBlaze : Programming in C++... Is Possible ?
From: Zara <yorara@terra.es>
Date: Fri, 22 Sep 2006 18:07:23 +0200
Links: << >>  << T >>  << A >>
On Fri, 22 Sep 2006 06:00:48 -0700, Alfmyk <Alfmyk@hotmail.com> wrote:

>Hi all.
>
>Please, what are main steps to try programming in C++ on uBlaze ? It's mandatory use a XilKernel (little Kernel) provided by Xilinx? In fact some built-in C++ command like new are unavailable...
>
>Please refer here any other possible suggestion and any issues using C++ in uBlaze environment.
>
>Thanks in advance.
>
>Cheers, Al.


It is possible. You may be forced to veto exceptions and floating
point.

In my case, I have written a multithreaded OS, pretty fast (but not
RTOS, interrupts are serviced in varying time) in templated C++ and a
little of assemebler, and it works really nice.

I found I had to rewrite some of the standard functions and macros as
provided by Xilinx, including global operator new, new[], delete and
delete[]  because they were too heavy-weighted fro an embedded
application.

BTW, no C++ will work with an EDK version before 8.1, previous
versions had some unpredictable bugs in the compiler.

Best regards,

Zara

Article: 109260
Subject: Xilinx OPB BFM simulation error with m_ABus signal
From: "lancos" <claudiolanconelli@gmail.com>
Date: 22 Sep 2006 09:40:48 -0700
Links: << >>  << T >>  << A >>
Hi,
I'm developing a custom OPB master peripheral for Spartan3. I don't use
IPIF. During simulation with BFM and Modelsim I noticed that OPB_ABus
is not correct in the following
case: my peripheral loose arbitration but still put a valid value on
the m_ABus (for example 10000), the new master put on his m_ABus for
example 40000, the result is on OPB_ABus is 50000.
It seems that the m_ABus is not ANDed with m_select signal. I read from
OPB specifications on page 11:
"The Mn_ABus signals from each OPB Master are AND'ed with that
master's Mn_select, and the resulting buses from all OPB masters are
then OR'ed together to form OPB_ABus. Thus, a master device may
continue to drive data onto Mn_ABus when its select is not asserted."

So my question is: the AND operation should be done on my peripheral or
on the opb arbitrer?
Is it a fault in the BFM toolkit?


Article: 109261
Subject: Re: Dell Laptop for Embedded Work
From: "Ulf Samuelsson" <ulf@a-t-m-e-l.com>
Date: Fri, 22 Sep 2006 19:12:37 +0200
Links: << >>  << T >>  << A >>
> I don't know how their docking stations work but I'd be suspicious. 
> Programmers often bit-bang the parallel port directly and that typically 
> doesn't work if they chose to simply convert USB-parallel in the dock 
> station.
>
> My suggestion would be to pay a little more and get a laptop with a 
> genuine parallel port.

I think the latest laptop chipsets does not support parallel ports.
When I went shopping for a PC for embedded support needs
last year, I ended up with an HP NW8000 which was just beeing
phased out because of this and similar problems.

Maybe get an old one, or a PCMCIA card with a true parallel port.

(- Or concentrate on the AVR stuff :-).
I think AVR Studio now supports USB <-> Serial Bridges.

>
> -- 

The

-- 
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB 



Article: 109262
Subject: Re: i2c,ahb,apb
From: "markus" <markus_1401@yahoo.com>
Date: 22 Sep 2006 10:27:22 -0700
Links: << >>  << T >>  << A >>
Hi Vits,

Opencores' files includes a model of an I2C slave device. I used this
model to test my modified Opencores' I2C. You connect the data and the
clock of the I2C master to the data and clock of the I2C slave. This is
where the I2C wires are located.

One thing to note, the provided I2C slave device only has four
registers. You can change the I2C slave device to have more than four
registers. I thought I'd share this with you, because this one took me
by surprise.

Per your question in regards to the Wishbone interface of the I2C
cores. The Wishbone interface is a backend interface that is defined by
the author of Opencores' I2C. The interface (in this core's case) is
used to control what action the I2C master need to do (e.g. send a
start, send data, look for acknowledge, etc).

Hope this helps,
-Markus

vits wrote:
> Thanks for the reply.
> First of all i want to test the i2c bus in verilog.For testing it i
> need a model of EEPROM(or anything else ,but i dont know much) to which
> i apply stimulus and apply the same stimulus to i2c bus and then
> compare the 2 outputs .In i2c rtl given in the opencores.org there are
> seperate signals for wishbone and i2c. i want to know why wishbone
> signals are there if i want to test only i2c bus.
> thanks,
> vits


Article: 109263
Subject: Re: Dell Laptop for Embedded Work
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 22 Sep 2006 17:37:00 GMT
Links: << >>  << T >>  << A >>
Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> wrote:

>Hi:
>
>I'm considering to buy a Dell Precision M90 laptop to replace a regular 
>PC on a cart that was used to wheel around and program various embedded 
>devices.
>
>The new laptops of course don't offer old-fashioned ports like parallel 
>and RS-232.  Well, some have serial, but the M90 doesn't.
>
>I will be getting the docking station which *does* have a parallel and 
>serial port though, so it should be just fine.  There is also the option 
>of USB->RS-232 converters.  But the dock's parallel port will be 
>critically important to work correctly.
>
>I will need to connect to the following devices:
>
>Atmel STK500 (RS-232) and JTAG-ICE (USB/RS-232)
>
>Spectrum Digital eZdsp 'F2812 (parallel)
>
>Xilinx Parallel Cable IV (parallel)
>
>In the future there will likely be a USB JTAG Emulator for the 'F2812, 
>and perhaps I'll upgrade to a better Xilinx cable.  Also will probably 
>get into some Xilinx FPGAs and 3rd party development boards, but just 
>need to be sure I can work my present tools.
>
>Anyone have any serious problems with Dell laptops for these or other tools?

I tried to use a Dell laptop for data acquisition in a car for a lot
of test runs, but somehow it got its USB ports screwed up after a
while (probably due to heating). I ended up with using a standard Dell
PC which seemed to work fine.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 109264
Subject: Re: uBlaze : Programming in C++... Is Possible ?
From: "Vasanth Asokan" <nospam@xilinx.com>
Date: Fri, 22 Sep 2006 10:44:33 -0700
Links: << >>  << T >>  << A >>
Hi,

C++ is indeed supported on MicroBlaze and no, it has no requirement to be 
used with Xilkernel. In fact, if anything, C++ has typically not been used 
in a multi-threaded environment, as the OS libraries need to provide 
thread-safety and re-entrancy on some key routines.

new, delete etc. are indeed available. (assuming you are using EDK 8.1i and 
post).

Some functions in the C++ STL may not be available - especially calls that 
require file system support.

There are one or two obscure bugs with exception handling, but it works for 
the most part. mb-g++ has a 95% pass rate on the DejaGNU G++ testsuite.

thanks,
Vasanth



"Alfmyk" <Alfmyk@hotmail.com> wrote in message 
news:ee9f05b.-1@webx.sUN8CHnE...
> Hi all.
>
> Please, what are main steps to try programming in C++ on uBlaze ? It's 
> mandatory use a XilKernel (little Kernel) provided by Xilinx? In fact some 
> built-in C++ command like new are unavailable...
>
> Please refer here any other possible suggestion and any issues using C++ 
> in uBlaze environment.
>
> Thanks in advance.
>
> Cheers, Al. 



Article: 109265
Subject: Re: Xilinx OPB BFM simulation error with m_ABus signal
From: David Ashley <dash@nowhere.net.dont.email.me>
Date: Fri, 22 Sep 2006 11:15:30 -0700
Links: << >>  << T >>  << A >>
lancos wrote:
> Hi,
> I'm developing a custom OPB master peripheral for Spartan3. I don't use
> IPIF. During simulation with BFM and Modelsim I noticed that OPB_ABus
> is not correct in the following
> case: my peripheral loose arbitration but still put a valid value on
> the m_ABus (for example 10000), the new master put on his m_ABus for
> example 40000, the result is on OPB_ABus is 50000.
> It seems that the m_ABus is not ANDed with m_select signal. I read from
> OPB specifications on page 11:
> "The Mn_ABus signals from each OPB Master are AND'ed with that
> master's Mn_select, and the resulting buses from all OPB masters are
> then OR'ed together to form OPB_ABus. Thus, a master device may
> continue to drive data onto Mn_ABus when its select is not asserted."
> 
> So my question is: the AND operation should be done on my peripheral or
> on the opb arbitrer?
> Is it a fault in the BFM toolkit?
> 

My understanding was that all masters need to drive 0's when they don't
own the bus. But I have no personal experience with the xilinx busses,
it's just heresay.

-Dave

-- 
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture

Article: 109266
Subject: Re: Dell Laptop for Embedded Work
From: Jim Thomas <jthomas@bittware.com>
Date: Fri, 22 Sep 2006 14:36:16 -0400
Links: << >>  << T >>  << A >>
Chris Carlen wrote:
> Hi:
> 
> I'm considering to buy a Dell Precision M90 laptop to replace a regular 
> PC on a cart that was used to wheel around and program various embedded 
> devices.
> 
> The new laptops of course don't offer old-fashioned ports like parallel 
> and RS-232.  Well, some have serial, but the M90 doesn't.

I'm typing this on a Dell Latitude 610, and it has both a serial and a 
parallel port.  Dunno if that's one your "approved" list or not, but 
this has been a great laptop for my needs.

-- 
Jim Thomas            Principal Applications Engineer  Bittware, Inc
jthomas@bittware.com  http://www.bittware.com    (603) 226-0404 x536
Today is the last day of your life so far.

Article: 109267
Subject: Re: MV4.0.1 and Avnet Mini-Module
From: "funkrhythm" <rimas@cnmat.berkeley.edu>
Date: 22 Sep 2006 11:53:52 -0700
Links: << >>  << T >>  << A >>

what processor revision (PVR) is the PowerPC core in the V4FX12 part on
the mini module ?  if its 0x20011430 then you need to make sure you've
applied a patch to sets bits 1 & 3 in the CCR0 register and disable all
the caches.  thats what i had to do to get 2.4 to work reliably on the
mini module.  here's the xilinx page the describes the silicon errata
involved:

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=20658&BV_SessionID=@@@@0305580279.1158951085@@@@&BV_EngineID=ccccaddikmdkkglcefeceihdffhdfjf.0

(answer record 20658)

-rimas

Anonymous wrote:
> Has anyone been able to get montavista4.0.1 to build a 2.6 kernel for the
> mini-module? I get a build but the kernel crashes trying to allocate kernel
> cache memory:
>
> loaded at:     00400000 004E913C
> board data at: 004E7124 004E713C
> relocated to:  004051E4 004051FC
> zimage at:     00405A3D 004E6BC4
> avail ram:     004EA000 04000000
>
> Linux/PPC load: console=tty1 console=ttyS0,9600 ip=on root=/dev/xsysace2 rw
> Uncompressing Linux...done.
> Now booting the kernel
> Linux version 2.6.10_mvl401-ml40x (Administrator@Rachel_d600) (gcc version
> 3.4.3
>  (MontaVista 3.4.3-25.0.100.0600797 2006-06-06)) #4 Wed Sep 20 19:14:20 EDT
> 2006
> Xilinx ML40x Reference System (Virtex-4 FX)
> Port by MontaVista Software, Inc. (source@mvista.com)
> Built 1 zonelists
> Kernel command line: console=tty1 console=ttyS0,9600 ip=on
> root=/dev/xsysace2 rw
> Xilinx INTC #0 at 0x41200000 mapped to 0xFDFFE000
> PID hash table entries: 512 (order: 9, 8192 bytes)
> hr_time_init: arch_to_nsec = 20971520, nsec_to_arch = 429496729
> Console: colour dummy device 80x25
> Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
> Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> Memory: 62848k available (1452k kernel code, 452k data, 116k init, 0k
> highmem)
> Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
> Badness in __schedule at kernel/sched.c:2842
> Call trace:
>  [c0003a64] check_bug_trap+0x98/0xdc
>  [c0003c98] ProgramCheckException+0x1f0/0x2b4
>  [c00032a4] ret_from_except_full+0x0/0x4c
>  [c01674c4] __schedule+0x28/0x728
>  [c0167c34] preempt_schedule+0x70/0xa4
>  [c003e04c] buffered_rmqueue+0x2ec/0x2f8
>  [c003e120] __alloc_pages+0xc8/0x3ac
>  [c003e42c] __get_free_pages+0x28/0x68
>  [c0042c80] cache_alloc_refill+0x32c/0x5d0
>  [c00426dc] kmem_cache_alloc+0x68/0x6c
>  [c006436c] sget+0xc4/0x3fc
>  [c006558c] get_sb_single+0x34/0xcc
>  [c009b700] sysfs_get_sb+0x1c/0x2c
>  [c0065680] do_kern_mount+0x5c/0x118
>  [c01d2e8c] sysfs_init+0x48/0x80
> kmem_cache_create: Early error in slab bdev_cache
> kernel BUG in kmem_cache_create at mm/slab.c:1209!
> Oops: Exception in kernel mode, sig: 5 [#1]
> PREEMPT
> NIP: C0043C94 LR: C0043C94 SP: C01BFF60 REGS: c01bfeb0 TRAP: 0700    Not
> tainted
> MSR: 00029030 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 11
> TASK = c0198710[0] 'swapper' THREAD: c01be000
> Last syscall: 0
> GPR00: C0043C94 C01BFF60 C0198710 00000035 00000703 FFFFFFFF 00000001
> 00000720
> GPR08: C01F0000 C01C0000 00000000 C01BE000 44000028 00003570 02001400
> 00000000
> GPR16: 00000001 00000001 FFFFFFFF 007FFF00 01FFAA80 C0065E54 00000003
> 00000000
> GPR24: 00000000 C0176A18 FF950040 78737973 00062000 C01A0000 00000000
> 00000188
> NIP [c0043c94] kmem_cache_create+0x5c/0x5e0
> LR [c0043c94] kmem_cache_create+0x5c/0x5e0
> Call trace:
>  [c01d2078] bdev_cache_init+0x3c/0xb0
>  [c01d2424] vfs_caches_init+0xf0/0x108
>  [c01c05dc] start_kernel+0x12c/0x170
>  [c000225c] start_here+0x44/0xb0
> Kernel panic - not syncing: Aiee, killing interrupt handler!
>  <0>Rebooting in 180 seconds..<NULL>
>
>
> Near as I can tell it is crashing because it thinks it's in an interrupt
> when it goes to allocate the kernel cache. It's got to be something simple
> like the interrupt controller is programmed wrong based on my xparm.h file.
>
> Anyway, does anybody have a 2.6 kernel working on mini-module? So far
> neither MV or Xilinx have been any help.
> 
> Thanks,
> Clark


Article: 109268
Subject: Re: Fast Platform for ISE?
From: "Tim" <tim@rockylogiccom.noooospam.com>
Date: Fri, 22 Sep 2006 22:07:18 +0100
Links: << >>  << T >>  << A >>

Jon Beniston wrote
> E6600 Dual Core - 2.6 GHz, with DDRII 667 memory.
>
> Pentium 4 was 3 GHz, with 400 MHz memory, I think. (So a little old,
> but not exactly ancient)

4MB cache on the new toy, 2MB on the old. Others have mentioned that cache 
size is the key.



Article: 109269
Subject: Re: Fast Platform for ISE?
From: "John Adair" <g1@enterpoint.co.uk>
Date: 22 Sep 2006 14:29:43 -0700
Links: << >>  << T >>  << A >>
The E6600 is the slowest + cheapest one with 4M cache. Going by gamer
benchmarks, which we have found to be reasonably representative in the
past, the E6600 should be good performance for the money. If not on a
budget then the faster versions are available too. We will certainly
move over from our current Athlon64 preference on any new machines.

John Adair
Enterpoint Ltd.

Tim wrote:
> Jon Beniston wrote
> > E6600 Dual Core - 2.6 GHz, with DDRII 667 memory.
> >
> > Pentium 4 was 3 GHz, with 400 MHz memory, I think. (So a little old,
> > but not exactly ancient)
>
> 4MB cache on the new toy, 2MB on the old. Others have mentioned that cache
> size is the key.


Article: 109270
Subject: Re: Dell Laptop for Embedded Work
From: Joerg <notthisjoergsch@removethispacbell.net>
Date: Fri, 22 Sep 2006 21:32:56 GMT
Links: << >>  << T >>  << A >>
Hello Chuck,

> Joerg wrote:
> 
>>>I'm considering to buy a Dell Precision M90 laptop to replace a regular
>>>PC on a cart that was used to wheel around and program various embedded
>>>devices.
>>>
>>>The new laptops of course don't offer old-fashioned ports like parallel
>>>and RS-232.  Well, some have serial, but the M90 doesn't.
>>>
> 
> ... snip ...
> 
>>I don't know how their docking stations work but I'd be suspicious.
>>Programmers often bit-bang the parallel port directly and that typically
>>doesn't work if they chose to simply convert USB-parallel in the dock
>>station.
>>
>>My suggestion would be to pay a little more and get a laptop with a
>>genuine parallel port.
> 
> 
> I agree.  When everyone caves in and buys these emasculated
> machines, they just encourage the manufacturers to save the few
> pennies it takes to make a real system.  Same goes for desktops and
> for ECC memory.
> 

True, but I am afraid we are in a minority that shrinks fast. Almost all 
printers are USB now and those made up for close to 99% of parallel port 
devices. The number of people who still need a parallel port is so 
miniscule these days that mfgs probably won't care. The last printer I 
bought still has a parallel port but it already came sans cable and sure 
enough I hooked it up to the LAN.

-- 
Regards, Joerg

http://www.analogconsultants.com

Article: 109271
Subject: Re: Dell Laptop for Embedded Work
From: Joerg <notthisjoergsch@removethispacbell.net>
Date: Fri, 22 Sep 2006 21:36:11 GMT
Links: << >>  << T >>  << A >>
Hello Ulf,


>>I don't know how their docking stations work but I'd be suspicious. 
>>Programmers often bit-bang the parallel port directly and that typically 
>>doesn't work if they chose to simply convert USB-parallel in the dock 
>>station.
>>
>>My suggestion would be to pay a little more and get a laptop with a 
>>genuine parallel port.
> 
> 
> I think the latest laptop chipsets does not support parallel ports.
> When I went shopping for a PC for embedded support needs
> last year, I ended up with an HP NW8000 which was just beeing
> phased out because of this and similar problems.
> 
> Maybe get an old one, or a PCMCIA card with a true parallel port.
> 
> (- Or concentrate on the AVR stuff :-).
> I think AVR Studio now supports USB <-> Serial Bridges.
> 

They pretty much all do now. The coolest thing is that little EZ430 
stick. You can connect wires to it after cracking it open and then use 
it at a client site. Slips right into a small pocket. Of course, airport 
security will want to know what that thing is...

-- 
Regards, Joerg

http://www.analogconsultants.com

Article: 109272
Subject: Re: X4000 bad configuration
From: Jacques GENIN <rxnd@wanadoo.fr>
Date: Fri, 22 Sep 2006 23:54:55 +0200
Links: << >>  << T >>  << A >>
Gabor a écrit :

> The date code is after the package type on line 2,
> in the above case 0141 or 41st week of 2001.
> 
> See answer record #1067
> 
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067
> 
Thanks for that;
Oups ! My bad parts are the most recent I ever got...

Article: 109273
Subject: Re: Altera configuring/programming for FLEX10KE with EPC2 - sof or pof?
From: "Subroto Datta" <sdatta@altera.com>
Date: 22 Sep 2006 15:00:23 -0700
Links: << >>  << T >>  << A >>
Hello Jim,

) Configuring refers to the loading information into the FPGA.
Programming refers to loading information into the EPC2 flash memory
device.

2) Quartus II software uses the SOF file to configure the FPGA with a
download cable.  The POF file is used to program the EPC2 device.

Hope this helps.
Subroto Datta
Altera Corp.



jasimpson@gmail.com wrote:
> I want to configure/program an Altera FLEX EPF10K30ETC144-3 + EPC2LC20
> using files I've generated using Quartus for the same devices. I want
> to use JTAG to interface to the devices using my ByteBlaster II. I have
> carefully followed all Altera directions in generating the files and
> designing the circuit with the devices on a PCB. My 2 questions are:
>
> 1) What is the difference between "configuring" and "programming" in
> this context?
>
> 2) What file should I use to configure/program? .sof or .pof or both?
>
> Any help would be greatly appreciated. I inherited the code and PCB
> from another team that were using everything successfully. All I'm
> trying to do is reprogram a new FPGA on the same PCB with the same
> files. Unfortunately I do not have any contact with that team any more
> for help.
> 
> -Jim


Article: 109274
Subject: Re: X4000 bad configuration
From: "Peter Alfke" <peter@xilinx.com>
Date: 22 Sep 2006 15:01:28 -0700
Links: << >>  << T >>  << A >>
I think it's time for you to describe the "badness".
The thread gets a bit long in the tooth. :-(
Peter Alfke
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Jacques GENIN wrote:
> Gabor a =E9crit :
>
> > The date code is after the package type on line 2,
> > in the above case 0141 or 41st week of 2001.
> >
> > See answer record #1067
> >
> > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=3D1&iCountry=
ID=3D1&getPagePath=3D1067
> >
> Thanks for that;
> Oups ! My bad parts are the most recent I ever got...




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search