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Messages from 93800

Article: 93800
Subject: Re: Power Optimization: can the routing and placement really save power?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 30 Dec 2005 14:43:04 -0800
Links: << >>  << T >>  << A >>

Why all this commotion?
It does not take a genius to interpret the graph:

Dynamic power is very similar for the two competing devices, although
Xilinx has still an edge, even after the Altera improvements.
The dramatic (>2:1) difference is in static power consumption, which of
course is ugliest at 85 degrees. Here Xilinx benefits from its use of
three different gate oxide thicknesses (Altera uses only two).
And, to camouflage their weakness, Altera conveniently published those
meaningless 25 degree total power numbers.
That's what I mean by Marketing BS, for most devices in the Virtex-4 or
Stratix-II class are operated at high clock rates, which makes them run
hot, close to and sometimes even above 85 degrees. To brag about
allegedly low power at 25 degrees misses the point, is Marketing BS.
Peter Alfke, from home.
Happy New Year. whichever FPGA you prefer.


Article: 93801
Subject: Re: Brute Force Examination of a PLD
From: "logjam" <grant@cmosxray.com>
Date: 30 Dec 2005 15:03:12 -0800
Links: << >>  << T >>  << A >>
That's good news Antti, thanks!

However now I am confused why PALs slowed the counterfeiting of
computers in the early 80s.  I've read that PALs were used primarily
for component reduction but that some companies used them in ways to
slow down reverse engineering.

Was it just that a computer with I/O resources, memory, and human
knowledge of electronics slowed down the reproduction?

The HAL and PALs do not offer the ability to preload, but if all the
inputs to the PAL were low and the clock were cycled a few times and
the "brute force" program stopped on a pattern (its possible to get a
repeating pattern by clocking all 0s into the PAL) that was the same
starting pattern for all tests then that could help.

Potentially there would be two patterns, right?  All 0 inputs into the
PAL, and with the same inputs a different output.  So if the 65535
tests were begun with ONE of the initial all 0 input patterns, then
would a second set of 65535 tests on the other pin help decide the
internal feedback configuration?

This is assuming of course that the computer is processing and reducing
the test results itself.  That program/algorithm is still beyond me at
this point.  Does anyone have any ideas on a program or algorithm
written?  A book about this process?

Thanks for your time,

Grant


Article: 93802
Subject: Newbie question - using library "design elements"
From: Mike Oxlarge <oxlargeMike@yahoo.com>
Date: Fri, 30 Dec 2005 21:49:12 -0800
Links: << >>  << T >>  << A >>
I've got the Spartan-3 starter board, and in going through the ISE 7.1i
documentation I see that there are "design elements" that can be used in a
design. In some of those elements it says that they are "inferred rather
than instantiated". For example, CC8CE for the Spartan 3 is a 8-, 16-Bit
Cascadable Binary Counter with Clock Enable and Asynchronous Clear. I had
gone through the whole learning experience of creating a 32-bit binary
counter using Verilog, and then I found that the CC8CE was "available". My
question is, how are these available? I mean, in looking at my RTL
schematic I'm not seeing that a CC8CE was synthesized. I also see
the following in the synthesis report:
 ...
Synthesizing Unit <myNbitCounter>.
    Related source file is "myNbitCounter.v".
WARNING:Xst:653 - Signal <M> is used but never assigned. Tied to value 0.
    Found 16-bit up counter for signal <cnt>. Found 1-bit register for
    signal <carryout>. Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <myNbitCounter> synthesized.

Forgetting about the warning for now, I see that it recognizes my code as
a 16 bit counter, but it didn't "infer" it to be a CC8CE type. Could I
have somehow simply told it to use a CC8CE instead of going through the
effort of creating my own (probably with errors) 16 bit counter? Isn't
this such a basic element that I shouldn't have to re-create it?

Thanks for your assistance.

Article: 93803
Subject: open source xnf to edif script
From: "Totally_Lost" <air_bits@yahoo.com>
Date: 30 Dec 2005 23:25:22 -0800
Links: << >>  << T >>  << A >>
Does anybody know of an open source xnf to edif converter we can use
with FpgaC?   A C program would be fine, as would a perl/ruby script.

Or if there is a student on holiday that would like to knock this
project off as a FpgaC developer that would be cool too :)

The xnf to edf project is a feature request on the fpgac site:

http://sourceforge.net/tracker/index.php?func=detail&aid=1365849&group_id=152034&atid=782959


Article: 93804
Subject: Fitting circuits to fpga LUTs
From: "Totally_Lost" <air_bits@yahoo.com>
Date: 30 Dec 2005 23:29:32 -0800
Links: << >>  << T >>  << A >>
The FpgaC internal algorithm is pretty generic, and just decideds
pretty early on to force all internal functions to 4-LUTs. This makes
it difficult to decide to use support logic like H-LUTs on XC4K, or F5
muxes on Virtex parts, or the carry logic on any of these.

I'm looking for papers which discuss/descript alternative fitting
algorithms to better use vendor assist logic in FPGAs, particularly for
scheduling logic expressions across multiple LUTs for both space and
time specific tradeoffs.


Article: 93805
Subject: Re: Is there anybody that have ported the linux to the nios or microblaze?
From: Mike Frysinger <vapier@gentoo.org>
Date: Sat, 31 Dec 2005 02:30:19 -0500
Links: << >>  << T >>  << A >>
On Fri, 23 Dec 2005 18:05:25 +1100, Alex Gibson wrote:
> uclinux for nios2
> http://www.enseirb.fr/~kadionik/embedded/uclinux/nios-uclinux.html
> http://www.enseirb.fr/~kadionik/embedded/uclinux/HOWTO_compile_uClinux_for_NIOS.html
> 
> http://linuxdevices.com/news/NS9386138954.html

anyone know where i could find *working* and *up-to-date* toolchain
sources for nios2 ?

the cdk4nios project is out of date:
http://sourceforge.net/projects/cdk4nios/
their work is based upon the old gcc-2 release (what altera calls
"gnupro-src-3.x")

on altera's site, they tell you how to download the sources:
http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html

and there you can find the up-to-date release (gcc-3.4.1 / gnutools-5.1),
but the source tarball is missing a lot of files in the gcc dir which
prevent it from compiling ... read the gcc/config/nios2/t-nios2 config
file and you'll see that the math files for libgcc.a are missing as well
as the source .asm files for crt*.o objects:
$(srcdir)/config/nios2/lib2-divmod.c
$(srcdir)/config/nios2/lib2-divmod-hi.c
$(srcdir)/config/nios2/lib2-divtable.c
$(srcdir)/config/nios2/lib2-mul.c
$(srcdir)/config/nios2/crti.asm
$(srcdir)/config/nios2/crtn.asm
-mike


Article: 93806
Subject: Low cost PCI FPGA cards for reconfigurable computing
From: "Totally_Lost" <air_bits@yahoo.com>
Date: 30 Dec 2005 23:33:42 -0800
Links: << >>  << T >>  << A >>
What are the recomendations for low end PCI FPGA cards with at least
15,000 LUTs?


Article: 93807
Subject: Re: Low cost PCI FPGA cards for reconfigurable computing
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 31 Dec 2005 09:20:11 +0100
Links: << >>  << T >>  << A >>
"Totally_Lost" <air_bits@yahoo.com> schrieb im Newsbeitrag 
news:1136014422.814368.98960@z14g2000cwz.googlegroups.com...
> What are the recomendations for low end PCI FPGA cards with at least
> 15,000 LUTs?
>

enterpoint raggedstaone-1 can be ordered with spartan3-2000, I guess that 
would be the lowset cost solution

Antti 



Article: 93808
Subject: Re: TCL SCRIPT AND VHDL DESIGN
From: "Hans" <hans64@ht-lab.com>
Date: Sat, 31 Dec 2005 09:22:43 GMT
Links: << >>  << T >>  << A >>
If you have access to Modelsim then have a look in the Command Reference 
manual. Look for the force,  change, examine and when commands, all have 
some simple examples.

Hans
www.ht-lab.com


"AAA" <abrar_ahmed_313@yahoo.co.in> wrote in message 
news:1135946335.609453.46980@z14g2000cwz.googlegroups.com...
> hii
>
> i have to study TCL SCRIPTING and i have to verify the VHDL codes, i
> have learnt this lannguage but have to verify the vhdl code using TCL
> SCRIPT. can any one out here please tell me how to go about. Any link
> or pdf doc. that explains how to do the same.
> suppose i have to verify a counter. i have to force values to teh
> signal, get it on the waveform. the entire process that a testbench
> does, has to be performed in TCL SCRIPT...
> i hope query is well explained.
>
> thanks
> HAPPY NEW YEAR TO ALL
> 



Article: 93809
Subject: Re: call for papers,Expresscard specification?
From: "Hans" <hans64@ht-lab.com>
Date: Sat, 31 Dec 2005 09:32:51 GMT
Links: << >>  << T >>  << A >>
Look for a company that builds ExpressCards and see if they are willing to 
sponsor your project. This is also a good opportunity to show your 
capabilities and perhaps end up with a job (worked for me when I was a 
student :-)

Hans.
www.ht-lab.com

"bjzhangwn" <bjzhangwn@126.com> wrote in message 
news:1135954545.288345.115490@g43g2000cwa.googlegroups.com...
>I know,but I am astudent,and how can i get it freely?
> 



Article: 93810
Subject: Re: call for papers,Expresscard specification?
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 31 Dec 2005 13:08:25 -0000
Links: << >>  << T >>  << A >>
Specs can be got from PCI SIG http://www.pcisig.com/home but at a cost as 
said elsewhere. You may find that you College or University has membership 
and can get specs free so check that. It is also possible that PCI SIG has a 
University Program but I don't see any mention of it. Would be worth an 
email to them to find out.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"bjzhangwn" <bjzhangwn@126.com> wrote in message 
news:1135952990.898044.287390@g14g2000cwa.googlegroups.com...
> Can anyone have it?
> 



Article: 93811
Subject: Re: Low cost PCI FPGA cards for reconfigurable computing
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 31 Dec 2005 13:41:07 -0000
Links: << >>  << T >>  << A >>
I will clarify what Antti has said and that our standard Raggedstone1 
(RS1-400) comes with a XC3S400. We can offer special versions to volume or 
strategic customers with XC3S1000, XC3S1500 and XC3S2000 but these will not 
be off the shelf and may be subject to extra costs and leadtimes depending 
on the circumstances.

Your requirement for 15,000 luts approximates to a XC3S1000 Spartan-3. Our 
MINI-CAN product has this part as standard and is in stock. Cost is 100 
(US$180) and is a very competive product against other vendor offerings. We 
can also offer our high feature Broaddown2 with XC3S1000, or XC3S1500, as 
standard. The BD2-1000 is on offer currently at 190 (US$ 340) and is in 
stock. If you are a student of a academic institution we offer discounts 
under our University Access Program(UAP).

Depending on your application another option we can offer is our OVERCOAT 
feature. This is where an array is built-up from a number of of our boards. 
This is a semi-custom option where we change some of the headers to fit to 
the back of our boards allowing an array sandwich to be made up.

Details of our products are available on our website but will not ship until 
after 4th January when the main office reopens after the holiday break.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"Totally_Lost" <air_bits@yahoo.com> wrote in message 
news:1136014422.814368.98960@z14g2000cwz.googlegroups.com...
> What are the recomendations for low end PCI FPGA cards with at least
> 15,000 LUTs?
> 



Article: 93812
Subject: Re: Newbie question - using library "design elements"
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 31 Dec 2005 13:53:43 -0000
Links: << >>  << T >>  << A >>
Mike

You can use the CC8CE as an instantiated component if that is what you want 
exactly. Details of the component are in the Xilinx Libraries Guide which 
you can assess from the documentation with ISE tools or from the Xilinx 
website.

Often if you want to infer a particular component you need to use a 
structure that the synthesiser lines up exactly to a expectation that the 
synthesiser has for that component. That is usually difficult to do and if 
you must have it then instantiate. CC8CE is also a macro element and not a 
primative so may not be inferred by the sythesiser for that reason. It may 
break your design down into smaller primative elements.

Generally I would be more concerned that Verilog description has the 
features that you need and is best checked with a simulator. Beyond that 
setting and meeting timing constraints should be your other concern.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"Mike Oxlarge" <oxlargeMike@yahoo.com> wrote in message 
news:pan.2005.12.31.05.49.12.520398@yahoo.com...
> I've got the Spartan-3 starter board, and in going through the ISE 7.1i
> documentation I see that there are "design elements" that can be used in a
> design. In some of those elements it says that they are "inferred rather
> than instantiated". For example, CC8CE for the Spartan 3 is a 8-, 16-Bit
> Cascadable Binary Counter with Clock Enable and Asynchronous Clear. I had
> gone through the whole learning experience of creating a 32-bit binary
> counter using Verilog, and then I found that the CC8CE was "available". My
> question is, how are these available? I mean, in looking at my RTL
> schematic I'm not seeing that a CC8CE was synthesized. I also see
> the following in the synthesis report:
> ...
> Synthesizing Unit <myNbitCounter>.
>    Related source file is "myNbitCounter.v".
> WARNING:Xst:653 - Signal <M> is used but never assigned. Tied to value 0.
>    Found 16-bit up counter for signal <cnt>. Found 1-bit register for
>    signal <carryout>. Summary:
> inferred   1 Counter(s).
> inferred   1 D-type flip-flop(s).
> Unit <myNbitCounter> synthesized.
>
> Forgetting about the warning for now, I see that it recognizes my code as
> a 16 bit counter, but it didn't "infer" it to be a CC8CE type. Could I
> have somehow simply told it to use a CC8CE instead of going through the
> effort of creating my own (probably with errors) 16 bit counter? Isn't
> this such a basic element that I shouldn't have to re-create it?
>
> Thanks for your assistance. 



Article: 93813
Subject: Timing problem in ModelSim, Post-Route Simulation.
From: "Dan NITA" <ndf@free.fr>
Date: Sat, 31 Dec 2005 15:55:09 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm doing a Post-Route Simulation simulation in ModelSim V6.1a and having 
problem with physical paths delays.

The placed & routed netlist and associated SDF delay file are created with 
Lattice ispLever V5.1.

The problem is that propagations times from all signals are not the same on 
ModelSim wave window compare with the propagations times display on SDF 
file.


Example:

On the .SDF file and the Place & Route Trace Report .TWR file I found 2.887 
ns between the output F0 of SLICE_1442 and the input D1 of SLICE_1384.

On ModelSim the same physical path had a propagation delay of  5.487 ns!!!!

The question is simple: Why a difference here?

Useless to say that the whole simulation is wrong and the only solution is 
to increase the clock period...

Thanks,
Dan NITA




.TWR FILE RAPPORT:
CTOF_DEL    ---  0.310    R8C11A.D0 to    R8C11A.F0 SLICE_1442
ROUTE         5  2.377    R8C11A.F0 to    R3C15D.D1 instMotorsDriver_N_23
CTOOFX_DEL  ---  0.510    R3C15D.D1 to    R3C15D.OFX0 
instMotorsDriver_sigAccumulator_20_8_0_13/SLICE_1384
ROUTE         1  0.000    R3C15D.OFX0 to  R3C15C.FXB 
instMotorsDriver_instDriverProcessor_N_323


.SDF FILE RAPPORT:
(CELL
      (CELLTYPE "instMotorsDriver_sigAccumulator_20_8_0_13_SLICE_1384")
      (INSTANCE instMotorsDriver_sigAccumulator_20_8_0_13_SLICE_1384I)
    (DELAY
      (ABSOLUTE
        (IOPATH D1 OFX0 (510:571:632)(510:571:632))
        ...........
      )
    )
  )
(INTERCONNECT SLICE_1442I/F0 
instMotorsDriver_sigAccumulator_20_8_0_13_SLICE_1384I/D1 
(2377:2563:2749)-(2377:2563:2749)) 



Article: 93814
Subject: Re: Timing problem in ModelSim, Post-Route Simulation.
From: "Julian Kain" <entanglebit@gmail.com>
Date: 31 Dec 2005 08:21:15 -0800
Links: << >>  << T >>  << A >>
Dan,

What kind of speeds are you pushing through your external I/O's and the
fabric itself? Depending on the clock period of your external I/O's and
the input port delays of your fabric components, it may be a
Verilog/ModelSim pulse-swallowing simulation issue. You can, however,
set path and transport delays to fine-tune the post-PAR simulation.

I was having a (somewhat) similar problem before, and it turned out
that my internal routing was not an issue, but my external I/O's were.
In my case, the facade was that fast bit transitions appeared to take
about twice as long, and the data was often wrong. This was ultimately
traced back to chip's multi-gigabit pins being too fast for ModelSim to
handle without special parameters... it was essentially swallowing
pulses on MGT pins and missing bit-by-bit transitions on the input.
This may or may not be the same issue as yours, but it could have the
same solution.

This is a Xilinx page, but it addresses the Verilog/ModelSim issue of
pulse swallowing on fast transitions:
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/simu12.html

Julian Kain
www.juliankain.com


Article: 93815
Subject: Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 31 Dec 2005 16:39:55 -0000
Links: << >>  << T >>  << A >>
Generally the answer is that Chipscope always has some effect. However you 
can minimise the effect by pre-registering signals used as inputs to 
chipscope. This reduces the raw fight for resources between where design 
elements need to be and where Chipscope needs to be with the chip.

The problem you describe does sound like timing. Have you set proper timing 
constraints? Have you considered the implementation where any clock 
boundaries that are crossed?


John Adair
Enterpoint Ltd. - Home of MIN-CAN. The Spartan-3 CAn Bus Development Board.
http://www.enterpoint.co.uk


<linq936@hotmail.com> wrote in message 
news:1135895051.874809.226500@g14g2000cwa.googlegroups.com...
> Hi,
>  I am working on a Virtex4 FX design, when the system clock runs at
> 100MHz, the memory controller core does not work correctly. Then I
> inserted ChipScope trying to identify the problem, but once it is
> inserted, the problem is gone!
>
>  I know it is of timing problem since if I lower the system clock to
> 50MHz, there is no problem either.
>
>  It looks like that after the chipscope is inserted, somehow the
> routing is altered in favor of the memory controller.
>
>  I just wonder if there are any trick so that Chipscope insertion does
> not impact design routing?
> 



Article: 93816
Subject: Re: Newbie question - using library "design elements"
From: Mike Oxlarge <oxlargeMike@yahoo.com>
Date: Sat, 31 Dec 2005 09:01:19 -0800
Links: << >>  << T >>  << A >>
On Sat, 31 Dec 2005 13:53:43 +0000, John Adair wrote:

> Mike
> 
> You can use the CC8CE as an instantiated component if that is what you
> want exactly. Details of the component are in the Xilinx Libraries Guide
> which you can assess from the documentation with ISE tools or from the
> Xilinx website.
> 
> Often if you want to infer a particular component you need to use a
> structure that the synthesiser lines up exactly to a expectation that
> the synthesiser has for that component. That is usually difficult to do
> and if you must have it then instantiate. CC8CE is also a macro element
> and not a primative so may not be inferred by the sythesiser for that
> reason. It may break your design down into smaller primative elements.
> 
> Generally I would be more concerned that Verilog description has the
> features that you need and is best checked with a simulator. Beyond that
> setting and meeting timing constraints should be your other concern.
> 
> John Adair
> Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3
> Development Board.
> http://www.enterpoint.co.uk
> 

Thanks for the speedy reply.

So what I'm taking from your response is:

1. There is no way that I can simply say in my verilog code to use a
CC8CE. 
2. If by chance, my verilog code matched what the synthesizer was
expecting, then it _may_ use a CC8CE.

I understand that a counter in verilog is no big deal, but I'm having a
tough time understanding why these design elements exist if there is no
way to directly instantiate them. Like I said in my original post, I'm
sure there are probably errors in my counter's design, so it would be nice
to be able to "drop in" a known working element. In general, I think that
this boils down to an issue of code-reuse, and me not yet at a point in my
FPGA education of realizing how to take advantage of it. I'm hoping that I
will learn that yes, there is a way to simply say "use this counter" or
other design element, and feel confident that it was going to work.

Thanks again for your response, and happy Hogmanay.

Article: 93817
Subject: Re: Newbie question - using library "design elements"
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 31 Dec 2005 18:17:23 -0000
Links: << >>  << T >>  << A >>
Mike

Point1- You can instantiate components including CC8CE. When you use them as 
components the synthesiser will normally consider them as a "black box" and 
does nothing to them. It will attach signals to ports as defined in your 
verilog.

Point2 - Spot on.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Mike Oxlarge" <oxlargeMike@yahoo.com> wrote in message 
news:pan.2005.12.31.17.01.16.156231@yahoo.com...
> On Sat, 31 Dec 2005 13:53:43 +0000, John Adair wrote:
>
>> Mike
>>
>> You can use the CC8CE as an instantiated component if that is what you
>> want exactly. Details of the component are in the Xilinx Libraries Guide
>> which you can assess from the documentation with ISE tools or from the
>> Xilinx website.
>>
>> Often if you want to infer a particular component you need to use a
>> structure that the synthesiser lines up exactly to a expectation that
>> the synthesiser has for that component. That is usually difficult to do
>> and if you must have it then instantiate. CC8CE is also a macro element
>> and not a primative so may not be inferred by the sythesiser for that
>> reason. It may break your design down into smaller primative elements.
>>
>> Generally I would be more concerned that Verilog description has the
>> features that you need and is best checked with a simulator. Beyond that
>> setting and meeting timing constraints should be your other concern.
>>
>> John Adair
>> Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3
>> Development Board.
>> http://www.enterpoint.co.uk
>>
>
> Thanks for the speedy reply.
>
> So what I'm taking from your response is:
>
> 1. There is no way that I can simply say in my verilog code to use a
> CC8CE.
> 2. If by chance, my verilog code matched what the synthesizer was
> expecting, then it _may_ use a CC8CE.
>
> I understand that a counter in verilog is no big deal, but I'm having a
> tough time understanding why these design elements exist if there is no
> way to directly instantiate them. Like I said in my original post, I'm
> sure there are probably errors in my counter's design, so it would be nice
> to be able to "drop in" a known working element. In general, I think that
> this boils down to an issue of code-reuse, and me not yet at a point in my
> FPGA education of realizing how to take advantage of it. I'm hoping that I
> will learn that yes, there is a way to simply say "use this counter" or
> other design element, and feel confident that it was going to work.
>
> Thanks again for your response, and happy Hogmanay. 



Article: 93818
Subject: Why 'a plurality of N' must be used for 'N' in patent claims
From: wtxwtx@gmail.com
Date: 31 Dec 2005 16:33:04 -0800
Links: << >>  << T >>  << A >>
Hi,
Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in
patent claims?

What is the difference between them?

I found all patents I have checked if a number N (>0, or >1) is used,
'a plurality of N' or 'the plurality of N' must be used.

I checked with English disctionanry and still don't get any clue.

Thank you.

Weng


Article: 93819
Subject: basic DSP with FPGA
From: "drg" <drgenio@gmail.com>
Date: 31 Dec 2005 16:52:01 -0800
Links: << >>  << T >>  << A >>
Hi all, I'm new to FPGA stuff... i have an idea of making an audio
spectrum analyzer implemented on a fpga, displaying data on a VGA
monitor (spartan-3 starter kit). I guess I will need to filter the
audio data in some way (band pass filters for each channel?), and I
want to do it with the FPGA. That is, I'll get some ADC and plug it to
the FPGA, and then process the audio, first some basic filters for
audio manipulation (low pass, "bass boost", etc), and then move on to
something more complex..
Does anyone have some pointers of how to implement this kind of
filtering with FPGAs?

Regards,
Hernan

PS. Happy new year! (31/12/2005 9:51 PM here)


Article: 93820
Subject: Re: Brute Force Examination of a PLD
From: Eric Smith <eric@brouhaha.com>
Date: 31 Dec 2005 16:56:39 -0800
Links: << >>  << T >>  << A >>
"logjam" <grant@cmosxray.com> writes:
> However now I am confused why PALs slowed the counterfeiting of
> computers in the early 80s.  I've read that PALs were used primarily
> for component reduction but that some companies used them in ways to
> slow down reverse engineering.

With PALs that have internal combinatorial feedback (non-registered outputs),
reverse-engineering can be significantly more challenging.

With CPLDs that have internal feedback from nodes that don't have external
visibility, it is WAY more challenging.

Article: 93821
Subject: Re: Brute Force Examination of a PLD
From: "Totally_Lost" <air_bits@yahoo.com>
Date: 31 Dec 2005 18:01:40 -0800
Links: << >>  << T >>  << A >>
Back in 1981 the founders of Fortune Systems wanted a secure serial
number device to deter theft of high value software on their M68K unix
machine.  A security consultant came up with using registered Pals to
provide several uniqe sequencies that produced both a box ID andf group
ID that could independently be used to lock software to a machine, or
group of machines. Major businesses could order multiple of these
machines, then purchase a site license for the software which was group
locked. The scheme repeated ID's about every 1,000 or some PALs, which
ment that for the roughly 100,000 of the machines produced, each had
about 100 identical twins, very unlikely to ever be in the same
building/organization.

The company wanted an NDA with very heavy post employment restrictions
to be aware of the algorithms used, to protect the secrecy of the
product protection strategy, which I and a few others refused.

After I left the company, it took a couple hours with a logic analyzer
to defeat it. There wasn't a better choice in 1981 of devices. A few
years later when GAL's started being popular you could actually build
devices much harder to defeat.


Article: 93822
Subject: Re: Brute Force Examination of a PLD
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 01 Jan 2006 15:04:33 +1300
Links: << >>  << T >>  << A >>
logjam wrote:

> That's good news Antti, thanks!
> 
> However now I am confused why PALs slowed the counterfeiting of
> computers in the early 80s.  I've read that PALs were used primarily
> for component reduction but that some companies used them in ways to
> slow down reverse engineering.
> 
> Was it just that a computer with I/O resources, memory, and human
> knowledge of electronics slowed down the reproduction?

That, and also that something had to be copied, and so that implies
a more-legally-risky path for the copier.

> This is assuming of course that the computer is processing and reducing
> the test results itself.  That program/algorithm is still beyond me at
> this point.  Does anyone have any ideas on a program or algorithm
> written?  A book about this process?

If you have a universal programmer, they have vector testing
abilities - you can create the vectors manually, either with a text
editor, or on the PGMR itself, or with a PGM like Atmel's WinCUPL.
You can also them PGM a new copy, using a 16V8

As a first pass, you would use the programmer'd editor, to check
simple dependencies.
The same Vector file can be used to verify your RevEngineered version.

Here is an example of a 20 Pin PLD JED file, Test vector section :

Input values are 0,1,X and output values are H,L,Z
X tests both 0 & 1, but a string of XXXXX does not
usually do 32 tests.


*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 011110000NXHLHHL1H1N
*V0002 011110000NXHLHHL0H1N
*V0003 011110000NXHLHHL1H1N
*V0004 001110000NXLHHHL1H1N
*V0005 011010000NXLHHHL1H1N
*V0006 010110000NXLHHHL1H1N
*V0007 011100000NXLHHHL1H1N
*V0008 011110000N0HLHHL0H0N
*V0009 111110000N0HHLHH0H0N
*V0010 011110000N0HLHHL0H0N
*V0011 101110000N0HHLHH0H0N
*V0012 011110000N0HLHHL0H0N
*V0013 111010000N0HHLHH0H0N
*V0014 011110000N0HLHHL0H0N
*V0015 110110000N0HHLHH0H0N


Article: 93823
Subject: Re: basic DSP with FPGA
From: "Binary" <binary.chen@gmail.com>
Date: 31 Dec 2005 19:23:11 -0800
Links: << >>  << T >>  << A >>
opencores.org


Article: 93824
Subject: Re: basic DSP with FPGA
From: Tim Wescott <tim@seemywebsite.com>
Date: Sat, 31 Dec 2005 21:36:29 -0800
Links: << >>  << T >>  << A >>
drg wrote:

> Hi all, I'm new to FPGA stuff... i have an idea of making an audio
> spectrum analyzer implemented on a fpga, displaying data on a VGA
> monitor (spartan-3 starter kit). I guess I will need to filter the
> audio data in some way (band pass filters for each channel?), and I
> want to do it with the FPGA. That is, I'll get some ADC and plug it to
> the FPGA, and then process the audio, first some basic filters for
> audio manipulation (low pass, "bass boost", etc), and then move on to
> something more complex..
> Does anyone have some pointers of how to implement this kind of
> filtering with FPGAs?
> 
This is basic DSP stuff.  At its most basic you're just implementing the 
math on an FPGA; in reality you're going to be doing a bunch of messing 
around with the details of the process.

You really need to know three things: DSP, FPGA design, and optimizing 
FPGA designs for DSP.  For the DSP part of it I recommend "Understanding 
Digital Signal Processing" by Rick Lyons.  I learned logic design by 
osmosis, so I can't recommend any one text.  When you get to the part of 
merging the two onto a real, live FPGA I'd check the Xilinx web site for 
app notes.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com



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