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On 29 Sep, 16:34, cs_post...@hotmail.com wrote: > On Sep 29, 11:15 am, Benjamin Krill <b...@codiert.org> wrote: > > > You have to include the FPGA host (mac and ip) into the ARP table of the > > host PC. Then you didn't need to implement the ARP protocol. > > I don't think that will be needed, since the PC is not expected to > reply. > > I suppose there might be software on the PC that would consider this > "traffic from nowhere" suspicious and possibly forged, but that's a > configuration problem, not a fundamental one. Many thanks for the replies. I wasn't sure if I needed to add my MAC and IP address to the PC ARP table, or if it would be added by default once I had sent a packet. It would be nice if this was a purely one way transmission. Thanks again.Article: 135376
On Mon, 2008-09-29 at 08:34 -0700, cs_posting@hotmail.com wrote: > > I don't think that will be needed, since the PC is not expected to > reply. > > I suppose there might be software on the PC that would consider this > "traffic from nowhere" suspicious and possibly forged, but that's a > configuration problem, not a fundamental one. Sure, software which listen on a port and capture/evaluate the sent data are also needed. But the host pc needs to arp entry to recognize the FPGA (the other host).Article: 135377
Benjamin Krill <ben@codiert.org> wrote: >Hi, > >On Mon, 2008-09-29 at 08:10 -0700, Fred wrote: >> Do I require any ARP or any other protocol? Will it just work, with >> the destination PC receiving UDP packets? > >You have to include the FPGA host (mac and ip) into the ARP table of the >host PC. Then you didn't need to implement the ARP protocol. That won't be necessary. You don't even have to know the IP & MAC address of the destination if you broadcast the data. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135378
Benjamin Krill <ben@codiert.org> wrote: >On Mon, 2008-09-29 at 08:34 -0700, cs_posting@hotmail.com wrote: >> >> I don't think that will be needed, since the PC is not expected to >> reply. >> >> I suppose there might be software on the PC that would consider this >> "traffic from nowhere" suspicious and possibly forged, but that's a >> configuration problem, not a fundamental one. > >Sure, software which listen on a port and capture/evaluate the sent >data are also needed. But the host pc needs to arp entry to recognize >the FPGA (the other host). That is only required when sending data, not when receiving it. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135379
"KJ" <kkjennings@sbcglobal.net> wrote: > >"Nico Coesel" <nico@puntnl.niks> wrote in message >news:48dfe4ee.168426254@news.planet.nl... >> jhallen@TheWorld.com (Joseph H Allen) wrote: >> >> An easier way without the extra jitter is to use an >> output flipflop (aka DDR flipflop) which can be clocked using 2 >> clocks. The first clock sets the output, the second clock (inverted >> first clock) resets the output. And presto, you'll have a clock output >> which is (within pin-to-pin skew) perfectly synchronous to the other >> outputs. >> > >Hold time requirements (like the .4ns in the OP) will be impossible to >guarantee with this method though. A slightly longer PCB track will do that for you. But that won't work on a pre-made board because you can't alter the PCB. Still, if the OP uses an off the shelf board the designer should have thought about these sort of things... Perhaps the OP could ask them. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135380
On Sep 29, 1:11=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > "KJ" <kkjenni...@sbcglobal.net> wrote: > > >"Nico Coesel" <n...@puntnl.niks> wrote in message > >news:48dfe4ee.168426254@news.planet.nl... > >> jhal...@TheWorld.com (Joseph H Allen) wrote: > > >> An easier way without the extra jitter is to use an > >> output flipflop (aka DDR flipflop) which can be clocked using 2 > >> clocks. The first clock sets the output, the second clock (inverted > >> first clock) resets the output. And presto, you'll have a clock output > >> which is (within pin-to-pin skew) perfectly synchronous to the other > >> outputs. > > >Hold time requirements (like the .4ns in the OP) will be impossible to > >guarantee with this method though. > > A slightly longer PCB track will do that for you. Slightly? The OP estimated the PCB traces at ~1 inch. To add .4 ns of delay (the hold time requirement of the SRAM) would require adding ~2.5 inches of trace. Tommy eyeballed the existing traces at ~1 inch. To do what you suggest would require adding 2.5x of the existing trace to each and every address/control signal on something that is running ~200 MHz...not the sort of thing one would design into a board...at least not intentionally. KJArticle: 135381
Hi everyone, I'm having a hell of a time trying to get an a/d pmc module working on a PMC_SPAN extension card on a MVME 5500 motherboard. I have the 2 PMC slots on the 5500 card populated with 2 VMetro FPGA01 PMC cards and they seem to work ok. After the system boots and I do a PCIDeviceShow(0) and I see devices 0 (host PCI bridge?),6 (First FPGA01 card) and 10 (PCI2PCI Bridge). PCIDeviceShow(1) shows devices 0,6 and 10 also with 6 being the 2nd FPGA01 card. PCIDeviceShow(2) or (3) show no signs of my a/d card? I've attached a PDF file that shows the internal debug statements generated during autoconfiguration. In it certainly looks like device 10 on bus 0 is acting as a bridge to the a/d card and it looks like it is being configured ok as far as I can tell. However after VxWorks boots I have tried using PCIFindDevice with the Vendor Id etc. to find the a/d card without success. I can use the input output calls (pciConfigWordLongIn/out etc) to talk to the FPGA01 cards but not the a/d. It seems like the bridge is not working but it seemed to work ok during auto config? Does anyone see what might be going on from the included dump file? Any help is appreciated. Chuck W.Article: 135382
Hi, I am trying to simulate a EDK system based on microblaze. I have 10 slaves and one of the slave is a mpmc(4.02.a) and has microblaze i/d cache connections on 2 ports and a external DDR interface on third port. I have a simple program that performs read and write to register bits in each of the slaves. All the slaves on the bus are responding except mpmc. When I tried to probe I found out that the "MPMC_InitDone" stayed low for a long time. Seems like ddr never initializes there by the slave interface(SPLB2) on mpmc doesn't respond to read/write to ddr. EDK Version : 10.1 SP2. Below is mpmc definition in my mhs file. ----------------------------------------------------- BEGIN mpmc PARAMETER INSTANCE = mpmc_0 PARAMETER HW_VER = 4.02.a PARAMETER C_FAMILY = virtex5 PARAMETER C_PIM0_BASETYPE = 1 PARAMETER C_PIM1_BASETYPE = 1 PARAMETER C_PIM2_BASETYPE = 2 PARAMETER C_NUM_PORTS = 3 PARAMETER C_MPMC_BASEADDR = 0xEC000000 PARAMETER C_MPMC_HIGHADDR = 0xEFFFFFFF # ### Memory and Memory Part Parameters PARAMETER C_MEM_TYPE = DDR PARAMETER C_MEM_PARTNO = MT46V32M16-6 PARAMETER C_MEM_PART_TDQSS = 1 PARAMETER C_MEM_PART_TAL = 0 PARAMETER C_MPMC_CLK0_PERIOD_PS = 11740 PARAMETER C_MEM_CLK_WIDTH = 1 PARAMETER C_MEM_CE_WIDTH = 1 PARAMETER C_MEM_CS_N_WIDTH = 1 PARAMETER C_MEM_DATA_WIDTH = 16 PARAMETER C_MEM_BITS_DATA_PER_DQS = 8 PARAMETER C_MEM_NUM_RANKS = 1 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y1 PARAMETER C_XCL0_WRITEXFER = 0 PARAMETER C_SPLB2_NATIVE_DWIDTH = 32 PARAMETER C_SKIP_SIM_INIT_DELAY = 1 BUS_INTERFACE SPLB2 = mb_plb # ### PORT MPMC_Clk0 = sys_clk_s PORT MPMC_Clk90 = sys_clk90_s PORT MPMC_Clk_200MHz = cpu_ddr_idelay_clk PORT MPMC_Rst = sys_rst_s PORT SPLB2_Clk = sys_clk_s PORT SPLB2_Rst = sys_rst_s PORT MPMC_InitDone = ddr_init_done # ### PORT DDR_Clk = ddr_clk PORT DDR_Clk_n = ddr_clk_n PORT DDR_CE = ddr_cke PORT DDR_CS_n = ddr_cs_n PORT DDR_RAS_n = ddr_ras_n PORT DDR_CAS_n = ddr_cas_n PORT DDR_WE_n = ddr_we_n PORT DDR_BankAddr = ddr_ba PORT DDR_Addr = ddr_a PORT DDR_DQ = CPU_DDR_DQ PORT DDR_DM = ddr_dqm PORT DDR_DQS = CPU_DDR_DQS END -------------------------------------------------- I have checked clocks and reset and they are fine. I appreciate if anyone can point me in right direction. Thanks RaoArticle: 135383
(comp.protocols.tcp-ip added) Fred wrote: > I've been tasked to write some code for an FPGA to interface to 10BASE- > T Ethernet using differential drivers and receivers. > The information is one way, transmit only! I will have an IP address > within the network range, give myself a MAC number and know the MAC > and IP address of the destination PC. > Do I require any ARP or any other protocol? Will it just work, with > the destination PC receiving UDP packets? Normally you would use ARP to find the destination MAC given the IP address. Since you seem to already know it, you shouldn't need ARP. If you don't need to receive, or the sender already knows your MAC address then you don't need to receive and reply to ARP. (Most will add you to the ARP table on receiving your data. The entry will eventually time out, though.) You could also broadcast. (Set the destination to X'ffffffffffff'). That isn't recommended if there are other hosts on the net, and it might be that some IP implementations ignore broadcast packets without a broadcast IP address. -- glenArticle: 135384
In comp.protocols.tcp-ip glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > (comp.protocols.tcp-ip added) > Fred wrote: > > I've been tasked to write some code for an FPGA to interface to > > 10BASE- T Ethernet using differential drivers and receivers. > > The information is one way, transmit only! I will have an IP > > address within the network range, give myself a MAC number and > > know the MAC and IP address of the destination PC. > > Do I require any ARP or any other protocol? Will it just work, > > with the destination PC receiving UDP packets? > Normally you would use ARP to find the destination MAC given the IP > address. Since you seem to already know it, you shouldn't need ARP. > If you don't need to receive, or the sender already knows your MAC > address then you don't need to receive and reply to ARP. (Most will > add you to the ARP table on receiving your data. The entry will > eventually time out, though.) Is the destination "always" going to be in the same broadcast domain as the FPGA? If so, then why bother with IP and UDP? The only value IP adds in this case would seem to be fragmentation and reassembly, but then only if you implement fragmentation in your FPGA. If the destination can be "remote" (on the other side of an IP router) then there are a rather large host (as it were) of things expected of an IP implementation besides just "slap a header on there and go" described in a number of the RFC's one can find at places such as www.ietf.org. rick jones -- No need to believe in either side, or any side. There is no cause. There's only yourself. The belief is in your own precision. - Jobert these opinions are mine, all mine; HP might not want them anyway... :) feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...Article: 135385
On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <raonpc@gmail.com> wrote: >Hi, > > I am trying to simulate a EDK system based on microblaze. > I have 10 slaves and one of the slave is a mpmc(4.02.a) and has > microblaze i/d cache connections on 2 ports and a external DDR >interface > on third port. > I have a simple program that performs read and write to register > bits in each of the slaves. All the slaves on the bus are responding > except mpmc. When I tried to probe I found out that the >"MPMC_InitDone" > stayed low for a long time. What is "a long time" in this context? Remember that a full initialisation sequence for DDR memory is supposed to take slightly over 200 us. Which is quite a long time in a simulator. How long is your simulation? - BrianArticle: 135386
Rick Jones wrote: (snip) >>Fred wrote: >>>I've been tasked to write some code for an FPGA to interface to >>>10BASE- T Ethernet using differential drivers and receivers. (snip, then I wrote) >>Normally you would use ARP to find the destination MAC given the IP >>address. Since you seem to already know it, you shouldn't need ARP. >>If you don't need to receive, or the sender already knows your MAC >>address then you don't need to receive and reply to ARP. (Most will >>add you to the ARP table on receiving your data. The entry will >>eventually time out, though.) > Is the destination "always" going to be in the same broadcast domain > as the FPGA? If so, then why bother with IP and UDP? The only value > IP adds in this case would seem to be fragmentation and reassembly, > but then only if you implement fragmentation in your FPGA. It means you don't have to do so much work on the receiver if it already has IP running. In many cases, it isn't easy to receive raw data on a host already running IP. Adding the UDP header is pretty easy. You can even put in zero for the checksum to ignore it. You still have to generate the ethernet CRC, though. > If the destination can be "remote" (on the other side of an IP router) > then there are a rather large host (as it were) of things expected of > an IP implementation besides just "slap a header on there and go" > described in a number of the RFC's one can find at places such as > www.ietf.org. Well, you need the MAC address of the router instead of the destination host. Implementing route redirect would be nice, but not needed. Otherwise, just adding a UDP header should work. You might also want source quench or some kind of flow control. For transmit only you can't use the reply packets for flow control. -- glenArticle: 135387
On Sep 29, 4:22=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <rao...@gmail.com> wrote: > >Hi, > > > =A0I am trying to simulate a EDK system based on microblaze. > > =A0I have 10 slaves and one of the slave is a mpmc(4.02.a) and has > > =A0microblaze i/d cache connections on 2 ports and a external DDR > >interface > > =A0on third port. > > =A0I have a simple program that performs read and write to register > > =A0bits in each of the slaves. All the slaves on the bus are responding > > =A0except mpmc. When I tried to probe I found out that the > >"MPMC_InitDone" > > =A0stayed low for a long time. > > What is "a long time" in this context? > > Remember that a full initialisation sequence for DDR memory is supposed > to take slightly over 200 us. Which is quite a long time in a simulator. > > How long is your simulation? > > - Brian Hi Brian, Thanks for the tip. I caught this init_done at almost 580us. I was expecting very short init_done as I was setting "PARAMETER C_SKIP_SIM_INIT_DELAY =3D 1". You saved lot of time as I was thinking of ripping the design to have only mpmc for the debug. Thanks again RaoArticle: 135388
In article <gbribf$q3i$6@usenet01.boi.hp.com>, Rick Jones <rick.jones2@hp.com> wrote: >Is the destination "always" going to be in the same broadcast domain >as the FPGA? If so, then why bother with IP and UDP? The only value >IP adds in this case would seem to be fragmentation and reassembly, >but then only if you implement fragmentation in your FPGA. > >If the destination can be "remote" (on the other side of an IP router) >then there are a rather large host (as it were) of things expected of >an IP implementation besides just "slap a header on there and go" >described in a number of the RFC's one can find at places such as >www.ietf.org. My answer to the question at the start is that in the real world there are *always* situations where the absolutely guaranteed for certain always and forever promise that there will never be a router is broken. Therefore the low the costs of slapping fake but servicable UDP/IP headers in front of the payload are so low that you can't afford not to pay them. There are always test networks if the promises about no routers are always and forever met when the application is deployed...and the promises usually are broken in some deployed case. Vernon Schryver vjs@rhyolite.comArticle: 135389
vlodiya@gmail.com writes: > Guys, > > I am designing a conventional Digital down converter on virtex > -4 Sx55 FPGA for GSM applications. > > The Input clock frequency is above 160 Mhz for the initial CIC > decimation filter. After decimation , the data is fed to low pass > filter at a very low rate of ~1 Mhz > > The issue is ,I am not able to generate this low frequency clcok with > Virtex -4 DCM , obviously the min output frequency is 32 Mhz. > > After I looked into the previous threads , i dont feel its a clean way > to generate the divided clock by internal clock divider or clock > gating circuit in FPGA . > > Can anyone let me know any other way of generating the low frequency > clock or is it safe to use internal clock divider considering my > asynchronous design ( FIFO between each filter stage) ? > > Iam using the latest FIR compiler to generate the LP filter core. but > i do see the option of input sample per no of clock cycles in > previous Distributed FIR core which made life easy. but the FIR > compiler core doesnt have this option. > > Please advice > > Thanks in Advance > > Vijay I'm certainly no expert in the field of hardware design, but I've had good luck using the master clock signal and an 'enable' that runs at the desired clock speed. I've successfully used this technique to divide the Spartan 3E 50MHz clock down to 230Khz for serial port transmission. I'd be happy to provide the entity which produces the 'enable' signal and an example of how to use it if you're interested. thutt -- Hoegaarden!Article: 135390
Hi All, I have one basic doubt what will happen if the data throughput is greater than the Clock Speed. What are the possible violations. If clock has higher speed than the Data Throughput. Thanks SrikArticle: 135391
On 30 Sep., 08:06, "ekavirsrika...@gmail.com" > I have one basic doubt what will happen if the data throughput is > greater than the Clock Speed. The only thing that might go wrong is that its not working. But it is in principle no problem to have higher data throughput than clock speed (DDR, parallelism,..) > What are the possible violations. If > clock has higher speed than the Data Throughput. I want to build a car, what mistakes could happen if I allready know that it needs 4 wheels touching ground? I guess your real question is a bit different, so maybe you like to reformulate your question. bye ThomasArticle: 135392
XMOS has just announced a $99 dev kit for their XC-1 device. I've put my name down for one: https://products.xmos.com/ I used to work with transputers, it's nice to see that the concept has been resurrected. LeonArticle: 135393
On Mon, 29 Sep 2008 17:14:57 -0700 (PDT), rao <raonpc@gmail.com> wrote: >On Sep 29, 4:22 pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Mon, 29 Sep 2008 14:17:50 -0700 (PDT), rao <rao...@gmail.com> wrote: >> >Hi, >> >> > When I tried to probe I found out that the >> >"MPMC_InitDone" >> > stayed low for a long time. >> >> What is "a long time" in this context? >> >> Remember that a full initialisation sequence for DDR memory is supposed >> to take slightly over 200 us. Which is quite a long time in a simulator. >> >> How long is your simulation? >> >> - Brian > >Hi Brian, > Thanks for the tip. I caught this init_done at almost 580us. > > I was expecting very short init_done as I was setting > "PARAMETER C_SKIP_SIM_INIT_DELAY = 1". > > You saved lot of time as I was thinking of ripping the design > to have only mpmc for the debug. To be honest, 580 us would surprise me too, but I don't know the internal details of MPMC. If it needs some intervention from the host (PPC or Microblaze), that would explain it. I would also double-check what is happening with C_SKIP_SIM_INIT_DELAY. Does initialisation take another 200 us without it? Anyway I am glad the simulation is basically working. - BrianArticle: 135394
Hi, I am using Virtex - 2pro Board of Xilinx, I am actually getting an image from expansion connectors and then saving it in the DDR RAM as my project. I am new to FPGAs and EDK v10.1 and have no information about how to interface the. I have read tutorials from Xilinx but none of them give any info about interfacing with Memory devices and expansion connectors. Moreover, i also wana save and retrieve data from FLASH CARD. I know that XilFATfs is a library used for this but i dont know how to use it... please provide me some tutorials and give me some links about how to do it...i would be very very thankful to u all... mail me at msfarooq@gmail.com Regards, SaadArticle: 135395
>Hi All, > >I have one basic doubt what will happen if the data throughput is >greater than the Clock Speed. What are the possible violations. In summary, lost data. > If clock has higher speed than the Data Throughput. If the clock is not synchronised to the data, the clock frequency must be more than twice the maximum data rate. http://www.google.com/search?hl=en&q=nyquist+sampling+theoryArticle: 135396
Hi, I want to perform reasonable post place&route timing analysis for some RTL modules. The modules have a higher pin count as the FPGA itself. ISE always tries to map the modules I/Os to specific IO pads, so its not possible to make post P&R timing analysis for such (internally used) modules. The post synthesis timing is unrealistic, so how can I get a timing estimation including wire delay for dedicated modules? Any ideas?Article: 135397
On Sep 30, 12:08=A0pm, Heiner Litz <heinerl...@googlemail.com> wrote: > Hi, > > I want to perform reasonable post place&route timing analysis for some > RTL modules. The modules have a higher pin count as the FPGA itself. > ISE always tries to map the modules I/Os to specific IO pads, so its > not possible to make post P&R timing analysis for such (internally > used) modules. > > The post synthesis timing is unrealistic, so how can I get a timing > estimation including wire delay for dedicated modules? > > Any ideas? Create a wrapper around your module and place flip flops clocked by the appropriate clock (or clocks) on all of the inputs and outputs of your module. KJArticle: 135398
Kevin Neilson wrote:
> Sure, you can determine that a LUT with a INIT code of FFFE is an
> inverter.
thutt wrote:
> Can you point me to a reference that shows how to do this?
Any textbook on digital logic!
You have a logic circuit with four inputs, with the truth table:
ABCD Q ABCD Q
---- - ---- -
0000 1 1000 1
0001 1 1001 1
0010 1 1010 1
0011 1 1011 1
0100 1 1100 1
0101 1 1101 1
0110 1 1110 1
0111 1 1111 0
It should be immediately obvious that the circuit is a four-input NAND, and
that if any three inputs are tied high, Q is the inverse of the fourth input.
Article: 135399Heiner Litz wrote: > Hi, > > I want to perform reasonable post place&route timing analysis for some > RTL modules. The modules have a higher pin count as the FPGA itself. > ISE always tries to map the modules I/Os to specific IO pads, so its > not possible to make post P&R timing analysis for such (internally > used) modules. > > The post synthesis timing is unrealistic, so how can I get a timing > estimation including wire delay for dedicated modules? > > Any ideas? If the problem is that you don't have enough pins on the device, you could make sure all the I/O are registered, instruct the synthesizer not to add IOB pads, and put syn_keep or syn_preserve (or whatever) HDL directives on the I/O registers to make sure they don't get pruned. Then you could have a static timing analysis even though no pins are connected. You won't be able to easily use this for a simulation, since none of the I/Os will come out to top-level ports. -Kevin
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