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I've initiated the component and the instance according to the .vho files created along when I created my FIFO with the core generator. I've copied all the files into the same directories, but i just get the below error: # ** Warning: (vsim-3473) Component instance "inst_fifo_generator_v4_2_16k : fifo_generator_v4_2_16k" is not bound. how? thanksArticle: 133801
On Jul 15, 12:30=A0pm, Zhane <m...@hotmail.com> wrote: > I've initiated the component and the instance according to the .vho > files created along when I created my FIFO with the core generator. > > I've copied all the files into the same directories, but i just get > the below error: > > # ** Warning: (vsim-3473) Component instance > "inst_fifo_generator_v4_2_16k : fifo_generator_v4_2_16k" is not bound. > > how? > > thanks It means that there is no source file that you have compiled with Modelsim that has any entity/architecture called 'fifo_generator_v4_2_16k'. KJArticle: 133802
I need help with immediate delivery of two Virtex 4 FPGA's. The part numbers are XC4VLX80-11FFG1148C (50pcs) and XC4VLX25-11FFG668C (25pcs). Anything that you can do is appreciated. Regards, Jon E. Hansen (949)864-7745Article: 133803
Hi, I'm having the same exact problem with ISE 7.1 and the Spartan 3e starter kit. anyone have any ideas? Malik >i have got a problem while i am generating bit file using xilinx ise >7.1i for spartan 3E device i am getting warining as > > warning: Bitgen:26 - bitgen only supports DRC on this device. >Error: bitgen failed >Reason: >Process "Generate Programming File" did not complete. > >i am using xilinx webpack what the cause of the problem for this >warning as a result i am unable to generate the bit file which is used >for downloading to the kit. > >what kind of possible mistakes may result this kind of errors. or else >i need to update the software IP downloads .......... > >give me some sort of suggestion................... if at all to update >bitgen how can i proceed since i am beginner i need some guidence > > >thanks and regards, >srik > >Article: 133804
> >"Göran Bilski" <goran.bilski@xilinx.com> wrote in message >news:f9h3ki$d1v1@cnn.xilinx.com... >> Hi Fred, >> >> XPS keeps track of the .mhs settings for each core and stores a copy for >> it in implementation/cache >> >> So what I usually do is to go in the implementation directory and deletes >> the files associated with the core. >> So when I work with microblaze I delete the microblaze_0_wrapper.ngc in >> the implementation and in implementation/cache >> In order to for a new system to be generated, I just touch the system.mhs >> file since this is a file that is used in the makefile. >> Now just microblaze will be regenerated when I generated a bitfile. >> >> On other option that I use with MicroBlaze is to change a parameter in the >> .mhs file which don't change the actual implementation. >> Ex. if I don't have HW debug enabled, I can freely change the number of >> breakpoints in the .mhs. >> XPS will see a difference of the parameter settings in the .mhs file >> compared to the cached version and will regenerate the core >> > >I have tried deleting the files and directory in the "implementation" >directory and this doesn't update the design. I have since noticed there is >a synthesis directory and perhaps I should have deleted the files there as >well. > >Many thanks for your help.. > > > You may also note a directory in the implementation folder called "cache". Within it you will find a cached .ngc of your design. If you delete the single ngc residing in the implementation folder, the ngc in the cached folder will be copied as well. I have a script that deletes the ngc from the implementation foler, the cached folder, the system.ngc, the system.bit, and the download.bit. And I never have to worry. Right now I'm suffering a problem of the synthesis running for ever. It almost looks like it's stuck in a recursive loop, but it finally runs map hours later. Don't know where to go from here... From me@home.org Tue Jul 15 13:09:43 2008 Path: unlimited.newshosting.com!dartmaster!s03-b18.iad01!s02-b12.iad01!nx01.iad01.newshosting.com!newshosting.com!83.128.0.12.MISMATCH!news-out2.kabelfoon.nl!newsfeed.kabelfoon.nl!xindi.nntp.kabelfoon.nl!feeder.erje.net!news2.arglkargh.de!news.karotte.org!feeder06.uucp-net.de!news.uucp.at!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <487d0408$0$25949$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <me@home.org> Subject: Re: ps2 mouse initialization fails Newsgroups: comp.arch.fpga Date: Tue, 15 Jul 2008 22:09:43 +0200 References: <4877c1ba$0$25950$6e1ede2f@read.cnntp.org> <g5et1b$jqs$1@news.uni-kl.de> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 34 Organization: CNNTP NNTP-Posting-Host: 87e7cae6.read.cnntp.org X-Trace: DXC=ZJOYG5h9e\ocd>EK;k8V7nWoT\PAgXa?a`81AK\eERfkCWCf629N19dhldKiGb`JFmX2=`gSnYFAnlPE<4KL_GTc X-Complaints-To: abuse@cnntp.org Xref: unlimited.newshosting.com comp.arch.fpga:109355 Matthias Alles wrote: > Hi Thorsten! > >> 1. http://www-user.rhrk.uni-kl.de/~alles/fpga/files/fractal.tgz >> (gets stuck in state "send") > > In that case the mouse didn't initialize the own clock signal. What is > the clock frequency you use? Did you adapt the constants in the VHDL > file such that you drive the clock signal to zero for 100 us (or maybe > longer)? You have to change the lines 135 and 144 according to your > clock frequency. > > Matthias > > > >> 2. from the book "FPGA prototyping by VHDL examples" >> (gets stuck in state "start") >> >> Does anyone have any suggestions ? >> btw. the keyboard works fine. >> I have the digilent spartan 3 starter kit. >> >> Best Regards >> Thorsten >> Hi Mathias, my clock frequency is 50MHz, the same as yours, I guess ;) Best Regads ThorstenArticle: 133805
On Jul 15, 11:56=A0am, jon <j...@pyramidemail.com> wrote: > I need help with immediate delivery of two Virtex 4 FPGA's. The part > numbers are XC4VLX80-11FFG1148C =A0(50pcs) and XC4VLX25-11FFG668C > (25pcs). Anything that you can do is appreciated. > > Regards, > Jon E. Hansen > (949)864-7745 These parts are neither exotic nor very new, nor very old. What does your trusty distributor say? It's his job to provide these parts That's what he is in business for... Peter Alfke, Xilinx ApplicationsArticle: 133806
Hai, Any anyone can list test cases to verify unified protocol. regards, rajArticle: 133807
On Jul 16, 1:03=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Jul 15, 12:30=A0pm, Zhane <m...@hotmail.com> wrote: > > > I've initiated the component and the instance according to the .vho > > files created along when I created my FIFO with the core generator. > > > I've copied all the files into the same directories, but i just get > > the below error: > > > # ** Warning: (vsim-3473) Component instance > > "inst_fifo_generator_v4_2_16k : fifo_generator_v4_2_16k" is not bound. > > > how? > > > thanks > > It means that there is no source file that you have compiled with > Modelsim that has any entity/architecture called > 'fifo_generator_v4_2_16k'. > > KJ thanks I forgot to add it into my ISE I'm sampling some stuffs at 33Mhz, and feeding into my FIFO at 33Mhz continuously. On the other side of my FIFO, I have it clocked at 50Mhz, sending the output to UART which transmit at 115200baud rate. It seems that my FIFO gets full quite often. Is there anything I can do? I tried using up all of my block rams and lowering the data width, but it doesnt help muchArticle: 133808
HI, on our PCB there is a LED directly connected to a Virtex5 I/O pad. The LED is connected through a series resistor to 3.3 V. As it seems Virtex devices do not support open-drain outputs. If I drive a zero on that output there will be current flowing from the 3.3V through the LED into the FPGA. Does the FPGA tolerate that? Which I/O standard/fashion should I use? regs, HeinerArticle: 133809
I'm in trouble, do you think that could be possible to program the FPGA from ethernet for this board ? Thanks, Antonio www.etantonio.itArticle: 133810
Target FPGA: Virtex II PRO I generated 2 designs including 4 AURORA single lane CORE each, configured in streaming : The first 4 are on bottom edge in the first design and the others are on TOP edge in the second design. While testing transmission with external hardware loopback, I got some lanes working well and others not. On the "bad" lanes, I detect received valid data while transmit is not activated. Depending on the lane, the received unexpected values are not the same and not at the same pace ( I implemented an error counter). With loopback "internal parallel mode" , I have no more errors but with "internal serial mode" I notice the same behaviour as with my external loopback. Could you help? Thanks in advanceArticle: 133811
Use a tristate output driver. On Wed, 16 Jul 2008 03:10:12 -0700 (PDT), Heiner Litz <heinerlitz@googlemail.com> wrote: >HI, > >on our PCB there is a LED directly connected to a Virtex5 I/O pad. The >LED is connected through a series resistor to 3.3 V. As it seems >Virtex devices do not support open-drain outputs. > >If I drive a zero on that output there will be current flowing from >the 3.3V through the LED into the FPGA. Does the FPGA tolerate that? >Which I/O standard/fashion should I use? > >regs, HeinerArticle: 133812
On Jul 16, 6:10 am, Heiner Litz <heinerl...@googlemail.com> wrote: > HI, > > on our PCB there is a LED directly connected to a Virtex5 I/O pad. The > LED is connected through a series resistor to 3.3 V. As it seems > Virtex devices do not support open-drain outputs. > > If I drive a zero on that output there will be current flowing from > the 3.3V through the LED into the FPGA. Does the FPGA tolerate that? > Which I/O standard/fashion should I use? > > regs, Heiner Take a look at the Vcco for the bank that drives the LED. If it is 3.3V you don't need open-drain, as a CMOS output high will turn off the LED just as well. If the Vcco is lower than 3.3v you should use the equivalent of open-drain, which is to tie the output signal low and use the tristate function to turn on or off the LED. In Verilog this would be like: assign LED_PIN = drive_led ? 0 : 1'bZ; If Vcco is much lower than 3.3V, i.e. lower than 3.3v - Vf of the LED, you may have problems with the LED staying on even if you use open drain outputs due to the protection diodes on the FPGA I/O pin. HTH, GaborArticle: 133813
On Jul 16, 5:39=A0am, Zhane <m...@hotmail.com> wrote: > On Jul 16, 1:03=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > > > On Jul 15, 12:30=A0pm, Zhane <m...@hotmail.com> wrote: > > > > I've initiated the component and the instance according to the .vho > > > files created along when I created my FIFO with the core generator. > > > > I've copied all the files into the same directories, but i just get > > > the below error: > > > > # ** Warning: (vsim-3473) Component instance > > > "inst_fifo_generator_v4_2_16k : fifo_generator_v4_2_16k" is not bound= . > > > > how? > > > > thanks > > > It means that there is no source file that you have compiled with > > Modelsim that has any entity/architecture called > > 'fifo_generator_v4_2_16k'. > > > KJ > > thanks > I forgot to add it into my ISE > > I'm sampling some stuffs at 33Mhz, and feeding into my FIFO at 33Mhz > continuously. > > On the other side of my FIFO, I have it clocked at 50Mhz, sending the > output to UART which transmit at 115200baud rate. > > It seems that my FIFO gets full quite often. Is there anything I can > do? > Send less data or send it slower. Communication paths are always limited by the slowest element, in this case it is the 115,200 baud serial link. Basic math suggests that ~11KB/sec is the best that any UART could possibly handle (8 data, 1 start, 1 stop bit). Since you're putting stuff in at 33MB/sec (assuming that you're putting a byte in every 33MHz clock...not sure from your description) this means that your system is producing data at 3x the rate that you can pull it out. The choice of using a UART to send your data is fundamentally flawed, so you need to - Drastically cut down on the amount of data sent to the UART - Run the UART at a non-standard 3x (minimum) higher rate, which presumes that whatever is on the other end of the serial link can also run at that higher rate. - Use a different interface that can run faster (USB as an example). - Buffer the data in memory and transmit data from memory to the UART. None of the above solutions are necessarily possible for your particular situation, they are meant to get you thinking. Now you've got to sit down and figure out a solution based on whatever your actual constraints and functional requirements are. > I tried using up all of my block rams and lowering the data width, but > it doesnt help much- Hide quoted text - > Unless the overall amount of data is limited (many times it is) than no amount of memory will work because the input rate is 3x the available transmission rate. Many times though data comes in in a burst and then there is dead time before the next burst. If that's the case in your situation AND the dead time is at least 2x of the data time then the absolute minimum amount of memory you'd need would be on the order of 2/3 the maximum total amount received. For example, if you'll be receiving at most 3.3MB of data at 33 MHz then the data will be coming in for ~0.1 seconds and it will take you approximately 0.3 seconds to send it out the UART. If the next 3.3 MB starts coming in 0.3 sec after the first then you'll need a memory buffer that is at least 2.2 MB in size and you should be able to just squeak it out. You'd be running right on the edge, but if you know your data rates and sizes such a system can be designed. Good luck Kevin JenningsArticle: 133814
On Jul 16, 5:39 am, Zhane <m...@hotmail.com> wrote: > On Jul 16, 1:03 am, KJ <kkjenni...@sbcglobal.net> wrote: > > > > > On Jul 15, 12:30 pm, Zhane <m...@hotmail.com> wrote: > > > > I've initiated the component and the instance according to the .vho > > > files created along when I created my FIFO with the core generator. > > > > I've copied all the files into the same directories, but i just get > > > the below error: > > > > # ** Warning: (vsim-3473) Component instance > > > "inst_fifo_generator_v4_2_16k : fifo_generator_v4_2_16k" is not bound. > > > > how? > > > > thanks > > > It means that there is no source file that you have compiled with > > Modelsim that has any entity/architecture called > > 'fifo_generator_v4_2_16k'. > > > KJ > > thanks > I forgot to add it into my ISE > > I'm sampling some stuffs at 33Mhz, and feeding into my FIFO at 33Mhz > continuously. > O.K. so data comes in continuously at 33 MHz and ?? bits wide. > On the other side of my FIFO, I have it clocked at 50Mhz, sending the > output to UART which transmit at 115200baud rate. > O.K. so data goes out at 115.2 KHz or 0.1152 MHz and one bit wide using at best 8 of every 10 clock cycles at that frequency. > It seems that my FIFO gets full quite often. Is there anything I can > do? > 1) Decide how long you need this "continuous" data to run and make the FIFO deep enough to handle that much data. 2) Add about 286 more UARTs per input bit. 3) Raise the UART bandwidth to 33 MHz times the input bit width. 4) Consider a job in the food-service industry :) > I tried using up all of my block rams and lowering the data width, but > it doesnt help much It had to help some... How much it helps depends on how much data you really need to collect. If you want megabytes of continuous data, you either need to find a higher-bandwidth output channel or use external memory like SDRAM. You realize that even with one input bit at 33 MHz, your output bandwidth will limit you to your FIFO depth plus about 0.3% (the amount drained in the time it takes the FIFO to fill up). Regards, GaborArticle: 133815
On Jul 16, 8:52=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Jul 16, 5:39=A0am, Zhane <m...@hotmail.com> wrote: Woops, failed basic mathematics myself on the previous post. 115200 baud will translate to ~11KB/sec which is 3000x slower than the implied input rate of 33 MB/sec...not 3x. Replace all 3x with 3000x in the previous post...get a reeeeeally big memory buffer KJArticle: 133816
CONGRATULATIONS! You have won today's "Least well specified question" prize. ;-)Article: 133817
hai , can anyone suggest how to test and verify unified protocol layers? regards, rajArticle: 133818
On 16 juuli, 13:42, Etantonio <etanto...@gmail.com> wrote: > I'm in trouble, > do you think that could be possible to program the FPGA from ethernet > for this board ? > Thanks, > > Antoniowww.etantonio.it only if you have JTAT programmer with internet connection AnttiArticle: 133819
Hi Muzaffer, I more or less know what you are going through, having spent time debugging the VHDL version of the FMF DDR2 models (on a side note, I posted my particular situation in their forums, but no one there seems interested in discussing it). Overall, the models are great, but I've just found a few minor problems here and there. One such problem, maybe similar to yours, was that the PLL used to generate the memclk did not provide a duty cycle of exactly 50%. Because of this, there were some clock signals with inertial delays in the FMF model that never fully propagated; consequently I had clock signals that did not oscillate. The fix required adding the keyword 'transport' to the statement, and disco (AFAIK, this did not disturb any other functionality). Anyway, I have had success using MIG V5 DDR2 controllers with the FMF DDR2 VHDL models, but like Gabor said, since you're in a verilog environment and micron offers verilog simulation models of their components, I'd use them.Article: 133820
the service pack fixes it. >Hi, >I'm having the same exact problem with ISE 7.1 and the Spartan 3e starter >kit. anyone have any ideas? > >Malik > >>i have got a problem while i am generating bit file using xilinx ise >>7.1i for spartan 3E device i am getting warining as >> >> warning: Bitgen:26 - bitgen only supports DRC on this device. >>Error: bitgen failed >>Reason: >>Process "Generate Programming File" did not complete. >> >>i am using xilinx webpack what the cause of the problem for this >>warning as a result i am unable to generate the bit file which is used >>for downloading to the kit. >> >>what kind of possible mistakes may result this kind of errors. or else >>i need to update the software IP downloads .......... >> >>give me some sort of suggestion................... if at all to update >>bitgen how can i proceed since i am beginner i need some guidence >> >> >>thanks and regards, >>srik >> >> > > > > >Article: 133821
On Jul 16, 9:39=A0am, raj <rajesh.o...@gmail.com> wrote: > can anyone suggest how to test and verify unified protocol layers? > Yes...anyone can suggest anything. Perhaps if you ask a more specific question instead of an open ended one you'll get better responses. KJArticle: 133822
On Jul 16, 6:42=A0am, Etantonio <etanto...@gmail.com> wrote: > I'm in trouble, > do you think that could be possible to program the FPGA from ethernet > for this board ? > Thanks, > > Antoniowww.etantonio.it Antonio; According to the Xilinx web site (http://www.xilinx.com/publications/ prod_mktg/pn2029.pdf), the Spartan-3AN board comes with a USB programming cable. Or you can use the Digilent programming cable, as Austin suggested. -Dave PollumArticle: 133823
On Jul 16, 8:58=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Jul 16, 8:52=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > > On Jul 16, 5:39=A0am, Zhane <m...@hotmail.com> wrote: > > Woops, failed basic mathematics myself on the previous post. =A0115200 > baud will translate to ~11KB/sec which is 3000x slower than the > implied input rate of 33 MB/sec...not 3x. =A0Replace all 3x with 3000x > in the previous post...get a reeeeeally big memory buffer > > KJ :( im trying to sample the LPC bus though... I've already reduced to the minimal that I think I need...and with what I have now, there are weird extra cycles appearing at places where they shuoldnt be. Without these samples, I cant determine if those weird cycles are relevant or not. >.< :( how? my Spartan 3E has a USB interface, but... it's used to program my board. Can I remove my usb cable after downloading my program, and use it to transfer instead? what kind of program (eg.hyperterminal for rs232) is required for usb?Article: 133824
On Jul 16, 10:39=A0pm, Zhane <m...@hotmail.com> wrote: > On Jul 16, 8:58=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > > > On Jul 16, 8:52=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > > > > On Jul 16, 5:39=A0am, Zhane <m...@hotmail.com> wrote: > > > Woops, failed basic mathematics myself on the previous post. =A0115200 > > baud will translate to ~11KB/sec which is 3000x slower than the > > implied input rate of 33 MB/sec...not 3x. =A0Replace all 3x with 3000x > > in the previous post...get a reeeeeally big memory buffer > > > KJ > > :( > im trying to sample the LPC bus though... I've already reduced to the > minimal that I think I need...and with what I have now, there are > weird extra cycles appearing at places where they shuoldnt be. Without > these samples, I cant determine if those weird cycles are relevant or > not. > > >.< > > :( how? my Spartan 3E has a USB interface, but... it's used to program > my board. > > Can I remove my usb cable after downloading my program, and use it to > transfer instead? > what kind of program (eg.hyperterminal for rs232) is required for usb? hmmm I guess I can give up on usb.. I cant find a VHDL usb core to use anyway ~_~
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z