Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 93375

Article: 93375
Subject: Re: More beginner's verilog questions
From: "Reza Naima" <google@reza.net>
Date: 20 Dec 2005 19:26:52 -0800
Links: << >>  << T >>  << A >>
With regards to the clock - the design has a counter, but all the
counter does is count the number of pulses that come in.  I can't see
how a seperate clock would be required for a counter.

Also, are there some sort of standars for using a clock?  Can you flag
an input as being a clock such that the synthesizer would do something
special/different with it?  Or is it just a input that you deal with in
your own way?

Thnx,
Reza


Article: 93376
Subject: Re: More beginner's verilog questions
From: "Rob" <robnstef@frontiernet.net>
Date: Wed, 21 Dec 2005 03:38:47 GMT
Links: << >>  << T >>  << A >>
I have used the following book and it has been very helpful.

Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL
by Michael D. Ciletti

"Reza Naima" <google@reza.net> wrote in message 
news:1135064071.868137.197590@z14g2000cwz.googlegroups.com...
>I bought a book a book recommended by one of the application engineers
> at a reseller of Xilinx  (Verilog HDL), and it described verilog very
> well.  But it didn't distinguish between what was used for simulation
> and what is synthesizeable.  So my first bit of code (if you look at
> the link) worked fine on the simulator, but it relied heavily on
> constructs that could not be synthesized.  I then asked for
> recommendations on books, and was told that there were no good ones.
> Hence I'm hoping I can get some pointers to reference code, or some
> help debugging the code I wrote.
>
> Thnx,
> Reza
> 



Article: 93377
Subject: Re: Virtex II Pro XC2VP100
From: "rmanand" <murugs_india@yahoo.com>
Date: Tue, 20 Dec 2005 23:17:58 -0600
Links: << >>  << T >>  << A >>
rmanand wrote:
 Hi

 Thanks for your reply.
 
 >Do you have a pullup resistor on the TDI/TDO chain between the FPGAs?
It
>is needed, apparently only on the V2Pro devices (I use 150ohms).

Yeah i am suing 220 ohm  resistor.Xilinx reccomends  >200 ohm.so i  did
not  go below  200 ohm.





>> ...
>>>> 
>>>> Hi friends
>>>> 
>>>> The Virtex II pro (XC2VP100) device is not Configuring through
>>>> Impact7.1e
>>>> 
>>>> When i try to check with CRO what is happeing at the BOUNDARY 
>>>> SCAN SIGNALS TDO ,TDI,TCK ,TMS
>>>> 
>>>> I found TDI,TMS,TDI signals are okay .THE TDO is always stuck at
>>>>  one(pulled up by 220 ohm resisitor preferred by xilinix).
>>>> 
>>>> The prog Pin is pulled up to 3.3V through 4.7k.The Init pin is 
>>>> pulled up to 3.3v through 4.7k.These all are xilinx
>>>> reccomendation.
>>>> 
>>>> I could not understand what will be reason for the TDO is always 
>>>> high at one and how to solve the problem.
>>>> 
>>>> 
>>>> The impact is always throughing Impact -583 error. Expeting your 
>>>> valuabe replies
>



Article: 93378
Subject: Re: Virtex II Pro XC2VP100
From: "rmanand" <murugs_india@yahoo.com>
Date: Tue, 20 Dec 2005 23:27:17 -0600
Links: << >>  << T >>  << A >>
>rmanand wrote:
Hi 
Thanks for your reply

I checked the  both  device .TDO  of the  fist pin  low without  Pull up
with  pull up it  is  high.It is not  toggeled.

The second  FPGA is also  same 

I have read  somewhere, If TDO is  high , FPGAS are   in Reset state.What
Can be cause for the Reset.

I have checked the powersupply connections,The connection is  okay Upto
the  last  PTH  nearer to the pad .

I have  put the  Devices in  Master slave mode.The CCK is  coming out.So
device is okay.

We have two  board.One  board is   working fine  after adding  TDo  pull
up 220 ohm resistor.One board is the problem.


Please  give your Valuable suggestion 

Thanks and Regards
Muruganand.

>>you are out of luck sitting on mal functioning board and/or FPGA

what you describe is 'broken' JTAG chain, this is the point where
you can not do any further testing until you get something non stuck 1
out of the TDO. unless that works the JTAG testing can not be done.

the m2m1m0 do not matter.
virtually nothing matters, as long as the JTAG pins are connected
to correct pads and FPGA is powered up correctly, then you
should see something.

just use impact debug mode, set 1111 to IR scan and click scan IR
until you then at least one 0 in the response you are out of luck.

check schematics, PCB power etc..
do it again
do it again
until you get the jtag scan working

if you have 2 devices in the chain you can not check the
JTAG unless both of them work so check TDO of the
first device first if that toggles and the TDO of the second
device not then error is with first.

but you can not detect 1 out of 2, it will be either
2 or nothing, in your case nothing

Antti




>>>> 
>>>> Hi friends
>>>> 
>>>> The Virtex II pro (XC2VP100) device is not Configuring through
>>>> Impact7.1e
>>>> 
>>>> When i try to check with CRO what is happeing at the BOUNDARY 
>>>> SCAN SIGNALS TDO ,TDI,TCK ,TMS
>>>> 
>>>> I found TDI,TMS,TDI signals are okay .THE TDO is always stuck at
>>>>  one(pulled up by 220 ohm resisitor preferred by xilinix).
>>>> 
>>>> The prog Pin is pulled up to 3.3V through 4.7k.The Init pin is 
>>>> pulled up to 3.3v through 4.7k.These all are xilinx
>>>> reccomendation.
>>>> 
>>>> I could not understand what will be reason for the TDO is always 
>>>> high at one and how to solve the problem.
>>>> 
>>>> 
>>>> The impact is always throughing Impact -583 error. Expeting your 
>>>> valuabe replies
>



Article: 93379
Subject: Re: More beginner's verilog questions
From: "santosh" <santosh.akadam@patni.com>
Date: 20 Dec 2005 22:53:30 -0800
Links: << >>  << T >>  << A >>
Reza,
Well,What is it that you have thought of the RTL of the counter you
would like to code?


Article: 93380
Subject: Re: Place and Route Algorithms
From: Stephane <stephane@nospam.fr>
Date: Wed, 21 Dec 2005 10:20:17 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> Marco, I am sure that you will not find anything beyond very basic
> tutorial information.

Maybe it's just better not to know: [remark for all users:] did you 
never realize that sometimes setting some options has the opposite 
action that their name suggest?

I always told myself: the proof that the tool vendors are not 
comfortable with the complexity of their software is named Xplorer...

I don't blame, I'm no troll! I acknowledge the great job your teams do.
But intrisic knowledge of the tools should allow confirmed users to set 
correctly the right options with predictable behavior.


> Unless you
> are a genius and addressthe problem in a very unconventioanl way.

In that case, create your company and get acquired by one of those 
"biggest" or submit a CV ;-)


> Peter Alfke
> 

Article: 93381
Subject: exception (0xe06d7363) when creating a MicroBlaze from the ISE environment
From: "Raymond" <raybakk@yahoo.no>
Date: 21 Dec 2005 02:32:49 -0800
Links: << >>  << T >>  << A >>
When I create an embedded processor from the ISE environment an
exeption popps up whenever I close the XPS.

The exeption is as follows: <<The exception unknown software exception
(0xe06d7363) occurred in the application at location 0x7c81eb33.>>

in Answer Record # 21954 and Answer Record: 21737 Xilinx claims that
<<This Coregen / Project Navigator integration problem has been fixed
in ISE 7.1i IP Update 3>> and <<This problem has been fixed in ISE 7.1i
Coregen IP Update 3. >>

I use ISE version 7.1.04i and XPS version 7.1.02i

I have some question I hope some of you can help me out with.

1.) Is the corgen updated with the same SP as the ISE?

2.) Does the XPS use corgen cores? If so, are the corgen cores for XPS
updated in the same SP as XPS?

What I ment in question 2 is something like this: If I have XPS version
7.1.02i, does it use corgen cores created by the version 7.1.02i
regardless if I have ISE version 7.1.04i?

3.) What can I do to prevent this exeption?


Raymond


Article: 93382
Subject: HOW IS GREY BOX VERIFICATION DONE
From: "AAA" <abrar_ahmed_313@yahoo.co.in>
Date: 21 Dec 2005 02:36:41 -0800
Links: << >>  << T >>  << A >>
hiii friends...

can any one tell me or explain to how is grey box verification done???
black box and white box is clear but how do we carry on with grey box,
what knowledge is known. can we do the same in only in testbench. we
check the output response the way done in black box, but as per
definition grey box has little knowledge about the design
implementation.

Thanks

Cheers.  

Abbs


Article: 93383
Subject: Re: Incremental Compilation in Quartus 5.1?
From: "Banetele news" <none@none.none>
Date: Wed, 21 Dec 2005 12:28:02 +0100
Links: << >>  << T >>  << A >>
I have tried this with Quartus 5.0.

This gives you an improvement in compilation time, but the performance 
(speed) is lower than when running a full compilation.

I want to use the slowest speed grade, and when my design increased I had to 
switch to full compilation to meet my timing constraints.



/Vidar


<jjlindula@hotmail.com> wrote in message 
news:1134591940.003822.295690@o13g2000cwo.googlegroups.com...
> Hi, I was wondering if anyone could comment on using Incremental
> Compilation in Quartus 5.1? Is there any problems partitioning your
> design? I just want to know if it is worth using it?
>
> Thanks,
> joe
> 



Article: 93384
Subject: Re: More beginner's verilog questions
From: "Reza Naima" <google@reza.net>
Date: 21 Dec 2005 04:06:29 -0800
Links: << >>  << T >>  << A >>
Santosh -

I'm not sure if I understand your question, or what an RTL stands for.
Based on the feedback, I rewrote the module so it looks like this (and
is much simpler looking) :

module counterLatch32(counter_increment, in, reset, enable, out);
    input in;
    input counter_increment;
    input reset;
    input enable;
    output [31:0] out;

    reg [4:0] index;
    reg [31:0] out;

	always @(posedge counter_increment or posedge reset) begin
		if (!reset)
			index <= index + 1;
		else
			index <= 5'b00000;
	end

	always @(posedge enable)
		out[index] <= in;

endmodule

I still don't see a need for a clock - can someone shed some light into
a case where a clock would be helpful?  I'm still getting errors.  Just
this one so far....

ERROR:Xst:898 - counterlatch32.v line 12: The reset or set test
condition for <index> is incompatible with the event declaration in the
sensitivity list.


reza


Article: 93385
Subject: Is there anyboay work on the subject with the embeded system in the fpga?
From: "bjzhangwn" <bjzhangwn@163.com>
Date: 21 Dec 2005 04:11:10 -0800
Links: << >>  << T >>  << A >>
       Now I want to implement a arm core in the xilinx v4 or v2,but I
can't get the soft ip core,anybody konw how to get the free soft
ipcore,thanks!
       Also If I choose the hardcore from alter or xilinx,which is
better?And what I need list below:an embeded hardcore(with some
peripheral devices) and pci-express interface .with the price and
performence,which is better?and the cpu core I need do'nt need high
speed.


Article: 93386
Subject: Re: Is there anyboay work on the subject with the embeded system in the fpga?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 21 Dec 2005 13:27:35 +0100
Links: << >>  << T >>  << A >>
"bjzhangwn" <bjzhangwn@163.com> schrieb im Newsbeitrag 
news:1135167070.411523.119360@g47g2000cwa.googlegroups.com...
>       Now I want to implement a arm core in the xilinx v4 or v2,but I
> can't get the soft ip core,anybody konw how to get the free soft
> ipcore,thanks!
>       Also If I choose the hardcore from alter or xilinx,which is
> better?And what I need list below:an embeded hardcore(with some
> peripheral devices) and pci-express interface .with the price and
> performence,which is better?and the cpu core I need do'nt need high
> speed.
>

google: nnARM

and you get the free opensource ARM softcore

but its pretty rotten, it does synthesize but is huge
http://xilant.com/content/view/21/55/
there is a little info about our testing of it

short: hardly useable

the only FPGA with hardcore processor and PCIe capabilities is the xilinx 
Virtex4FX, Altera PCIe ready devices do not have hardcore processors

Antti



Article: 93387
Subject: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
From: wtxwtx@gmail.com
Date: 21 Dec 2005 04:28:46 -0800
Links: << >>  << T >>  << A >>
Hi John,
After I read your paper in Xilinx Tip Design, I searched the USPTO with
your name and found no result. It really surprised me.

Your result was worth filing a patent absolutely!

Try to get your company boss's support and you have the right to
invalidate the Lucent patent with rock solid prove.

Good luck.

Weng


Article: 93388
Subject: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
From: wtxwtx@gmail.com
Date: 21 Dec 2005 05:03:10 -0800
Links: << >>  << T >>  << A >>
Hi John,
Jiang's provisional patent was filed on Mar. 27, 2000, more than 4
years earlier than the patent approval date: July 6, 2004.

What is the published date of your paper?

That is the most important factor deciding who is the first person to
get the circuit. It is not only a circuit, but a fundamental method
covering all similar circuits.

Weng


Article: 93389
Subject: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
From: wtxwtx@gmail.com
Date: 21 Dec 2005 05:13:54 -0800
Links: << >>  << T >>  << A >>
Hi Richard,
I am asking a question:
"If you can demonstrate that your circuit was published or sold more
than 1 year before the priority date of Lucent's patent application,
then it would be difficult for Lucent to prevail in court. "

Why one year before the priority date of Lucent's patent application?

In this case, John published his paper 5 years ago, Jiang's priority
date is January 16, 2001. It seems that the patent was filed to be
within one year of John's paper. Doesn't it mean their paper and patent
application has no relationship? Could you please give more
explanation?

Weng


Article: 93390
Subject: Re: Mean value filter
From: "Gabor" <gabor@alacron.com>
Date: 21 Dec 2005 06:06:26 -0800
Links: << >>  << T >>  << A >>
Here's an article I've used to generate efficient 3 x 3 median filters:

http://www.cg.tuwien.ac.at/research/publications/1994/Kopp-1994-EMF/TR-186-2-94-18Paper.pdf

(Manfred Kopp and Werner Purgathofer, Technical University of Vienna,
1994)

wtxwtx@gmail.com wrote:
> Hi John,
> Thank you for your response.
>
> Yes, I did get something new about median filter. I am making living as
> a senior principle FPGA designer in a small company to do memory
> controller system and independently have designed several market
> successful products for my company.
>
> My hobby at home is to attack complex algorithms in computer science
> and electronics that either is currently implemented by software or the
> current algorithms in circuits that can be further improved, updated to
> cover more ranges, or get faster speed with less resources.
>
> I have a math background. In math, as you know, there are always many
> theorems that expand some previous narrower theorem. I am trying to do
> the same things for electronic circuits. One of targets is your paper.
> In the paper you really did an excellent job and I learned from the
> technique you have used. After reading your paper on June 13, 2005, I
> realized that I could and should do better than your paper in a
> different circuit. I finished it 2 weeks ago.
>
> I have read several papers after reading your paper and learn there is
> a Rank K filter that is similar to median filter and is the Kth largest
> data to replace the center data. Further more, there is a Stack filter
> further pushing the median filter method far from normal.
>
> In my opinion, developing a new algorithm for electronic algorithm
> doesn't need more background knowledge than printing and reading
> several papers describing existing best algorithms about the subjects
> you are interested. The reason is I will never use it and if I can
> develop an algorithm or a circuit, or a method, they can be used by
> others. If there is a chance, file a patent. If not, just publish it
> for fun.
>
> Due to being not in image industry circle, what I have about median
> filter is what I just read from your paper and other several papers. I
> will certainly read Khaled Benkrid's paper.
>
> I have been writing some patents now, but not for median filter. What I
> have done with median filter is certainly a material for patent. I will
> leave the decision whether or not to file a patent 1 year later.
> Because I am now occupied by other urgent projects at home.
>
> I appreciate your several responses very much. For example, you gave me
> 3 examples on how to handle edge pixels that are to be included in my
> algorithm without much logic.
>
> Your paper excellence is in the following points:
> 1. Paper is very concise;
> 2. Key circuit element is shown very clear;
> 3. Algorithm is very cleaver.
>
> Thank you.
>
> Weng
>
> If you like, send me email to wtxwtx at gmail dot com by deleting space
> char.


Article: 93391
Subject: Re: Is there anyboay work on the subject with the embeded system in the fpga?
From: "bjzhangwn" <bjzhangwn@163.com>
Date: 21 Dec 2005 06:10:08 -0800
Links: << >>  << T >>  << A >>
Thanks,How can I get the latest version?The sourse file avalable is
2001 version!


Article: 93392
Subject: FPGA DDR controller - CKE signal... do I need a pull down?
From: "I. Ulises Hernandez" <delete@e-vhdl.com>
Date: Wed, 21 Dec 2005 14:13:31 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi guys,

I've written a DDR controller, runs on a virtex2 and interfaces a sodimm 
256MB.

I've got a problem initialisating a DDR, it works 10 out of 11 times (random 
tbh, but fails once in a blue moon). I am not sure what it could be as I am 
doing all that the JEDEC specs during the initialization process... with the 
EXCEPTION of holding CKE low during power-up. I can NOT control the value of 
that signal during power-up because the FPGA has not been programmed yet 
(it's programmed from Flash). And there is not external pull-down.

The JEDEC standard for DDR specs that:

"Except for CKE, inputs are not recognized as valid
until after VREF is applied. CKE is anSSTL_2 input,
but will detect an LVCMOS LOW level after VDD is
applied. Maintaining an LVCMOS LOW level on
CKE during power--up is required to guarantee that
the DQ andDQS outputs will be in the High--Z state,
where they will remain until driven in normal operation
(by a read access). After all power supply and
reference voltages are stable, and the clock is
stable, the DDR SDRAM requires a 200 µs delay
prior to applying an executable command."

They recommend that:

"Operation or timing that is not specified is illegal and after such an 
event, in order to guarantee
proper operation, the DRAM must be powered down and then restarted through 
the specified
initialization sequence before normal operation can continue."

So... when the FPGA is not programmed the DDR control signals are floating, 
they could mimic a DDR access and put the DDR into an odd state, is that 
correct? If so, what do they mean by "DRAM must be powered down and then 
restarted...", do they mean a CKE high to low transition which in theory 
puts the DDR into power down mode...?

Any help would be appreciatted, thanks in advance,

-- 
Ignacio Ulilses Hernandez
" I'm not normally a praying man, but if you're up there, please save me, 
Superman!" - Homer Simpson ;O)




Article: 93393
Subject: Re: Is there anyboay work on the subject with the embeded system in the fpga?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 21 Dec 2005 15:17:52 +0100
Links: << >>  << T >>  << A >>
"bjzhangwn" <bjzhangwn@163.com> schrieb im Newsbeitrag 
news:1135174208.617093.15130@g14g2000cwa.googlegroups.com...
> Thanks,How can I get the latest version?The sourse file avalable is
> 2001 version!
>
there is nothing more recent, ARM lawer did go hunt for those chinese 
students, so that is the last snapshot available

Antti 



Article: 93394
Subject: Re: Is there anyboay work on the subject with the embeded system in the fpga?
From: "bjzhangwn" <bjzhangwn@163.com>
Date: 21 Dec 2005 06:36:15 -0800
Links: << >>  << T >>  << A >>
I see,can you give me any other information about the nnarm project?


Article: 93395
Subject: Re: More beginner's verilog questions
From: Jason Rosinski <Jason.DOT.Rosinski@zarlink.com>
Date: Wed, 21 Dec 2005 09:39:08 -0500
Links: << >>  << T >>  << A >>
   Hmm, right now I don't see what it's complaining about, since the asynchronous reset is active 
high.  My suggestion would be to rearrange the blocks a little.  Try something like:

  	always @(posedge counter_increment or posedge reset) begin
  		if (reset)
  			index <= 5'b00000;
  		else
  			index <= index + 1;
  	end


	Am I missing something obviously wrong with the sensitivity list here?  Or is it just a problem 
with the synthesiser?


Reza Naima wrote:
> Santosh -
> 
> I'm not sure if I understand your question, or what an RTL stands for.
> Based on the feedback, I rewrote the module so it looks like this (and
> is much simpler looking) :
> 
> module counterLatch32(counter_increment, in, reset, enable, out);
>     input in;
>     input counter_increment;
>     input reset;
>     input enable;
>     output [31:0] out;
> 
>     reg [4:0] index;
>     reg [31:0] out;
> 
> 	always @(posedge counter_increment or posedge reset) begin
> 		if (!reset)
> 			index <= index + 1;
> 		else
> 			index <= 5'b00000;
> 	end
> 
> 	always @(posedge enable)
> 		out[index] <= in;
> 
> endmodule
> 
> I still don't see a need for a clock - can someone shed some light into
> a case where a clock would be helpful?  I'm still getting errors.  Just
> this one so far....
> 
> ERROR:Xst:898 - counterlatch32.v line 12: The reset or set test
> condition for <index> is incompatible with the event declaration in the
> sensitivity list.
> 
> 
> reza
> 

Article: 93396
Subject: Re: Place and Route Algorithms
From: Kolja Sulimma <news@sulimma.de>
Date: Wed, 21 Dec 2005 15:39:15 +0100
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:
> Marco, I am sure that you will not find anything beyond very basic
> tutorial information.
> These are the "crown jewels" of any FPGA company, and these jewels are
> well guarded, but also polished daily. The quality of these tools
> determines the success of our companies, and each of us wants to be at
> leats a step ahead of the other company.
> BTW, the continuous investment by companies like Xilinx and Altera (to
> name just the two biggest) is enormous, and it is unlikely that an
> individual engineer can provide significant improvements. Unless you
> are a genius and addressthe problem in a very unconventioanl way.

I totally disagree.

There is a difference between an algorithm and an implementation with
tweaked parameters for a given architecture.
Im am doing EDA-algortihm research for quite some time, and most
substantial progress has been made by individuals or very small teams.

These people do not provide industrial grade implementations that can do
a better job on any given FPGA than the vendor tools, but provide enough
evidence that a certain approach might be better suited.

I hear pathfinder variants are used a lot for fpga routing. Two authors
only.
http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/fpga/1995/2550/00/2550toc.xml&DOI=10.1109/FPGA.1995.15

And without flowmap Xilinx probably would build MUX-based FPGAs now.

You and can be greatful that Leiserson and Saxe did not patent retiming
and sell it to altera.
http://www.springerlink.com/(equ2gbjfwu2v44ebrbkulu55)/app/home/contribution.asp?referrer=parent&backto=issue,2,47;journal,56,61;linkingpublicationresults,1:400117,1
Otherwise ISE would have to be an web based application with servers
running in europe.

Xilinx used placement based on simulated annealing in the past.
(UC Berkeley, Carl Sechen, Sangiovanni-Vincentelly, et. al.)
What is it now? Quadratic placement imported from Munich?


The OP should turn to University of Toronto were a lot of FPGA placement
and routing research has been done. Also, scholar.google.com tells me
that André DeHon at CalTech has published in the area of hardware
accelerated placement and routing recently (2003)

Kolja Sulimma




Article: 93397
Subject: Re: Is there anyboay work on the subject with the embeded system in the fpga?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 21 Dec 2005 15:42:33 +0100
Links: << >>  << T >>  << A >>

"bjzhangwn" <bjzhangwn@163.com> schrieb im Newsbeitrag 
news:1135175775.220011.275330@o13g2000cwo.googlegroups.com...
>I see,can you give me any other information about the nnarm project?
>
no.
nothing more that I already told or what you can find yourself buy googling.

for fun I checked the design for synthesis pass, thats it.

Antti 



Article: 93398
Subject: Can anyone have the evaluation board from xilinx and altera?
From: "bjzhangwn" <bjzhangwn@163.com>
Date: 21 Dec 2005 07:22:30 -0800
Links: << >>  << T >>  << A >>
I am interest in the embeded system in the fpga,but I have no money to
buy the board from xilinx or altera,Anyone who have it can share your
schematic and the docs?thanks!


Article: 93399
Subject: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
From: Kolja Sulimma <news@sulimma.de>
Date: Wed, 21 Dec 2005 16:50:17 +0100
Links: << >>  << T >>  << A >>
JustJohn schrieb:

> Corrolary question...Do most patents just make money for lawyers and
> add to the writer's resumes? Or do a majority have actual worth beyond
> that?

IBM estimates that patents do them 10x as much harm as they earn from
their patent portfolio.

This means that the main use for patents is to defend yourself against
patent trolls.

Kolja Sulimma



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search