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Messages from 96950

Article: 96950
Subject: Dual Port Block RAM Inference
From: "Yaseen Zaidi" <yaseenzaidi@NETZERO.com>
Date: 13 Feb 2006 22:45:38 -0800
Links: << >>  << T >>  << A >>
I infer a Dual Port Block RAM with port A as R/W and port B as R only
with dual clock, dual address, dual EN and dual DOB connected to B.
However, ISE reports mode READ FIRST and dual mode WRITE FIRST which is
contradicting since dual port B shall never be written.

Any thoughts?

YZ


Article: 96951
Subject: Re: microblaze with FSL
From: "siva.velusamy@gmail.com" <siva.velusamy@gmail.com>
Date: 13 Feb 2006 22:59:24 -0800
Links: << >>  << T >>  << A >>
microblaze_nbwrite_datafsl = non blocking write
microblaze_bwrite_datafsl = blocking write

On a non-blocking write the processor sets the control bit if the fsl
bus is full. On a blocking write the processor waits until the FSL bus
has space. More details can be obtained from the documentation (look
for the put instruction and its variants).

/Siva
Xilinx, Inc.


Article: 96952
Subject: Re: Newb question about Xilinx Impact and parallel cable III ....
From: ":-)" <a@b.c>
Date: Tue, 14 Feb 2006 01:59:48 -0500
Links: << >>  << T >>  << A >>

Ok now I'm  the point where I can have IDcode correctly

I have 1 xc9572_pc84  if I add config file xc9572_pc84.bsd   I got the 
IDCode correct.

Now (if I understand) I need to specified the jedec file  (add new 
configuration file)  so when I add my ex.jed file and try to program I 
still good same old  bad Idcode  and program failed...

:-/


>>
>>I install new ISE (withh Impact) package from xilinx.
>>Did a simple thing in it and now I,m trying to program my
>>xc9572.
>>
>>I got a parallel cable 3 clone form a company,
>>the cable is autodetected correctly.
>>
>>Now when I tried to get Idcode from my xc9572 it allways fails ....  :o(

Article: 96953
Subject: Re: Newb question about Xilinx Impact and parallel cable III ....
From: ":-)" <a@b.c>
Date: Tue, 14 Feb 2006 02:18:30 -0500
Links: << >>  << T >>  << A >>
  Ok now I'm  the point where I can have IDcode correctly

  I have 1 xc9572_pc84  if I add config file xc9572_pc84.bsd   I got the
  IDCode correct.

  Now (if I understand) I need to specified the jedec file  (add new
  configuration file)  so when I add my ex.jed file and try to program I
  still good same old  bad Idcode  and program failed...

  :-/


INFO:iMPACT:501 - '1': Added Device xc9572 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
Command: Program -p 0 -e -defaultVersion 0
// *** BATCH CMD : Program -p 1 -e -defaultVersion 0
PROGRESS_START - Starting Operation.
ERROR:iMPACT:583 - '1': The idcode read from the device does not match 
the idcode in the bsdl File.
INFO:iMPACT:1578 - '1':  Device IDCODE : 
00101001010100000100000010010011
INFO:iMPACT:1579 - '1': Expected IDCODE:    00001001010100000100000010010011
'1': Check to make sure if version '0010' is supported.
PROGRESS_END - End Operation.
Elapsed time =      3 sec.




>>> I install new ISE (withh Impact) package from xilinx.
>>> Did a simple thing in it and now I,m trying to program my
>>> xc9572.
>>>
>>> I got a parallel cable 3 clone form a company,
>>> the cable is autodetected correctly.
>>>
>>> Now when I tried to get Idcode from my xc9572 it allways fails ....  :o(

Article: 96954
Subject: Re: Entity with Multiple Architectures
From: backhus <nix@nirgends.xyz>
Date: Tue, 14 Feb 2006 08:45:38 +0100
Links: << >>  << T >>  << A >>
Sudhir.Singh@email.com schrieb:
> Hi All,
> I was wondering if anyone has declared an entity with multiple
> architectures using Xilinx ISE. How is this done, whether both
> architectures are defined in the same file where the entity is
> declared. 
> Thanks in advance
> Sudhir
> 
Hi Sudhir,
what you describe only makes sense for simulation, where you can put in 
a configuration file, telling the simulator which architecture to use.

In synthesis only one architecture per entity is allowed.
You should split your entity and architectures in separate files if 
still possible.

Another posibility (while not a very clean thing) is to wrap the unused 
architecture(s) in pragmas:

entity myentity is
-- some ports etc.
end entity;

-- synthesis off

architecture unused of myentity is
  --some crap
end architecture unused;

-- synthesis on

architecture which_i_want of myentity is
  --The real one
end architecture which_i_want;

The bad thing is that you always have to edit your sources when trying a 
different architecture. With separated files you can have separate 
projects or scripts that use one architecture or the other and have 
independant reproducable results. So, better spend some time for that 
than messing around with your sources. Also your CVS (or whatever you 
use) will be happier.

have a nice synthesis
   Eilert





Article: 96955
Subject: Re: Newb question about Xilinx Impact and parallel cable III ....
From: ":-)" <a@b.c>
Date: Tue, 14 Feb 2006 02:49:15 -0500
Links: << >>  << T >>  << A >>

Ohlala !!!

I made a mistake as it seems !
I download  BSDL model from xilinx web site for xc9500
And used them, some of them don't have the good idcode at it seems ...
So that was all that problem ,  I roll back to BSDL from the 
installation  and all is fine :-)
I can program my xc9572 :o)



:-) wrote:

>  Ok now I'm  the point where I can have IDcode correctly
> 
>  I have 1 xc9572_pc84  if I add config file xc9572_pc84.bsd   I got the
>  IDCode correct.
> 
>  Now (if I understand) I need to specified the jedec file  (add new
>  configuration file)  so when I add my ex.jed file and try to program I
>  still good same old  bad Idcode  and program failed...
> 
>  :-/
> 
> 
> INFO:iMPACT:501 - '1': Added Device xc9572 successfully.
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> ----------------------------------------------------------------------
> Command: Program -p 0 -e -defaultVersion 0
> // *** BATCH CMD : Program -p 1 -e -defaultVersion 0
> PROGRESS_START - Starting Operation.
> ERROR:iMPACT:583 - '1': The idcode read from the device does not match 
> the idcode in the bsdl File.
> INFO:iMPACT:1578 - '1':  Device IDCODE : 00101001010100000100000010010011
> INFO:iMPACT:1579 - '1': Expected IDCODE:    
> 00001001010100000100000010010011
> '1': Check to make sure if version '0010' is supported.
> PROGRESS_END - End Operation.
> Elapsed time =      3 sec.
> 
> 
> 
> 
>>>> I install new ISE (withh Impact) package from xilinx.
>>>> Did a simple thing in it and now I,m trying to program my
>>>> xc9572.
>>>>
>>>> I got a parallel cable 3 clone form a company,
>>>> the cable is autodetected correctly.
>>>>
>>>> Now when I tried to get Idcode from my xc9572 it allways fails ....  
>>>> :o(

Article: 96956
Subject: Re: Altera RoHS Irony
From: David Brown <david@westcontrol.removethisbit.com>
Date: 14 Feb 2006 09:24:16 +0100
Links: << >>  << T >>  << A >>
rickman wrote:
> I'm not sure what you mean.  Lead is a heavy metal that causes many
> problems including permanent damage to the central nervous system.
> That is why lead is no longer in gasoline or paint.  The lead in
> electronics ends up in landfills which at some point will end up in our
> water and food chain.  Yes, we take great "precautions" to keep
> landfills intact and away from our water sources, but they all leak and
> some leak a lot.  Eventually they will all be sources of significant
> contamination of our environment if they contain long term polutants
> like lead.
> 
> That is it in a nutshell.  If we continue to concentrate dangerous
> polutants by putting them in products and then bury them in our back
> yards, we will never have an even remotely clean environment.
> 

It's also worth pointing out that although people use the term "lead 
free", that's only a part of RoHS and similar directives.  There are a 
number of other metals and chemicals banned or limited by RoHS which are 
more poisonous than lead, although they are lower volumes in electronics.

The theory is nice - it's a step towards being a bit more 
environmentally friendly.  The implementation is a lot more questionable 
"let's set some rules, and a deadline with plenty of time, and 'market 
forces' will find a solution".  It would have been far better to have 
graduated commercial incentives - start with grants for companies 
willing to switch over early as "prototypes" for the industry, and then 
move to gradually increasing taxes on leaded components and electronics 
until everyone has switched over.


> 
> Hul Tytus wrote:
>> Anyone familiar with the reasoning behind the lead restrictions? There
>> hasn't been any publicity excepting the compounds that are poison when
>> eaten and those that are poison in the blood stream. Are there others?
>>
>> Hul
>>
>> Al Clark <dsp@danvillesignal.com> wrote:
>>> Today I got this in Altera's email newsletter
>>> Get RoHS Compliant with Altera FPGAs, CPLDs and Structured ASICs
>>> I have never seen a single 3000 series PLD available in leadfree that you
>>> could actually purchase for delivery from stock. I have been able to buy
>>> lead versions of most of this family without too much trouble.
>>> I managed to buy a small number of leadfree Max II parts that are on
>>> allocation.
>>> I think the current delivery is something like 14 weeks (about when we are
>>> all supposed to be RoHS compliant).
>>> I guess I found this ad a bit ironic since we have all known that RoHS was
>>> coming for a long time and Altera is bragging in their ads that they have
>>> been shipping RoHS compliant devices for a long time. I guess this must not
>>> include their distributors......
>>> I hate the RoHS requirements, but like nearly everyone else, we are working
>>> to comply. It doesn't help when the manufacturers are at least a year late
>>> in the transition process.
>>> Thanks for listening to my rant.....
>>
>>
>>> --
>>> Al Clark
>>> Danville Signal Processing, Inc.
>>> --------------------------------------------------------------------
>>> Purveyors of Fine DSP Hardware and other Cool Stuff
>>> Available at http://www.danvillesignal.com
> 

Article: 96957
Subject: Re: Problem programming Altera flex 10k100 & EPC2
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 14 Feb 2006 02:48:33 -0600
Links: << >>  << T >>  << A >>
>Lastly, I have noticed that simple designs seem to download more
>reliably than larger designs. Not sure why, as the programming file
>should be of equal length either way (though there may be a lot of zero
>padding in the smaller files)

Have you tried a scope on the clock/data lines?

Is this the same byteblaster you used back when it worked?
A newer PC might be a bit faster or there might be just a bit
more crosstalk on the cable or ...


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 96958
Subject: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 14 Feb 2006 09:56:32 -0000
Links: << >>  << T >>  << A >>
"Andrew Ward" <andy.ward@hevday.com> wrote in message 
news:2laIf.146249$vH5.1206909@news.xtra.co.nz...
>
> If you could watch the operation of the circuits inside your prototyping 
> board directly on your schematics as they run in real-time, or clock by 
> clock would you find this useful?

Synplicity sell something called Identify. It shows the operation of the 
circuit in the HDL source, I believe. Uses the JTAG interface. Dunno if it's 
any good, I never make any coding errors, so I don't need it. Ahem! ;-)
http://www.synplicity.com/products/identify/
Personally, I fail to see any benefit of schematics. Once you've been using 
HDLs long enough, it's just as easy to visualise the FFs, gates etc. from 
the code as it is to look at a pictorial representation of them. You can 
also see a lot more of them on one page! Mike's point about simulation 
reviews is spot on, and in my opinion, people who are using schematics would 
be better off following this course rather than reviewing the schematic 
sheets.
I don't want to start a flame war here, this is only my personal preference, 
greatly influenced by the fact that I wasted the best part of an afternoon 
last week when I had to maintain some old viewlogic stuff. Turns out a 
square dot doesn't connect like a round one. The problem was compounded when 
the software engineer solved it. Arse.
Cheers, Syms.
p.s. One last point, it's easy to write Perl scripts to create/change HDLs. 
How you gonna do that with schematics? HDLs also have much more powerful 
reuse capabilities. Generics to control bit widths, blah, blah, blah. This 
schematics vs. HDLs must've been gone over a hundred times on CAF. I'll shut 
up. 



Article: 96959
Subject: Re: How to decode FAR register in Virtex-4?
From: Stephane <stephane@nospam.fr>
Date: Tue, 14 Feb 2006 11:07:35 +0100
Links: << >>  << T >>  << A >>
Hi Bertrand,

did you have a look at the discussion "Xilinx legal" posted here by 
Austin Leslea on 30.01.2006 ?
You won't be allowed to perform bitstream creation...

Stephane


Bertrand Rousseau wrote:
> Hi everyone,
> 
> I'm trying to understand how the frame addresses have to be decoded for
> a Virtex-4 FPGA from Xilinx. So far I could find documentation about
> the configuration for VI and VII FPGAs, but there seem to be small
> modifications between these models frame addresses and the new
> Virtex-4.
> 
> Has anyone already tried to understand frame addresses in Virtex-4?
> 
> Thanks
> 
> Bertrand
> 

Article: 96960
Subject: Block vs. Distributed RAMs
From: bhatti1127@yahoo.com
Date: 14 Feb 2006 02:40:27 -0800
Links: << >>  << T >>  << A >>
ISE always seems to infer distributed RAM for async. reads.

Is it possible to infer distributed RAM with sync read?
Is is possible to infer/instantiate block RAM with async read?

I got ISE ver 6.

Rgds


Article: 96961
Subject: ModelSim Licence problem
From: "Sonali" <pradnya.karande@gmail.com>
Date: 14 Feb 2006 03:02:31 -0800
Links: << >>  << T >>  << A >>
I am using xilinx Tool Ver 6.3.
And Modelsim 5.8.
Due to some reasons I uninstalled modelsim.
After I installed it again I faced a problem related to license .
ModelSim is installed. and  While running it asks for license.

At licensing Wizard of ModelSim,
I choose a license file which was there previously( we kept a copy of
license file before uninstalling).

but gives following error msg:
---------------------------------------------------------------
Driver/Hostid is correctly configured.

License HostID detection report:

ERROR : The hostid type -Disk Serial Number- was referenced in the
license file
but does not match the value found on this machine.
  -the license file value for Disk Serial Number is:  e0ee2059
  -the actual value for Disk Serial Number is:  200e5645
---------------- and -----------------
XE Starter simulator license (xe-starter)
The hostid of the license does not match the hostid for this machine.
One of the following is likely:
   -The license is intended for another machine.
   -A dongle is not plugged into this machine.
   -The dongle driver is not installed or is not functioning properly.
   -The hostid mechanism has been changed or removed from this machine.
---------------------------------------------------------------

So I go for submit license request where they ask for Disk serial no.
There is a warning that one mistake in serial no. cost u $395 for
re-licensing.
I didn't know what is disk serial no. for Full VHDL.

I also have a latest copy of ModelSim where also i have to go for
licensing Wizard.

What is the way to come out from this?

"Is there any other Simulation tool which is free downloadable and
compatible with Xilinx 6.3 Tool ?"

Regards,
Sonali


Article: 96962
Subject: Re: Block vs. Distributed RAMs
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 14 Feb 2006 03:07:44 -0800
Links: << >>  << T >>  << A >>
Yes, just register the output ... (works for me). And if it's small, it
will use a distributed
No, brams are synchronous ... (input registred. On virtex4, you can
also register outputs)


Article: 96963
Subject: Re: How to decode FAR register in Virtex-4?
From: "Bertrand Rousseau" <bertrand.rousseau@gmail.com>
Date: 14 Feb 2006 03:08:06 -0800
Links: << >>  << T >>  << A >>
Hi,

Actually my work is not about bitstream generation, but bitstream
manipulation. I'd like to be able to do some readback operation on my
design and replace some parts with another design (partial
reconfiguration). Bitstreams  will still be generated by xilinx tools
and stored in memory, so I'm not generating bitstreams.

But I need to be able to address frames in the device in order to make
my design possible. Frame addressing for virtex-4 is - as far as I know
- undocumented (altough frame addressing for V-II devices is quite well
documented), that's why I was wondering if anyone had a clue about this
subject.

But thanks for the discussion, I did not see it on the list, it is sure
a good read to have.


Article: 96964
Subject: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
From: "PeteS" <ps@fleetwoodmobile.com>
Date: 14 Feb 2006 03:26:32 -0800
Links: << >>  << T >>  << A >>
richard wrote:
> I've recently noticed that the schematic software that's included with
> XILINX' ISE WebPack and with Altera's Quartus WebEdition software is
> pretty lame.  It looks as though the folks who generate, maintain, and
> repair this stuff have never had to make their living with it.
>
> I recently abandoned the last two releases of XILINX' WebPack stuff
> because there were problems making it nearly unuseable.  Release 7 was
> apparently written in VB or JAVA, hence, was so slow I couldn't use it,
> and release 8 was not only slow but "broken" in a number of ways that I
> couldn't use it either.
>
> Several bugs that I reported in 2002 still can be found, including a
> problem aligning bus taps with nets drawn on the grid that aligns with
> the symbol pins, translation/netlist errors, random breakdown in
> sequential signal-numbering (tell it to increment, and it decrements,
> and vice-versa, but not always) ... I could go on, and will in a note
> to the local sales rep ...
>
> The release 3 and 4 of Quartus wouldn't display whole text strings on
> any of our HP desktops.  That meant that, for a year, no Altera
> development could be done, except with MaxPlus-II.
>
> The current Quartus doesn't associate net names between net segments,
> i.e. if I put a right angle in a "wire," it loses its net-name
> property.   There are cases wherein a net name can't be deleted from a
> sheet, even if the net's gone, where a net name=>pin assignment won't
> work because the assignment editor doesn't allow editing of the net
> name, and busses ... well ...
>
> So, are any of you guys seeing the same sorts of problems?  Doesn't it
> make sense to have a half-hour review of a schematic rather than a
> week-long review of a ream of HDL listings?
>
> Richard

It was the utter uselessness of the schematic tools for programmable
logic (they sucked 15 years ago too) that helped push me to learn
Verilog and VHDL. I am now far more comfortable using those languages
than schematic entry for programmable designs (although I use schematic
tools for PCB designs, obviously).

I know there are some who have no choice but to maintain old schematic
based programmable designs, but for new designs I would just go to a
synthesis language.

Cheers

PeteS


Article: 96965
Subject: Re: Altera RoHS Irony
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 14 Feb 2006 04:21:50 -0800
Links: << >>  << T >>  << A >>
Good point.  I am working on a project that needs to meet the RoHS
standards and one of the parts from our existing product that we can't
use are kapton flex circuits.  I have no idea why kapton is on the list
of banned items.  Does it have to do with the way it is made?

David Brown wrote:
> It's also worth pointing out that although people use the term "lead
> free", that's only a part of RoHS and similar directives.  There are a
> number of other metals and chemicals banned or limited by RoHS which are
> more poisonous than lead, although they are lower volumes in electronics.
>
> The theory is nice - it's a step towards being a bit more
> environmentally friendly.  The implementation is a lot more questionable
> "let's set some rules, and a deadline with plenty of time, and 'market
> forces' will find a solution".  It would have been far better to have
> graduated commercial incentives - start with grants for companies
> willing to switch over early as "prototypes" for the industry, and then
> move to gradually increasing taxes on leaded components and electronics
> until everyone has switched over.

I agree that it would have been better to phase in the process, but
that would still have been painful and a LOT more work to manage.


Article: 96966
Subject: Which SelectIO for FPGA <-> FPGA buses?
From: Pete Robinson <pdr101@yahoo.co.uk>
Date: Tue, 14 Feb 2006 12:42:43 +0000
Links: << >>  << T >>  << A >>
Hi -

I'm doing a board with 17 Virtex-II's on it, which has a 32-bit bus
connected between all the devices. A master device has to be able to
read and write the 16 slaves, and (because of board limitations) I'll
probably set this up as two separate buses, with 8 slaves on each bus,
and both buses connected to the master. The bus is 50MHz, and the
timing isn't critical. The two buses will run most of the length of a
PCI card.

Any ideas on what bus interface standard I should be using, and what
termination? My first idea was LVCMOS, with parallel (RC at far end)
termination. I'm wondering if HSTL or SSTL would be better, and how
that affects the termination.

Thanks -

Pete

Article: 96967
Subject: Re: How to decode FAR register in Virtex-4?
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: 14 Feb 2006 04:44:08 -0800
Links: << >>  << T >>  << A >>
What about Table 7-5 of ug071.pdf (page 91) ?

http://direct.xilinx.com/bvdocs/userguides/ug071.pdf


Article: 96968
Subject: XPower report precision
From: the.gaffar@googlemail.com
Date: 14 Feb 2006 04:48:18 -0800
Links: << >>  << T >>  << A >>
Hi,

I am using the Xilinx Xpower tool to perform Power analysis. The
default precision in the reported power values is 1 decimal place.

This leads to a difference between the summary value produced in the
report and the value obtained by summing up the power consumption in
the logic components, given in the logic power breakdown section.

So I would like to know if there is an option which allows the user to
increase the precision of the values being displayed ?

Many Thanks


Article: 96969
Subject: Re: How to decode FAR register in Virtex-4?
From: "Bertrand Rousseau" <bertrand.rousseau@gmail.com>
Date: 14 Feb 2006 05:12:31 -0800
Links: << >>  << T >>  << A >>
Damn! You're totally right. That's incredible I just couldn't see it!

Thanks a lot, I should read more carefully.

Bertrand


Article: 96970
Subject: Re: How to decode FAR register in Virtex-4?
From: "Bertrand Rousseau" <bertrand.rousseau@gmail.com>
Date: 14 Feb 2006 05:15:45 -0800
Links: << >>  << T >>  << A >>
Actually I just checked my printed version of the UG701, and on the
version 1.2 (August 8, 2005) it is not present.

Bad luck I suppose, since I printed this version only 2 weeks ago (but
I don't remember if I took the version on my computer or the version
published on xilinx.com by this time).

Morality is: I should always check for updated version.


Article: 96971
Subject: Re: XPower report precision
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 14 Feb 2006 13:16:39 +0000
Links: << >>  << T >>  << A >>
Hi,
go to the edit menu -> preferences
and change the Current/Power units.

Aurash

the.gaffar@googlemail.com wrote:
> Hi,
> 
> I am using the Xilinx Xpower tool to perform Power analysis. The
> default precision in the reported power values is 1 decimal place.
> 
> This leads to a difference between the summary value produced in the
> report and the value obtained by summing up the power consumption in
> the logic components, given in the logic power breakdown section.
> 
> So I would like to know if there is an option which allows the user to
> increase the precision of the values being displayed ?
> 
> Many Thanks
> 

Article: 96972
Subject: Re: digital logic library by 74xxxx part number?
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Tue, 14 Feb 2006 13:50:47 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Mon, 13 Feb 2006 16:29:50 -0800) it happened Mike Treseler
<mike_treseler@comcast.net> wrote in <45cmk0F64n8sU1@individual.net>:


>Yes. Even some of the newer generation
>seem convinced that FPGAs are full of
>little counters, shifters
whots wrong with SLRs?

Article: 96973
Subject: is there a way to initialize signals to a value
From: "Matt Clement" <clement@nanotechsys.com>
Date: Tue, 14 Feb 2006 14:04:44 GMT
Links: << >>  << T >>  << A >>
Hello

Is there a way to setup a bit to be tri-stated so that it can be on a bus 
multiplexed with other signals and only becomes active low when being driven 
low by the process?  How can I setup the bit to be tri-stated or at least 
handle it such that it never goes low (and pulls the whole bus low) while 
not being driven by my CPLD??

Thanks
Matt



Article: 96974
Subject: Re: is there a way to tri-state outputs
From: "Matt Clement" <clement@nanotechsys.com>
Date: Tue, 14 Feb 2006 14:05:48 GMT
Links: << >>  << T >>  << A >>
sorry the title is not quite what i ended up asking.

matt


"Matt Clement" <clement@nanotechsys.com> wrote in message 
news:0slIf.3561$Lr.3543@trnddc01...
> Hello
>
> Is there a way to setup a bit to be tri-stated so that it can be on a bus 
> multiplexed with other signals and only becomes active low when being 
> driven low by the process?  How can I setup the bit to be tri-stated or at 
> least handle it such that it never goes low (and pulls the whole bus low) 
> while not being driven by my CPLD??
>
> Thanks
> Matt
>
> 





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