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Sorry, In this particular case, the sync enable is not present. I forgot to notice that I had edited that part as a test. In anycase, enable or no enable, the synthesizer complains that it cannot infer a flop. -sanjayArticle: 97801
ML wrote: > Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1, > M2, M3 pins floating or is it safer to tie them to VCCaux ? > > ML Don't float these. This is almost never a good idea on control signals.Article: 97802
Just a guess, but what if you make two regs rather than a reg array (memory) with two elements. It's isn't uncommon for compilers to treat arrays only as a unit and not as individual elements, even when the elements are always referenced by constant subscripts. Hope this helps, -Chris ***************************************************************************** Chris Clark Internet : compres@world.std.com Compiler Resources, Inc. Web Site : http://world.std.com/~compres 23 Bailey Rd voice : (508) 435-5016 Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours) ------------------------------------------------------------------------------Article: 97803
Brendan Illingworth wrote: > I'm looking to create a LUT based delay line for use in aligning DDR > strobes. The target device is a V2P, I have read the application notes > provided by Xilinx on this topic but can't seem to find a reference design > that illustrates this usage of LUTs. Perhaps someone could point me in the > right direction. Hmm.. I thought there was reference code. It's fairly simple - you should be able to find a LUT primitive on the libraries guide, or in unisim.vhd. If you're using synplify, you might be able to use fmaps instead, which give you things to attach tags to, while keeping the logic human-readable. You'll need appropriate incantations to avoid your synthesiser optimising it away. For your application, you'll probably also want RLOCs to lock the Luts into relative positions, and you'll probably also want to lock the origin of each macro onto the die. (Virtex-4 is way better for that kind of technique) my 2c JeremyArticle: 97804
Eric Smith wrote: > Jim Granville <no.spam@designtools.co.nz> writes: > >>That's a large array - does it really cover 2^25 combinations, >>or can you compress the inputs, so that the remainder can fit into >>Block Ram(s) ? > > > Not really. It was a design originally implemented in custom CMOS in > the early 1980s, and I don't really want to redesign it any more than > necessary. There are lots of don't cares scattered throughout the > AND matrix of the PLA, so it won't fit in any reasonable-sized ROM > or RAM. Also, the 25-bit input words don't uniquely map to outputs; > a given input word may (and often does) match multiple product terms. ... another idea : you could target a CPLD, like XC2C512, and see what that tool flow makes of it. It may give some ideas... Their PLA has a fanin of 40, a depth of 49 per 16 MC block, so it _should_ be very efficent - but it may be too big for the tools to optimize properly, in which case some middle nodes might help ? -jgArticle: 97805
Thomas Reinemann wrote: > Peter Alfke schrieb: > > Brendan, use Virtex-4 instead. There you have the IDELAY that gives you > > sub-100 picosecond granularity on the input side, and stability over > > temperature and voltage changes. It's meant for your purpose. > I'm interested in time to digital conversion, may the IDELAY used therefore? > IDELAY lets you specify an input delay (in 64 increments within a 5 ns window = 75 ps granularity), It generates, but it does not really measure the delay. Changing the delay setting is not instantaneous. I have played around with using multiple different delay driven by a common input signal, and then checking the arrival time. It gets a bit convoluted. But IDELAY is good for aligning signals with known delay offset. There is some pattern sensitivity, which means delaying the clock is more precise than delaying the data. (Sometimes you have a choice...) Peter Alfke, Xilinx ApplicationsArticle: 97806
Looks like your theory is correct Chris. Thanks. -sanjayArticle: 97807
Hi all,
I did observed a problem in the model sim. I was simulating a code
similar to the one given below.
module a (input a, output b);
wire local_variable c;
assign c = a;
tasks .....
..........
always @(*)
begin
..........
..........
end
endmodule
But the assignment c=a is not working some times. It always works if i
declare it as a reg and include it in the always block. But this will
not work if i use it part of the assign statement. the intresting part
of it is that it will not work in the first pass. At the second time
the execution enters the loops it simply executes. I can sidestep the
problem by declaring it as a reg but i want to know the reason. Did any
of you observed similar problems. Is this due to any knid of bug in the
modelsim.
regards
Sumesh V S
Article: 97808Hi Isaac, igelado@gmail.com wrote: > On the PCI base configuration provided by Xilinx I see that they use a > IPcore called misc_logic, which seems to merge all interrupts lines > (some of them are even inverted) into a single one, but I do not > understand why should I do it. Could anybody explain me the actual > reason? > > It would be great if somebody could explain me how does the whole > thing related to the interrupts from PCI devices works. At least I > would like to know which interrupt line is supposed to be asserted when > the ethernet card, the USB bridge (or whatever PCI device you prefer) > launches an interrupt, so then I can try looking into the linux kernel > code to fix the problem knowing that the interrupt line is being > asserted. As you are seeing, the approach is to merge all of the PCI interrupt lines into a single interrupt signal, which then feeds into the OPB interrupt controller (OPB_INTC). All device drivers request the same IRQ line (whichever it is on the OPB_INTC). When any PCI device raises an interrupt, it triggers the merged IRQ signal, and raises the interrupt. The kernel iterates through a linked list of drivers that are all registered on that one line. Each driver's IRQ handler queries its device, to see if it is responsible for the interrupt condition. If so then it does its thing. This process is documented in Chapter 4 of Bovet and Cesati's excellent "Understanding the Linux kernel". Doing it this way makes life a bit simpler from the kernel side, simply knowing that all PCI devices will appear on the same IRQ line makes life easier, at a modest increase in interrupt latency. Regards, JohnArticle: 97809
Jim Granville <no.spam@designtools.co.nz> writes: > ... another idea : you could target a CPLD, like XC2C512, and see what > that tool flow makes of it. It may give some ideas... > > Their PLA has a fanin of 40, a depth of 49 per 16 MC block, so it > _should_ be very efficent - but it may be too big for the tools > to optimize properly, in which case some middle nodes might help ? Interesting idea, but the rest of the design isn't going to fit in a CPLD, and splitting it across two chips is going to be even slower. I'm just trying tricks to improve performance in the FPGA. EricArticle: 97810
I was able to program my first XC9572 using a parallel jtag and ISE8.1. Of course ISE8.1 crash often but you can live with that (it does usually when u exit a tool ... ) Benjamin Todd wrote: > Whereabouts are you using the HC125 devices? Are you sure you haven't > inadvertantly inverted the signals? > A schematic or pinout would be helpful... (post it online somewhere and link > to it) > > Like Antii says, a quick solution is potentially an RC to remove the > glitches, but it would nice to know exactly what's going on. > > BTW: You should try moving away from the old foundation software... but I > guess your cable isn't supported for newer versions... In any event I use a > Parallel Cable IV with the XC9500, still using ISE7.1, will upgrade to 8 > when it settles down. It works very well. > > Ben > > "Chelam" <scpadala@gmail.com> wrote in message > news:cOednX_YcKEqlJzZnZ2dnUVZ_sOdnZ2d@giganews.com... > >>Hai >> >>XC9500 is not initialized and .log file directing me to look for hardware >>config problems. >>I have Connected Parallel cable and using JTAG interface(assembled). All >>of JTAG Connections and VCC, GND connections were made properly >>The Part Iam tring to use :PLCC84-15. >>The software ( ISE3.3i) has been tried on both win-98 and >>Win-2000.Hardware >>working with Pentium IV processor. >> >>When observed on scope, I have seen glitches on TDI TDO and TCk pins.As >>suggested in Parallel III cable, I am using HC125 ICs. How to kill them. >> >>Any suggestions! >> >>Thanks >>Chelam >> >> > > >Article: 97811
Hey ! Cool everything fit into my XC9572 and work like a charm :-) Now should I used some decoupling for the xc9572, I/O change at low freq (around 2kHz ). My question is how and how much ;-) :-)Article: 97812
Eric Smith wrote: > Jim Granville <no.spam@designtools.co.nz> writes: > >>... another idea : you could target a CPLD, like XC2C512, and see what >>that tool flow makes of it. It may give some ideas... >> >>Their PLA has a fanin of 40, a depth of 49 per 16 MC block, so it >>_should_ be very efficent - but it may be too big for the tools >>to optimize properly, in which case some middle nodes might help ? > > > Interesting idea, but the rest of the design isn't going to fit in a > CPLD, and splitting it across two chips is going to be even slower. > I'm just trying tricks to improve performance in the FPGA. I was not suggesting you move the whole design to the CPLD, just the PLA portion, to see what the tools do. The FIT reports might give you some ideas that can be used in the FPGA, and you will be able to judge the FPGA logic levels. The 512MCell device would be able to fit one output per block, and in that case the FanIN and OR widths will show you the resource needed per PLA output. Think of it as a PLA Analyzer :) -jgArticle: 97813
:-) wrote: > Hey ! > > Cool everything fit into my XC9572 and work like a charm :-) > > Now should I used some decoupling for the xc9572, I/O change at low > freq (around 2kHz ). > > My question is how and how much ;-) > > :-) If you aren't switching a huge number of outputs, one 0.01uF or 0.1uF cap per power pin (there are three) and a single bulk cap of about 1uF should be perfectly adequate. I use that on a device connected to an AC97 chain (clock at 12.288MHz, outbound stream at 256kb/s) and it works just fine. Cheers PeteSArticle: 97814
:-) wrote: > Hey ! > > Cool everything fit into my XC9572 and work like a charm :-) > > Now should I used some decoupling for the xc9572, I/O change at low > freq (around 2kHz ). > > My question is how and how much ;-) > > :-) I should have said, rather than on a device on an AC97 chain, on a XC9572XL on an AC97 chain :) Cheers PeteSArticle: 97815
Nial Stewart wrote: > That may be the case for large multi designer designs, for smaller > devices someone who understands the underlying architecture and > what they're actually trying to design to will be needed. I think that has always been the case for embedded, and realtime, and any other tightly integrated hardware/software design of any size. > The problem is, people who talk about this stuff get into their niche > and see everything else from that perspective. Few people routinely > work with a broad spectrum of systems from 4-bit to 64-bit and code > volumes from a few hundred bytes to a few dozen megabytes." Certainly true. As a consultant, I can only view the diverse sample of my clients for a perspective ... and that is certainly harder for W-2 employees that have lived inside the same company for the last 10 years. It would be interesting to take a survey at a developers embedded conference as get a better feel for the real numbers. > You seem to have a deeply entrenched view of the FPGA development future. > Only time will tell if you are correct or not, I don't believe you are > and I'll leave it at that. More like a receintly converted evangelist, with a pragmatic view of my prior 35 years of systems programming experiences casting a view on this new field and watching what is happening around me too. I did have a little fun this evening, writing a PCI target mode core in FpgaC as an example for the beta-2 release that is nearly at hand. It's not quite done, but checked in to subversion on sourceforge in the FpgaC examples directory. For something that is a bus interface state machine, it is expressed in C pretty nicely, and will get better as unions/enums are added to FpgaC. It brought out a couple problems with using I/O ports as structure members that I need to fix in FpgaC tomarrow, then finish the pci coding along with a C test bench before testing/installing on my Dini DN2K card.Article: 97816
Hi, I made a hardware module which gets as input all the PCI interrupt lines and merges them into a single one. The merge is done in the same way the misc_logic module of the Xilinx base configuration, it means all inputs are inverted except the SBR one. When using this hardware configuration the kernel is unable to boot. I think due to the interrupt line is always asserted. Does anybody know the correct way of merging the interrupt signals? Regards, IsaacArticle: 97817
Hi, there: In my application, a RAM needs to be written/read from two sets of data/address ports simultaneously. However, in the ASIC library I can only instantiate some single port RAM and RAM which can be written in one port and read from the other port. How shall I solve this problem? Thank you.Article: 97818
> I have been trying to get Altera's Stratix PCI Development Kit to work. > The device on the board is EP1s25f1020c5. > My design has a 32 bit PCI target core, alongwith a simple backend > design that > - sends a ready signal back to the PCI core following a framen signal > from the core > - and then reads in data (in case of a target write) > > When I try to use the sof file to configure the device, the whole > system hangs. The configuration LED shows that the device is > configured. Is there no config device on board you can program so the board will be configured on power up before the PCI bus configuration is performed? (Have you simulated your design ?) Nial.Article: 97819
> In my application, a RAM needs to be written/read from two sets of > data/address ports simultaneously. estimate your worst case data rates and take a ram with the sum of these data-rates (plus overhead) ... then you need to build some logic to switch between Port A and B to transfer concurrent access to a sequential access scheme bye, MichaelArticle: 97820
I agree, check Xilinx Application Note 73 http://direct.xilinx.com/bvdocs/appnotes/xapp073.pdf One of the last pages outlines the good approaches for decoupling. Ben "PeteS" <ps@fleetwoodmobile.com> wrote in message news:1141118118.178506.30000@p10g2000cwp.googlegroups.com... > :-) wrote: >> Hey ! >> >> Cool everything fit into my XC9572 and work like a charm :-) >> >> Now should I used some decoupling for the xc9572, I/O change at low >> freq (around 2kHz ). >> >> My question is how and how much ;-) >> >> :-) > > If you aren't switching a huge number of outputs, one 0.01uF or 0.1uF > cap per power pin (there are three) and a single bulk cap of about 1uF > should be perfectly adequate. I use that on a device connected to an > AC97 chain (clock at 12.288MHz, outbound stream at 256kb/s) and it > works just fine. > > Cheers > > PeteS >Article: 97821
Hi I am trying to design a DDR memory interface using Xilinx MIG 007 rel 6. However it is only generating two files - a vhdl file containing a package and a ucf file. Using a Virtex device a lot more files are created. Is this a bug or am I using it wrong? Thanks JonArticle: 97822
Jim's right, CPLDs are power hungry... 300-400mA is no problem for bigger ones, there's an equation to work it out somewhere... From http://direct.xilinx.com/bvdocs/publications/DS066.pdf You have ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f say the valid range is 180 - 250 mA for high performance Then you have to look at the package thermal characteristics for the package you use, (PLCC-84 / PQFP-100 / TQFP -100 / PQFP - 160) In the document http://www.xilinx.com/bvdocs/userguides/ug112.pdf to calculate the external temperature. I have some 95288 devices that run at 40-50 degrees, which is backed up by these equations. Note that your finger is quite a good thermometer, if it feels warm, its probably 40-50 degrees, if its not possible to touch for a prolonged period it closer to ~60, and if you simply cant touch it it's ~70, if you look at your finger and see XC95108 burned in it... then it's hotter still =) Anyways, post more info, an unusually heated CPLD could be due to many factors. Ben "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:44034412$1@clear.net.nz... > Augast15 wrote: >> hi, >> There is 4.5 V supply for entire circuit throughout the board. >> >> I am testing with schmitt trigger today thanx guies > > Can you give the full part number ? > You do realise the 95108 will get warm, anyway, because of > the high Icc - have you measured just how much current it > draws ? > 'Getting heated' is not quite good enough... > -jg >Article: 97823
Frank @ CN wrote: > Hi, there: > > In my application, a RAM needs to be written/read from two sets of > data/address ports > simultaneously. However, in the ASIC library I can only instantiate some > single port RAM > and RAM which can be written in one port and read from the other port. > > How shall I solve this problem? > > Thank you. You might get a better idea of the particulars by looking at a data sheet for IDT dual-port memories. (www.idt.com)Article: 97824
Anyone tried to use 32 bit select map programming for virtex4 chips? If you did let me know what clock speed you were able to achieve.
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