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Hey Thanks for your replies, all are very helpful. But I still don'y know which device to choose. At the moment any information about Spartan3 component: IFDDRxxx, OFDDRxxx and CycloneII: altdq, altdqs will be appreciate. Maybe someone have been using both and can compare them. -- PGWArticle: 123226
"fazulu deen" <fazulu.vlsi@gmail.com> wrote in message news:1187626825.233619.85180@x40g2000prg.googlegroups.com... > Hi all, > > Can anyone suggest me how to run an exe file in modelsim...I have > tried using > sccom -g basedes.cpp baseDesc.cpp -Wno-deprecated.Compilation and > linking was successful but i dont know the command to run an exe file > > Thanks in advance, > fazal > I assume you mean in command line mode like OSCI, if that is the case then create a top level sc_main (note the limitations in the manual) and run Modelsim as: vsim -c sc_main -sc_arg "arguments to sc_main" Hans www.ht-lab.comArticle: 123227
How would one best judge when it is acceptable to generate a clock from the outputs of an internal register instead of using the standard blocks such as DCM's? My design will go onto an XC2V8000-5 part, and I'd like to use registers to generate up to a 10MHz clock if that is alright. Any information would certainly be appreciated. I am basically trying to save DCM's for the low frequency clocks if possible.Article: 123228
bwilson79@gmail.com wrote: > How would one best judge when it is acceptable to generate a clock > from the outputs of an internal register instead of using the standard > blocks such as DCM's? My design will go onto an XC2V8000-5 part, and > I'd like to use registers to generate up to a 10MHz clock if that is > alright. Any information would certainly be appreciated. I am > basically trying to save DCM's for the low frequency clocks if > possible. > The DCMs have a somewhat restricted frequency range. Take a look at the "DCM Timing Parameters", and particularly the "Operating Frequency Ranges" in the Virtex2 data sheet.Article: 123229
On Aug 20, 2:37 pm, "bwilso...@gmail.com" <bwilso...@gmail.com> wrote: > How would one best judge when it is acceptable to generate a clock > from the outputs of an internal register instead of using the standard > blocks such as DCM's? The short answer is simply when it can be guaranteed that all flip flops that receive and are clocked by the 'register generated clock' will meet all timing requirements. For FPGAs, what generally ends up happening when you generate a clock signal from some internal register is that the clock to output delay of the flop plus the routing delay to get that clock to wherever it is you want to use it, causes too much skew on that clock signal relative to the other inputs to the flip flop and those inputs violate setup or hold time requirements. Within the FPGA world, generally the best approach is to use that 'register generated clock' not as a clock signal but as a clock enable to the flops. If you're starting from scratch, it's usually not a problem to write the code in that fashion. If you're starting from pre-existing IP you would have to modify that code to insert the clock enables on every clocked process/component. KJArticle: 123230
Somebody asked for access to old XCell magazines. I was able to download all issues #17 through #39 ( 2Q1995 through 1Q2001) by clicking on: ftp://ftp.xilinx.com/pub/documentation/xcell/xcell17.pdf etc. Peter AlfkeArticle: 123231
Peter Alfke wrote: > Yes, there are known problems. > The work-around is described in Answer Record 22462. > You can also go to the Xilinx website and search for Virtex-4 FIFO AR. > Peter Alfke > Thanks all of you. This really let me out. I used core generator to generate a new fifo16, it solved the problem. ChaoArticle: 123232
On Aug 20, 2:37 pm, "bwilso...@gmail.com" <bwilso...@gmail.com> wrote: > How would one best judge when it is acceptable to generate a clock > from the outputs of an internal register instead of using the standard > blocks such as DCM's? My design will go onto an XC2V8000-5 part, and > I'd like to use registers to generate up to a 10MHz clock if that is > alright. Any information would certainly be appreciated. I am > basically trying to save DCM's for the low frequency clocks if > possible. Judging by the size of part, I'm guessing you're doing ASIC prototyping. Generally there is no difference in the frequency the part can handle between DCM generated or other clocks. In any case the important thing is to use the BUFG or BUFGMUX to drive all of the clock loads on the net. That being said, If you're generating multiple clocks related in frequency and you need the clock edges to be coincident, the DCM can get your skew into the range where the clocks are somewhat usable. However it is generally safer to run the global clock nets at the higher frequency (least common multiple) that the clocks were generated from and use clock enables to get the frequencies you need. By the way 10 MHz is generally considered very slow in the Virtex 2 world, but I'm guessing you're looking at logic with many levels of gating between clock edges. You generally won't have problems with the speed of the clock, but with multiple clocks you need to be careful of the relative phase, since the routing delays before the global buffers can be significant, leading to hold-time violations. If your clocks are considered asynchronous for the design usage (whether or not you use a common frequency source to generate them), then you don't really need to worry about the routing delays up to the global buffers. Then you just need to make sure you have enough clock routing resources for all the quadrants.Article: 123233
Frequency is not the problem. Delay differences are. A DCM is good at aligning outgoing clock edges, down to the 100 ps level. With register outputs you have the sum of clock delays plus clock-to-out delay. In many applications the different clock domains have to communicate with each other, and that can lead to ugly hold-time violations, a problem at any, even the lowest, frequency. Under all cicumstances make sure that the registers are driven by a common global clock, so that their outputs are synchronous with almost identical delay. Peter Alfke, Xilinx Applications On Aug 20, 11:37 am, "bwilso...@gmail.com" <bwilso...@gmail.com> wrote: > How would one best judge when it is acceptable to generate a clock > from the outputs of an internal register instead of using the standard > blocks such as DCM's? My design will go onto an XC2V8000-5 part, and > I'd like to use registers to generate up to a 10MHz clock if that is > alright. Any information would certainly be appreciated. I am > basically trying to save DCM's for the low frequency clocks if > possible.Article: 123234
> IP should have a clock port and a clock enable > port. So, if you need to integrate several bits of IP, you can use one clock > with different enables. Thank you but I do not get the point. Problem was that --------------------------- If there is single global system clock, the overhead (by having only one global clock) becomes bigger and bigger. --------------------------- My question was that ----------------------------- Can FPGA come up with "Globally Asynchronous, Locally Synchronous (GALS)" design style that ASIC tends to do? If yes, how? ----------------------------- Thank you againArticle: 123235
On Mon, 20 Aug 2007 06:43:37 -0700, "Eddie H" <> wrote: >I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this. > >Eddie Is the load ECL? If so, look at the OnSemi TTL-to-ECL converter parts. Or you could do it with opamps and a few resistors. Or one common-base PNP and two resistors. Or just two resistors. JohnArticle: 123236
John, The load is is VCC referenced CML type. The positive rail is connected to 0.8V and VEE is connected to -2.5V. Do you think that I can use the TTL to ECL converter? Thanks. EddieArticle: 123237
> > (2) Number of wires grows over "g^1.5", > > ==> How did you obtain the value '1.5' ? > > This is the result of Rents expirments in the 60ies. They have been > verified many > times in later experiments, also for FPGAs. > > Kolja Sulimma Hi again :) I would like to ask one thing. I am looking for literature about : how to obtain the "growth rate of number of wires". For example, 1.5 or 1.2 or 1.6.... Could you please provide a pointer? (for example, book, paper, web, ....)Article: 123238
We are pleased to invite you to participate in the 2007 Field Programmable Logic Conference which will be held in Amsterdam, the Netherlands from August 27 until August 29. FPL is the oldest and one of the largest conferences in the domain of field programmable logic. This year's edition has received 302 papers out of which 67 were accepted as regular papers, giving an acceptance rate of 22%. There will also be several poster sessions during the breaks where 84 posters will be presented. The keynote speakers will be: - John Wawrzynek, University of California-Berkeley - Misha Burich , Senior Vice President, Research and Development Altera - Steve Trimberger, Xilinx - Ajay V. Bhatt, Intel The final program is posted on the website www.fpl.org On the website, you will also find the information regarding the conference location and hotel accommodation. ============================================================================ IMPORTANT MESSAGE Xilinx and Synplicity both organise workshops following the conference. Participation is FREE but registration is mandatory. Please consult the webpages for more information. ============================================================================ Computer Engineering Lab Delft University of Technology Mekelweg 4, 2628 cd Delft The Netherlands (t)+31-15-27-81632 (f)+31-15-27-84898 ce.et.tudelft.nlArticle: 123239
> > (2) Number of wires grows over "g^1.5", > > ==> How did you obtain the value '1.5' ? > > This is the result of Rents expirments in the 60ies. They have been > verified many > times in later experiments, also for FPGAs. > Kolja Sulimma Hi again :) I would like to ask two more things. 1. I am looking for literature about : How to obtain the "growth rate of number of wires". For example, 1.5 or 1.2 or 1.6.... Could you please provide a pointer? (for example, book, paper, web, ....) 2. I would like to obtain p value. Again, if you have pointer, please let me know. Method that I have in mind is that: In FPGA Editor, simply count number of wires between neighbor CLBs.Article: 123240
hi. i am a newibe to nios processor. i have a written a program in nios IDE. i am taking the inputr data from the pio core of the DE borad, from the external interface. now how can i send that data to my desired function in nios processor. for me the function is getdata(). waiting for replyArticle: 123241
On Aug 20, 7:18 pm, Pasacco <pasa...@gmail.com> wrote: > > Method that I have in mind is that: > In FPGA Editor, simply count number of wires between neighbor CLBs. Good idea: Do something, instead of just asking repetitive questions... Peter AlfkeArticle: 123242
On 20 Aug., 23:40, Pasacco <pasa...@gmail.com> wrote: > > IP should have a clock port and a clock enable > > port. So, if you need to integrate several bits of IP, you can use one clock > > with different enables. > > Thank you but I do not get the point. > > Problem was that > --------------------------- > If there is single global system clock, the overhead (by having only > one global clock) becomes bigger and bigger. > --------------------------- > > My question was that > ----------------------------- > Can FPGA come up with "Globally Asynchronous, Locally Synchronous > (GALS)" design style that ASIC tends to do? > If yes, how? > ----------------------------- This would require the possibility to have a lot of independend locally clock resources (like Actel quadrant clock). But how many would you suggest? Each independend clock resource is potentially slowing down the device when needing one global clock for the whole device. Second point is, that you can't locate a ff free over the whole chip, when you devide the chip in lets say 16 clock zones. You may end up in trouble when you need 50% of the chip with one clock, if the FPGA is designed to assume 16 equal sized parts. I think the fpga vendor has to do some trade-off in order to design parts that fit for most part of the market. As soon as the majority of the market needs 16 or 32 independend local clock you will have them on your desktop (give 12-18 month until an announced device will be really delivered :=) bye ThomasArticle: 123243
Pasacco wrote:
>>> (2) Number of wires grows over "g^1.5",
>>> ==> How did you obtain the value '1.5' ?
>> This is the result of Rents expirments in the 60ies. They have been
>> verified many
>> times in later experiments, also for FPGAs.
>> Kolja Sulimma
>
>
> Hi again :)
> I would like to ask two more things.
>
> 1.
> I am looking for literature about :
> How to obtain the "growth rate of number of wires".
> For example, 1.5 or 1.2 or 1.6....
>
> Could you please provide a pointer?
> (for example, book, paper, web, ....)
A good source with some reference to Rent's rule may be:
@techreport{ dehon96reconfigurable,
author = "Andre' DeHon",
title = "Reconfigurable Architectures for General-Purpose Computing",
number = "AITR-1586",
pages = "368",
year = "1996",
url = "citeseer.ist.psu.edu/dehon96reconfigurable.html" }
>
> 2.
> I would like to obtain p value.
> Again, if you have pointer, please let me know.
>
> Method that I have in mind is that:
> In FPGA Editor, simply count number of wires between neighbor CLBs.
>
Article: 123244Hi Young, Can you post your .mhs file? Göran "young" <zhang.young@gmail.com> wrote in message news:1187620326.108456.75260@19g2000hsx.googlegroups.com... > Hi all, > > I am currently work on multiple Microblazes too. I met this error > message when instantiion. > ------------------------------------------------------------------------------------------------------------------------------------ > Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC... > ERROR:MDT - xget_handle 43974304 44798020 parent : a null handle was > provided > ERROR:MDT - microblaze_3 (microblaze) - expected integer but got > "43974304 > 44798020" > while executing > "xget_handle $inhandle "parent"" > (procedure "xget_hw_parent_handle" line 2) > invoked from within > "xget_hw_parent_handle $master_addrstrobe_sink" > (procedure "::hw_microblaze_v5_00_c::check_syslevel_settings" > line 20) > invoked from within > "::hw_microblaze_v5_00_c::check_syslevel_settings 34520024" > ------------------------------------------------------------------------------------------------------------------------------------ > > The EDK version is 8.2. And I have connected each processor with an > opb bus and a lmb bus. > Thanks. > > Young Zhang >Article: 123245
There is a nice fixed-point package from Doulos which I successfully used in the past. Look it up on their website.Article: 123246
Hi, Well the subject says it all. Just wondering how does Spartan-3A DSP compares to Cyclone III in terms of power efficiency. I know the spartan is 90nm and hence should be less favourable. However, does it by any means at least approach the power performance of the cyclone? Thanks, -MannyArticle: 123247
On Tue, 21 Aug 2007 03:25:47 -0700, Manny <mloulah@hotmail.com> wrote: >There is a nice fixed-point package from Doulos which I successfully >used in the past. Look it up on their website. Manny, thanks for the free publicity, but please DON'T use it... there are a few rather significant bugs with signed arithmetic, and it's not as complete as the IEEE packages. I wish I had worked more closely with David Bishop on this, because I believe my (Doulos) package has a few features that are worth having; but it's far too late now, the IEEE package is far better developed, and it has a test suite - something I should have done in the first place, but never had time to do. I PROMISE to take the packages down from our website before the end of the week, and instead leave a pointer to the IEEE set! cheers -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 123248
On Mon, 20 Aug 2007 06:43:37 -0700, "Eddie H" <> wrote: >I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this. Is there any reason you can't simply run the target device with 2.5V on its ground rail? That would allow you to connect its +ve rail to 3.3V and its -ve rail to 0V. - BrianArticle: 123249
Brian, I am sorry I am not able to understand your suggestion. I have the source device postive rail connected to 3.3V and negative rail connected to 0V. The source device generates TTL compatible signal. My real target device positive rail is connected to 0.8V and negative rail is connected -2.5V. Thus I can not not connecte the 3.3V TTL signal directly to the traget device and need to do the voltage translation. I was thinking about using a device from analog device beween the source and target device at the following link. <http://www.analog.com/en/prod/0,2877,ADUM1411,00.html> Eddie
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