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Fabio Rodrigues de la Rocha wrote: > Hello, > > I'm a newbie in partial reconfiguration and I'm using the tutorial > by Gregory Mermoud "A Module-Based Dynamic Partial Reconfiguration > tutorial". However, I'm facing some problems following the tutorial > using the Xilinx tool ISE Webpack. > > In ISE Webpack 6.3 there is no "fpga_editor" tool so, after update > to ISE webpack 8 I thought the problem would disappear. However, I > couldn't use the bus macros files (provided in xapp290 and also > provided with the tutorial) because there some kind of incompatibility. > So, I would like to know if someone had success using the webpack for > partial reconfiguration and which version did you use. > > Thank you in advance, > Fabio I think if you check the Xilinx web site you will find that you need to purchase the full up development tools to get partial reconfiguration support. Also, be aware that partial reconfiguration is only supported for certain parts. The Virtex series is mostly supported, but the Spartan families are not. I don't know the particulars of Virtex4 support, but in the past communications between modules required the use of internal tristate buffers. Virtex4 does not have any internal tristate buffers. There is a user community of partial configuration users. You should tap into that. Partial reconfiguration is not anything like mainstream. You will find the community is a better source of support than Xilinx.Article: 97626
Austin Lesea" <austin@xilinx.com> wrote in a message news:dtklfu$6a18@xco-news.xilinx.com... > Finn, > > The stepping 0 program should be very conservative. I doubt what you are > seeing is related to the 120 MHz limitation on the step 0 parts. Have you > checked the incoming duty cycle? > > And yes, both CLKIN and CLKFB share the same specifications. So you also > need to check the duty cycle of the CLKFB as well. > > We spec from 45% to 55% for all operation. > Thank's Austin for the reply. I guess the 90 MHz is just a conservative "to be on the safe side" official spec. We'll check the duty cycle of both the CLKIN and CLKFB signals if we can. From our local FAE, we were told that the CLKFB max. freq. is the same as for the CLK2X output - but I guess it depends on whether the DCM is configured to lock on a CLK1X or CLK2X signal. We use it with the multichannel SDRAM controller at 100 MHz. and the DRAM works without the DCM deskewing - so it is related to the DCM. Thank's again, FinnArticle: 97627
"backhus" <nix@nirgends.xyz> wrote in message news:dtma4m$p4v$1@hermes1.rz.hs-bremen.de... > mnemo5@163.com schrieb: >> Thanks for your help. >> >> Actually, what I want to do is to make a hardware implementation(FPGA) >> of an Extended Kalman Filter of a tracking system(It works well in >> Matlab). >> >> I am a beginner of FPGA,so can anybody give me some suggestios? >> >> Thank you ~~ >> > Hi mnemo, > have a look at this page (especially the PDFs) > > http://www-user.tu-chemnitz.de/~beber/DA/da.php > > > It's a thesis work, where a kalman filter is used for controlling an > inverse pendulum. > > The really intresting point here is the way they use fixed point > arithmetic to keep the hardware lean. You can do that in Matlab too, by > using the fixed point toolbox (if available). > > Now comes the bad news, it's writen in german. > > Have fun > Eilert Try AltaVista's babblefish translation (you can translate a web page). TCArticle: 97628
Augast15 wrote: > I have xilinx 95108 > I am clocking by 555 timer and testing for some small project. the > 95108 is getting heated up when I connect 555 output to an IO pin(1 > number). > Then i dont understand what to do about it, this is a problem because > it rendered my previous chip non programable when I was doing same > thing? > circuit is > > > (Dip)555 ---> 95108 (plcc 84)-----> cro > > I have hand soldered everything on a general purpose board > > any body had similar problem? > > regards Sounds like the CPLD is going into a latchup state. LeonArticle: 97629
Hello Group, I could use some advice on hooking up asynchonous FIFO16s to an SRAM interface. Specifically I have two FIFOs on different clocks feeding the address lines of the SRAM, on a third clock. A control circuit looks at the two EMPTY flags to determine which fifo output should be muxed onto the address lines. Starting with empty FIFOs and looking at the result of writing an address into one of the fifo I get the events as follows: 1) Write address into fifo 2) After a few RDCLKs the EMPTY flag will sync and drop 3) At the next RDCLK, the logic sets an enable FLAG indicating which fifo it picked, and that FLAG signal goes to the fifo RD_EN 4) At the next RDCLK, the address is muxed to the address and the SRAM WR is made active. Since the RD_EN signal was on at last clock, the EMPTY flag goes high now. 5) Two clocks RDCLK later data is muxed out to the DATA bus. This is a No Bus Delay Latency SRAM. My issue is that the EMPTY flag is active low for two clock cycles and this is ambiguous. Does it mean that there are two data in the FIFO or just one? I have been thinking about running the FLAG as combinatorial logic without a clock since both EMPTY signals are synched to the RDCLK. But this doesn't seem right. Any advice would be appreciated. Thanks, Brad Smallridge Ai VisionArticle: 97630
Peter Alfke wrote: [snip] > And why insist on a 30-year old technology? > If you had picked a 50-year old technology, you would use Germanium > transistors, diodes, resistors, and capacitors, and you would really > learn the very details of circuit design. (I did, it was fun while > there was nothing better available!) What, no vacuum tubes? I miss the sound of a mag-drum spinning up - now that's a *real* system :-)Article: 97631
>"Xilinx products are not intended for use in life support applications. >Use of Xilinx products in such applications without the written consent >of the appropriate Xilinx officer is prohibited." I've seen things like that in various data books for a long time now, but I've never worked on anything where I had to pay attention to it. Is "life support" a legal term? If so, what does it mean? What about other safety critical applications? What do I have to do to get an officer to sign off? Is it a legal formality such as a letter promising not to sue, or is it something complicated and expensive like taking out an insurance policy to cover somebody suing Xilinx or paying somebody that Xilinx trusts to review the design? ... -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 97632
You should check out the EC family from Lattice. It has built in DDR memory control logic and makes interfacing up to 200Mhz possible with a low cost fabric.Article: 97633
logjam wrote: > For a while I wanted to build a computer out of relays, but I'm not > that brave yet. That's a LOT of time. :) Have you considered tinker toys? IIRC the Boston Computer Museum has a computer built out of tinker toys that is hardwired (hardsticked?) for playing tic tac toe. > I've just completed the soldering on a 19,008 LED display. Talk about > current, the thing draws 130A! So, yes...I am crazy. :) > > http://www.stockly.com/images2/060129-LED_Display_Front_2718.jpg > > http://www.stockly.com/images2/060129-LED_Display_Back_2716.jpg I don't see any drive electronics. Do they all just come on at the same time, like a giant green lamp? If they were wired in series, you could power them from a lightning rod.Article: 97634
Jeff Cunningham wrote: > logjam wrote: > > > For a while I wanted to build a computer out of relays, but I'm not > > that brave yet. That's a LOT of time. :) > > Have you considered tinker toys? IIRC the Boston Computer Museum has a > computer built out of tinker toys that is hardwired (hardsticked?) for > playing tic tac toe. > > > I've just completed the soldering on a 19,008 LED display. Talk about > > current, the thing draws 130A! So, yes...I am crazy. :) > > > > http://www.stockly.com/images2/060129-LED_Display_Front_2718.jpg > > > > http://www.stockly.com/images2/060129-LED_Display_Back_2716.jpg > > I don't see any drive electronics. Do they all just come on at the same > time, like a giant green lamp? If they were wired in series, you could > power them from a lightning rod. Out of interest, I saw an old LED matrix based device for stores to advertise things and just took a peek inside under the LED matrix and low and behold a ton of 74LS164. Serial In Parallel Out. Unfortunately the store was still using the device so I couldn't open it up for more investigation :(Article: 97635
Brad, synchronous FIFO controllers are trivial, just a state machine that manipulates the addressing of a dual-ported RAM. Asynchronous FIFOs are far more complex, especially when they are also supposed to be clocked at, say, 500 MHz. The difficulty is "only" with the flags. EMPTY goes active as a result of the read clock. The rising edge of EMPTY is thus a synchronous signal in the clock domain of interest, with <1 ns delay. But the trailing (falling) edge is caused by a write operation, thus is synchronous with the wrong clock. This requires a few synchronization flip-flops, if you want to avoid metastable problems. This delays the trailing edge of EMPTY by a few read clock ticks. I am describing a general-purpose controller. For special restricted applications, you can design all sorts of clever circuits that might avoid this extra delay... Peter Alfke, Xilinx Applications (from home)Article: 97636
cs_posting@hotmail.com wrote: > Fred Bloggs wrote: > > >... but what > > > would make sense today? > > > > > > > http://www.onsemi.com/PowerSolutions/product.do?id=MC100EPT21DR2 > > That sounds like a good idea, because theoretically we actually have > some on hand somewhere, I'll have to see if I can scare them up. Found one and wired it up as the datasheet suggests - cap coupled input to half the differential pair, the other side floating at the reference output pin voltage with decoupling cap to ground, terminating resistor across the pair. Worked quite well. The xilinx S3 kit from digilent doesn't seem to be designed with using the differential input capability as the pairs are split up all over the place. Not certain that I couldn't bias one input of a pair as a reference wherever it is and drive the other pin wherever that is, but putting it all in a little package seemed simpler.Article: 97637
>have been modified to operate with radiation-hardened magnetic RAM. I Core? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 97638
>I'm using the XilNet library on a Virtex-II Pro (PPC), and my objective >is to send quite large amounts of data via an external MAC/PHY (SMSC >91c111) to a computer running Windows XP. The server application on the >PPC is quite simple, it waits for the client to connect and then it >starts streaming the data as fast as the PC is able to receive it. The >protocol used is TCP. Talk to a software/networking geek. Lots of people have worked on making TCP go faster. It's not a simple problem - too many special cases. As a sanity check, you should run your PC against a handy web server and compare the speed and packet traces. My guess is that the TCP implementation on your PPC is dumb/simple and only allowing one un-ACKed packet at a time. That works, but won't go fast unless the other end cooperates. It makes the software a lot simpler. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 97639
The display is organized as 11x1728. When I had the boards made I thought I could handle 33 rows per refresh, but after doing duty cycle tests on the LEDs I switched to 11. 1728 bits are loaded into 216 addressable flip flops, then the data is transfered into a second set of storage registers which drives the display. There are only 11 columns to refresh. I organized the display this way because 8x11 is a very nice font. The first thing I want to do is program a pong game for the Altair. After all, the Altair and other computers of its time were known for blinking lights. I figure this is the next evolution of blinking lights. :) At 90ma per LED and a maximum number of LEDs on at any given time of 1728, well, you do the math. :)Article: 97640
> Have you considered tinker toys? IIRC the Boston Computer Museum has a > computer built out of tinker toys that is hardwired (hardsticked?) for > playing tic tac toe. The most interesting thing I've read yet is the simple fact that the first relay computers could have been built as early as 1890. Maybe we'd be running around playing StarGate, or worse...Battlestar Galactica... :)Article: 97641
Hello, Could U please suggest me a development board which really supports partial/dynamic reconfiguration, satisfying one crucial requirement: ** being shipped with one or more reference designs exploiting partial/dynamic reconf ** It would also be nice if the board: - exploited FPGA self-reconf capabilities (e.g., the Xilinx ICAP component) - cost less than 1000 $ - had an embedded OS ported on it I of course know not all these requirements can be satisfied at the same time!! :) the OS is not really important for now... Many many thanks for your help pabloArticle: 97642
Austin Lesea napisał(a): > Have you considered the immediate cost savings and no risk that you > would gain with EasyPath? > > http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/ Thank you, Austin and Gabor. Easy path looks very interesting for my use, but I've nowhere found information about power consumption of this solutions. It is very important this dice to be less hungry for power, then equivalent FPGA. Kind regards Jerzy GburArticle: 97643
Any board out there with a Virtex-II, Virtex-II Pro, or Virtex-4 will support run-time reconfiguration through the Internal Configuration Access Port (ICAP). ucLinux can be easily run on a MicroBlaze on any of these boards and Monta Vista Linux is available on the PPC on many 2vp boards. As for a board that has reference designs supporting partial dynamic reconfiguration, I know of none that exist. Partial reconfiguration is not an easy task and, as several other posts will contest to, it is currently broken in the tools. I have heard that Xilinx is working on the problem, as there is growing demand for this from the Software Defined Radio community. StephenArticle: 97644
Hi all!
I' using Handel-C to target hardware (a board with spartan IIE)
and i'd like to optimize this following macro (where cartelle[i][j][k] is a
ram unsigned 7 cartelle[6][3][5]) and posizioni is a ram unsigned 8
posizioni[90]).
Have you any idea?
Thanks!
--------
static macro proc Fill_position()
{
unsigned 7 n;
while(i!=6)
{
j=0;
while(j!=3)
{
k=0;
while(k!=5)
{
n = cartelle[i][j][k]-1;
par{
posizioni[n]=i@j@k;
k++;
}
}
j++;
}
i++;
}
}
Article: 97645
John_H wrote:
>
> The link at the online store for the starter kit info ends in HW-SPAR3E-DK
> but should end in HW-SPAR3E-SK-US - make that change and you'll see there's
> now some documentation for the board! Wheeee!!!
>
I had hopes of doing some wide LVDS testing (14-16 bit) using
the S3E board when I first saw the schematics, given the new
well-grounded expansion connector, and the soft-touch and
unloaded terminators indicating some differential pair routing.
Unfortunately, after reviewing the {mirrored} gerbers and schematics,
many of the "high speed" I/O connector signals are shared with
other LED's and connectors, resulting in huge stubs on those lines,
which are routed FPGA -> Hirose Connector -> other stuff, mostly on
inner layers ( i.e. can't cut the stub off at the Hirose pad ).
There's maybe 7 unencumbered differential pair pins routed to the
connector, of which four are input-only pins without LVDS output
drivers.
Oh well; it's still a good value for the price, I just wish they'd
manage to include provisions for high speed I/O one of these years.
Brian
Article: 97646John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource: http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ The archive is available here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ pablo wrote: > > Hello, > Could U please suggest me a development board which really supports > partial/dynamic reconfiguration, satisfying one crucial requirement: > > ** being shipped with one or more reference designs exploiting > partial/dynamic reconf ** > > It would also be nice if the board: > - exploited FPGA self-reconf capabilities (e.g., the Xilinx ICAP > component) > - cost less than 1000 $ > - had an embedded OS ported on it > > I of course know not all these requirements can be satisfied at the > same time!! :) > the OS is not really important for now... > > Many many thanks for your help > > pabloArticle: 97647
John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource: http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ The archive is available here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Fabio Rodrigues de la Rocha wrote: > > Hello, > > I'm a newbie in partial reconfiguration and I'm using the tutorial > by Gregory Mermoud "A Module-Based Dynamic Partial Reconfiguration > tutorial". However, I'm facing some problems following the tutorial > using the Xilinx tool ISE Webpack. > > In ISE Webpack 6.3 there is no "fpga_editor" tool so, after update > to ISE webpack 8 I thought the problem would disappear. However, I > couldn't use the bus macros files (provided in xapp290 and also > provided with the tutorial) because there some kind of incompatibility. > So, I would like to know if someone had success using the webpack for > partial reconfiguration and which version did you use. > > Thank you in advance, > FabioArticle: 97648
Hi Peter, Well I am in the asynchronous world, not at 500 MHz. I am using the Virtex 4 SX35 and I read that the falling edge of EMPTY is already being synched to the RDCLK by the primitive FIFO16. Is that not true? My issue is that in my simulations I see the EMPTY go on for two RDCLKs, whereas I have only written one datum into the FIFO16. BradArticle: 97649
Brad Smallridge wrote:
> Hi Peter,
>
> Well I am in the asynchronous world, not at 500 MHz. I am using the Virtex 4
> SX35 and I read that the falling edge of EMPTY is already being synched to
> the RDCLK by the primitive FIFO16. Is that not true?
>
> My issue is that in my simulations I see the EMPTY go on for two RDCLKs,
> whereas I have only written one datum into the FIFO16.
I don't get your problem ...
The sequence you decribe on your first pos looks ok, the empty flag will
stay low for two clocks because you only activate RDEN on the second
clock cycle :
1 2 3
| | |
_ _ _ _ _ _ _ _
rdclk / \_/ \_/ \_/ \_/ \_/ \_/ \_/
_____ ________________
empty \_______/
___
rden _________/ \________________
1 -> Empty goes low because some write has been done a few cycles before
2 -> Some registred control logic sample empty at 0 and raise rden for 1
cycle
3 -> rden is sampled by the FIFO16 logic and since there as no data left
(only 1 written), it raises the empty flag.
empty was low for two clock because the reading logic didn't pull the
data out of the fifo directly but instead waited for 1 cycle to register
it's input (or output).
Sylvain
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