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Quesito wrote: > Hi all, > I'm looking for a verilog to VHDL translator. > Does anybody can point me for a free tool please? emacs? Everybody wants something for free these days... How we supposed to earn a living? Cheers, JonArticle: 112751
Verilog supports inout ports. Even through the Spartan3 has no internal tristates, you should still be able to use the tristate structures in your code (this is how the Xilinx PCI v3.0 core does it) using the 1'bz assignments when not driving from your module. I changed most of my internal bus interfacing to the PCI core to be effectively your "bus_star" so I can have all the outputs going where they need when they only interface to the PCI core, not each other. This eliminated (conceptually, at least) any false paths from an internal module's output to an internal module's input. Any inter-module communication was directly connected and not part of my interface bus. I split the PCI into a dedicated input path and used their I/O path only for my output. If you synthesize with tristate values, the synthesizer may implement your bus_star or the roughly equivalent "1 if idle, 0 if there's bus contention" like what the Spartan 2E's internal BUFTs implemented electrically. "Jürgen Böhm" <jboehm@gmx.net> wrote in message news:ekhkj4$i0c$00$1@news.t-online.com... > > hi, > > currently I am working on a small hobby project with the Spartan 3 > Starter Kit board from Xilinx. I use ISE WebPack 8.1i and Verilog as a > language. > > Now some questions have come up during this: > > 1) There is a need to implement bus structures, say a 16 bit > bidirectional data bus which should connect several modules on the > highest level of the project. > > 1a) Do i understand it right that although there is an "inout" statement > for pins in verilog, this is of no use here, as it is working fully only > for IO-Pins on the main level, which connect to physical pins of the > FPGA itself ? > > 1b) Additionally there seems to be no possibility (at least for the > Spartan 3 device) that several outputs from different modules drive a > single bus line, even if care is taken for a proper assignment of 1'bz > values. > > So the consequence seems to be the following (my own thought): > if one has modules > > m1, m2, m3 > > and one is intending > > m1(inout d), m2(inout d), m3(inout d) > > one has in reality to do > > m1(in din, out d1), m2(in din, out d2), m3(in din, out d2) > > and declare a 4th module > > bus_star(in sd1, in sd2, in sd3, out sdo) > > and connect > > sdx to dx (x from 1 to 3) > din to sdo > > The 4th module I called "bus_star" as it is internally realising a star > shaped topology on the buses, wire-oring the products > > (sdi and eni) > > to give sdo. The signals eni here are enable signals, which dictate > which of the modules mx is allowed to "talk out" over dx into the sdo > and therefore into the din bus. > > Is this correctly thought ? Or is there an easier way ? > > 1c) If the way in 1b) is correct, can the duplication of the buses (d1, > d2, d3) - which are in reality maybe 32 bit wide - lead to practical > problems in routing on the FPGA chip ? (Too many lines ?) > > 2) A second, totally unrelated question: Is there a verilog simulation > module for the static RAMs on board of Spartan3 Starter Kit ? I intend > to write a synchronous RAM-controller for these asynchronous RAMs and > would like to test it before, possibly, damaging the RAMs with wrong > code. (Or is this impossible ?) > > Greetings > > Jürgen > > > -- > Jürgen Böhm www.aviduratas.de > "At a time when so many scholars in the world are calculating, is it not > desirable that some, who can, dream ?" R. ThomArticle: 112752
Jürgen Böhm wrote: > hi, > > currently I am working on a small hobby project with the Spartan 3 > Starter Kit board from Xilinx. I use ISE WebPack 8.1i and Verilog as a > language. > > Now some questions have come up during this: > > 1) There is a need to implement bus structures, say a 16 bit > bidirectional data bus which should connect several modules on the > highest level of the project. > > 1a) Do i understand it right that although there is an "inout" statement > for pins in verilog, this is of no use here, as it is working fully only > for IO-Pins on the main level, which connect to physical pins of the > FPGA itself ? > > 1b) Additionally there seems to be no possibility (at least for the > Spartan 3 device) that several outputs from different modules drive a > single bus line, even if care is taken for a proper assignment of 1'bz > values. > > So the consequence seems to be the following (my own thought): > if one has modules > > m1, m2, m3 > > and one is intending > > m1(inout d), m2(inout d), m3(inout d) > > one has in reality to do > > m1(in din, out d1), m2(in din, out d2), m3(in din, out d2) > > and declare a 4th module > > bus_star(in sd1, in sd2, in sd3, out sdo) > > and connect > > sdx to dx (x from 1 to 3) > din to sdo > > The 4th module I called "bus_star" as it is internally realising a star > shaped topology on the buses, wire-oring the products > > (sdi and eni) > > to give sdo. The signals eni here are enable signals, which dictate > which of the modules mx is allowed to "talk out" over dx into the sdo > and therefore into the din bus. > > Is this correctly thought ? Or is there an easier way ? > > 1c) If the way in 1b) is correct, can the duplication of the buses (d1, > d2, d3) - which are in reality maybe 32 bit wide - lead to practical > problems in routing on the FPGA chip ? (Too many lines ?) > > 2) A second, totally unrelated question: Is there a verilog simulation > module for the static RAMs on board of Spartan3 Starter Kit ? I intend > to write a synchronous RAM-controller for these asynchronous RAMs and > would like to test it before, possibly, damaging the RAMs with wrong > code. (Or is this impossible ?) > > Greetings > > Jürgen > > Hi Jürgen The simplest way is to define the interface for each module as inout, and be careful of the 'z' statement. The tools will (usually, now)convert this to multiplexers internally. Alternatively, you can define your own bus multiplexer (I've done this in the past) for the interconnect. Cheers PeteSArticle: 112753
Al wrote: > Jim Granville wrote: > >> Depending on what exactly you are using this for, you could also look >> at 'margining' it - generate a tapped delay, and use a faster tap for >> your delay, and check the longer one was still (just) OK, which >> means the faster one was OK with margin. > > > Sorry Jim, I didn't understand correctly what do you mean by that. It depends on just what you are trying to do - it sounds like you have some sort of centering issue ? The idea above means to create a number of delays, and then use one, but check with another - so you can at least flag a failure. The simplest delay schemes have no error flags >> >> Or, even build a calibrate phase into the tap selection. >> > Don't understand this either To do this, you need again a tapped delay line, only now you add a CAL phase - again, system dependant, but often you have a pulse/chipselect of known width, and that is used to sample/latch the Chip delay line, and store the result. That number then selects a tap to use in the desired delay. Rather more complex than a simple IO pin delay, but it self-tracks. Downside is you need a CAL pass before it is valid. -jgArticle: 112754
Hi, I'm using a microcontroller to configure a Spartan-3 device. The device seems to configure ok (the design works as expected) but INIT_B goes low & stays low after the last frame has been clocked in. According to the datasheet this indicates a CRC error. Does anyone have any idea why I'd get a CRC error but my design still works ? Thanks DaveArticle: 112755
karollo@o2.pl schrieb: > I'm using Model for Actel. When performing pre-synthesis simulation in > ModelSim, I observe 'unknown' signals in design. Do you mean VHDL uninitialized 'U'? What signal you are talking about? Bidirectional ports? Did you ever write to these signals? RalfArticle: 112756
What about when you want to implement in DSP or FPGA? What is advantages and disadvantages? Regards "Vladimir Vassilevsky" <antispam_bogus@hotmail.com> wrote in message news:RGYah.10474$yE6.262@newssvr14.news.prodigy.com... > > > ma wrote: > >> Hello, >> PLL is a good way to do FM demodulation in analogue domain. What about >> its use in digital domain? > > There are many ways to do FM demodulation in analog or digital domains. > Neither way is good or bad. It depends on what is available and what are > the performance requirements. > >> Why not to use a digital PLL to do FM demodulation? > > Yes, you can do it this way if you like. > > what is advantages(if any) and disadvantages of this >> technique? > > It can provide for somewhat better performance compared to a > discriminator. On the other side, the complexity will be significantly > higher. > > Vladimir Vassilevsky > > DSP and Mixed Signal Design Consultant > > http://www.abvolt.comArticle: 112757
1. It depends. 2. Do your homework yourself. 3. Top posting is very rude. VLV ma wrote: > What about when you want to implement in DSP or FPGA? What is advantages and > disadvantages? > > Regards >>>PLL is a good way to do FM demodulation in analogue domain. What about >>>its use in digital domain? >> >>There are many ways to do FM demodulation in analog or digital domains. >>Neither way is good or bad. It depends on what is available and what are >>the performance requirements. >> >> >>>Why not to use a digital PLL to do FM demodulation? >> >>Yes, you can do it this way if you like. >> >>what is advantages(if any) and disadvantages of this >> >>>technique? >> >>It can provide for somewhat better performance compared to a >>discriminator. On the other side, the complexity will be significantly >>higher. >>Article: 112758
Hi Antti, Could you please elaborate a little bit on your solution? I have just tried building my old design in ISE 8.2 and it doesn't update the bmm file at all, i.e. I don't see edkBmmFile_bd.bmm file being generated whatsoever... although I do know that ngbuild processes the edkBmmFile.bmm. Thanks, /Mikhail "Antti" <Antti.Lukats@xilant.com> wrote in message news:1164270882.466211.14650@f16g2000cwb.googlegroups.com... > > well my workaround is simpler and doesnt require FPGA editor to > be used, just wrap all memory blocks in its own ADDRESS_SPACE container > and rerun ngdbuild this will update the BMM file properly, but this > means that you cant do it from the GUI any more > > Antti >Article: 112759
Xilinx ISE 8.2i service pack 3 ModelSim XE III 6.1e VHDL system When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL file and the Verilog file. When ModelSim sees the verilog file it grabs it and trys to use it but then errors out saying this version of ModelSim does not support a mixed design of both VHDL and Verilog. If I go in and delete the Verilog files everything works fine. This did not happen until I recently updated my software (both Xilinx ISE and ModelSim). Anyone else run into this problem and maybe have a fix for it? Thanks DanArticle: 112760
Daveb wrote: > Hi, > > I'm using a microcontroller to configure a Spartan-3 device. The device > seems to configure ok (the design works as expected) but INIT_B goes > low & stays low after the last frame has been clocked in. According to > the datasheet this indicates a CRC error. > > Does anyone have any idea why I'd get a CRC error but my design still > works ? > > Thanks > Dave INIT_B is a "dual-purpose" pin. After config it is an I/O. Make sure you haven't inadvertently assigned this pin as an output (this can happen if your .ucf file doesn't specify LOC for all top level module outputs). When in doubt, use FPGA editor to check the pin. HTH, GaborArticle: 112761
One of my vendors (reps, really) has expressed a desire to sell me Lattice devices based on low standby power, low cost, the usual gumph. I am doing a major redesign of an existing unit and an FPGA seems to be the logical way to go for a lot of the stuff onboard. I have used devices from vendors A & X recently so I can reasonably compare their offerings in this context. I am not up to speed on Lattice. So I have a question for those who have used the devices recently (in the last couple of years preferably) 1. Are the free tools as decent (after the learning curve) as the offerings from vendors A & X? (I do know there is no free version of Modelsim for the freely downloadable version. Are there ways around that as I have a full Modelsim license)? 2. What's the typical equivalence of the logic cell to the other vendors? It's sometimes hard to compare the amount of logic so one can compare truly equivalent devices. If someone has implemented the same core and has numbers on usage, that would truly be an eye opener (but I won't be too disappointed if nobody has such a thing). 3. Are the tools reliable? (that's relative to the other vendors of course). These are, of course, only the first questions before I even commit to _looking_ at a device; I just don't want to overload the thread. Also note I am not looking for flames or icing; just honest opinions :) Cheers PeteSArticle: 112762
Jon Beniston schrieb: > Quesito wrote: > > Hi all, > > I'm looking for a verilog to VHDL translator. > > Does anybody can point me for a free tool please? > > emacs? > > Everybody wants something for free these days... How we supposed to > earn a living? > > Cheers, > Jon I have a perl script that does most of the conversion work, but usualy leaves the resuting file needing some editing.I don't know about free though I mean whats it worth ???Article: 112763
Gabor wrote: > Daveb wrote: > > Hi, > > > > I'm using a microcontroller to configure a Spartan-3 device. The device > > seems to configure ok (the design works as expected) but INIT_B goes > > low & stays low after the last frame has been clocked in. According to > > the datasheet this indicates a CRC error. > > > > Does anyone have any idea why I'd get a CRC error but my design still > > works ? > > > > Thanks > > Dave > > INIT_B is a "dual-purpose" pin. After config it is an I/O. Make sure > you > haven't inadvertently assigned this pin as an output (this can happen > if > your .ucf file doesn't specify LOC for all top level module outputs). > When > in doubt, use FPGA editor to check the pin. > > HTH, > Gabor Gabor I've checked my .ucf file & loaded it into FPGA pin editor & INIT_B isn't inadvertently being used by the design. I'm really quite baffled as to what is going on because the datasheet says that if the CRC is incorrect then the startup sequence is aborted. In this situation I'm assuming the design isn't used to configure the device. Maybe this is an incorrect assumption ? DaveArticle: 112764
Antti, Sorry, it does actually produces the file but with the exactly the same problem as you described it... So, my question on your solution still stands... Thanks, /Mikhail "MM" <mbmsv@yahoo.com> wrote in message news:4t3q31F11u5fgU1@mid.individual.net... > Hi Antti, > > Could you please elaborate a little bit on your solution? I have just > tried building my old design in ISE 8.2 and it doesn't update the bmm file > at all, i.e. I don't see edkBmmFile_bd.bmm file being generated > whatsoever... although I do know that ngbuild processes the > edkBmmFile.bmm. > > > Thanks, > /MikhailArticle: 112765
Antti wrote: >>Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working? > > same here :( > all attempts to get MPMC2 DDR2 designs to work have failed so far > have tested on custom V4 board with single 16bit device and on ML501 > all attempts failing > And same here (mch_opb_ddr2 not MPMC) - we've spent a week trying to get the mch_opb_ddr2 core talking to a Micron 512Mb 32Mx16 -37E part on a PCIe board - no luck. The board is OK - there's a MIG design that works fine. Webcase is in progress, we'll see what happens. In the process of trying to simulate the design, I discovered that the standard practice of chaining one DCM's "locked" pin to the next DCM's "reset" pin is not supported by the simulation libraries - you must have at least three clock cycles on CLKIN before releasing reset or the simulated DCM refuses to start. Sigh.. JohnArticle: 112766
So Göran, When will it be ready ;-) Lattice is already talking about that a MMU is on it's way.. Regards Finn "Göran Bilski" <goran.bilski@xilinx.com> skrev i en meddelelse news:ekgq4k$t8d2@cnn.xsj.xilinx.com... > Just one thing, MicroBlaze can of course have a MMU. > Wonder what the idea this it's impossible come from? > > Göran Bilski > > <burn.sir@gmail.com> wrote in message > news:1164647777.560172.119220@f16g2000cwb.googlegroups.com... >> Thank you for your answer Jon, >> >> >> The JTAG problem was expected, and is easy to fix (write your own JTAG >> block). Regarding the MMU, well, I have heard the MB cannot be modified >> to include a MMU, is the same true for Mico32? >> >> >> The reason that I posted my previous questions in the first place was >> that if you synthesize a Mico32 project with, say, Quartus II you will >> notice that it cant fit in _any_ Cyclone II devices. The reason is that >> the lm32_ram block is designed in such way that the Quartus synthesizer >> cannot infer MK4 blocks... >> >> >> So my question to the list: has _anyone_ tried this CPU on Altera >> devices? >> >> >> regards, burns (still waiting for my ECP2M kit) >>Article: 112767
> What signal you are talking about? Bidirectional ports? Did you ever > write to these signals? There are X(es) in the outputs. I'm sorry. I didn't describe it precisely. I've project in Altera and I want use it in actel (I don't use any altera library, it's pure vhdl) In Quartus d filp-flops, counters, registers etc. start from zeros, in model they are unkown at 0 ns and have x value through certain time. Do you know how change it in model to have known output values at 0 time (forcing signals isn't the best idea). -- KarlArticle: 112768
Xilinx has a long reputation of writing inefficient memory controllers.. ;-o Finn "Antti" <Antti.Lukats@xilant.com> skrev i en meddelelse news:1164196859.256587.287670@f16g2000cwb.googlegroups.com... > Hi > > when looking at EDK OPB_MCH_DDR2 memory controller datasheet then it > looks like each access to DDR2 memory takes about 30 system clock > cycles (60 memory clocks) > > so maximum bandwith when reading bursts is about 50MB/s and even less > when doing random reads, this sounds like EXTREMLY low performance, I > wonder if the datasheet timings are wrong, or maybe the timing is > fixed in EDK 9.1? > > Antti >Article: 112769
"Daveb" <dave.bryan@gmail.com> wrote in message news:1164743617.931311.315690@n67g2000cwd.googlegroups.com... > Hi, > > I'm using a microcontroller to configure a Spartan-3 device. The device > seems to configure ok (the design works as expected) but INIT_B goes > low & stays low after the last frame has been clocked in. According to > the datasheet this indicates a CRC error. > > Does anyone have any idea why I'd get a CRC error but my design still > works ? > > Thanks > Dave You may have the bitgen option for the INIT_B "Persist" set to "No" for this pin, making the INIT_B no longer determined by the configuration logic once you're programmed. The fact that your design works says that the INIT_B stayed high throughout the startup sequence. The flow diagram in the documentation you were probably looking at shows that a CRC error does not allow you to enter user mode.Article: 112770
"Daveb" <dave.bryan@gmail.com> wrote in message news:1164754755.908635.123850@16g2000cwy.googlegroups.com... > Gabor wrote: >> Daveb wrote: >> > Hi, >> > >> > I'm using a microcontroller to configure a Spartan-3 device. The device >> > seems to configure ok (the design works as expected) but INIT_B goes >> > low & stays low after the last frame has been clocked in. According to >> > the datasheet this indicates a CRC error. >> > >> > Does anyone have any idea why I'd get a CRC error but my design still >> > works ? >> > >> > Thanks >> > Dave >> >> INIT_B is a "dual-purpose" pin. After config it is an I/O. Make sure >> you >> haven't inadvertently assigned this pin as an output (this can happen >> if >> your .ucf file doesn't specify LOC for all top level module outputs). >> When >> in doubt, use FPGA editor to check the pin. >> >> HTH, >> Gabor > > Gabor > > I've checked my .ucf file & loaded it into FPGA pin editor & INIT_B > isn't inadvertently being used by the design. I'm really quite baffled > as to what is going on because the datasheet says that if the CRC is > incorrect then the startup sequence is aborted. In this situation I'm > assuming the design isn't used to configure the device. Maybe this is > an incorrect assumption ? > > Dave > Dave, During configuration, there are several CRC checks. The first makes sure that the bitstream device ID matches that of the device being programmed. The other CRC checks are performed after the final frame of each FRDI read sequence. After the final CRC is completed, the startup sequence begins and DONE goes high (assuming default startup). The IO's are released as well as internal FF's and RAM. As you are not using INIT as an IO in your design, the default is to attach a weak pulldown on the (all unused) IO. Thus, it is now low. Without knowing what type of file you are using with your u-proc configuration, it is hard to say what is contained in the last frame of the configuration file, but everything you are describing appears to be normal. You can always specify to leave unused IO as floating or pulled up if you wanted to test this for a sanity check. -DavidArticle: 112771
I have a bug and it seems to manifest itself only in stealth mode. When I move my LEDs to see what the trouble is, the bug goes away. I am using Xilinx XST v7.1, a ML403 dev board, and the issue seems to happen during powerup. A certain action freezes and Reset does not help. Timing is being met. I would like to add LEDs to debug the problem without there changing the circuit as little as possible. Is there a way to do this with incremental design change and how do I do that? Can I nail all the logic to the same LOCs? Is there a TIG-like constraint that would act from the LED output backwards toward the source? Thanks, Brad Smallridge Ai VisionArticle: 112772
That is the memory that I am using. Besides MPMC2, I tried plb_ddr2 also. Didn't work :( I queried through the webcase and Xilinx said they only support their own product. As the Micron DDR2 is "external" to them. They do not provide support for that. Sigh! -zyanArticle: 112773
Richard Klingler wrote: > EHLO (o; > > > What happened to the nios2 sources which were once accessable > via the doc/degree ftp login documented on the Altera website? > > Unfortunately Altera stopped sponsoring me with Quartus/NIOS > for doing core tests and porting cores to sopc builder...so > I won't get any more nios2 toolchain sources on CD (o; > > > > cheers > rick > > I found this link very useful. http://nioswiki.jot.com/CrossGcc I built the sources on Linux a week or two ago. -RichArticle: 112774
Hi Brad, This might be an even better solution if you know exactly where you would like to probe. After PAR, you can open FPGA editor and insert a "probe" (See right-hand column of FPGA editor -- Add Probe). This probe is essentially a route connected directly to your net of interest, and it can be routed directly to a spare pin -- at which point you could probe it (or drive a LED I guess) to help you debug your problem. FPGA sorts out the primitives, nets etc. out for you in a logical manner so you should be able to trace down the net of interest. FPGA editor will also provide you with a timing estimation (ie delay due to routing) of skew that will occur between the IOB and the net of interest. The nifty part of this solution is that you will be able to probe your problem AFTER synthesis and par -- so you are probing your EXACT design of interest (ie your problem can't 'go away'). Hope that helps Gordon Avnet FAE Brad Smallridge wrote: > I have a bug and it seems to manifest itself only > in stealth mode. When I move my LEDs to see what > the trouble is, the bug goes away. > > I am using Xilinx XST v7.1, a ML403 dev board, and > the issue seems to happen during powerup. A certain > action freezes and Reset does not help. Timing is > being met. > > I would like to add LEDs to debug the problem without > there changing the circuit as little as possible. > Is there a way to do this with incremental design change > and how do I do that? Can I nail all the logic to the > same LOCs? Is there a TIG-like constraint that would act > from the LED output backwards toward the source? > > Thanks, > > Brad Smallridge > Ai Vision
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