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Dan K schrieb: > Xilinx ISE 8.2i service pack 3 > ModelSim XE III 6.1e > VHDL system > > When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL > file and the Verilog file. > When ModelSim sees the verilog file it grabs it and trys to use it but then > errors out saying this version of ModelSim does not support a mixed design > of both VHDL and Verilog. If I go in and delete the Verilog files > everything works fine. This did not happen until I recently updated my > software (both Xilinx ISE and ModelSim). > > Anyone else run into this problem and maybe have a fix for it? > > Thanks > > Dan > > > Hi Dan, Modelsim itself is blind and neither sees files nor grabs them without being told to do so. :-) You are probably starting Modelsim from the ISE Project Navigator. PN creates a script for Modelsim (*.fdo). This script tells Modelsim which files to compile and what else shall be done. The real problem is that good old bilangual ISE favors verilog when converting or searching for files. Try to create a schematic and simulate it. Guess what, it will be converted to a verilog *.vf file. Really great, when you are doing VHDL-Designs and your unilingual Modelsim XE is installed with VHDL. This behavior of ISE PN is a mayor annoyance for VHDL designers. For schematics the workaround is to set the "View HDL..." properties to VHDL. For coregen you found out to delete the verilog files, but if I remember it correctly, there may also be a property that can be set to avoid the use of the verilog files. ISE PN should have a global project property where designers can chose between VHDL, verilog and bilangula flows. And this property should be stored like the other global settings like the chip and the prefered simulator etc. Have a nice simulation EilertArticle: 112776
Hi DAn, You need a "midex mode" license for ModelSim if you want to simulate verilog and vhdl code at the same time. This license is not included in your Modelsim XE Xilinx Edition. If you dt want to purchase an apropiate Modelsim Version (10k=80) you have to decide which language you wanna use. Bye Helmut Dan K wrote: > Xilinx ISE 8.2i service pack 3 > ModelSim XE III 6.1e > VHDL system > > When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL > file and the Verilog file. > When ModelSim sees the verilog file it grabs it and trys to use it but th= en > errors out saying this version of ModelSim does not support a mixed design > of both VHDL and Verilog. If I go in and delete the Verilog files > everything works fine. This did not happen until I recently updated my > software (both Xilinx ISE and ModelSim). > > Anyone else run into this problem and maybe have a fix for it? >=20 > Thanks >=20 > DanArticle: 112777
Hi, I am presently involved in a project dealing with a pretty large design in a Stratix II GX chip with a Nios II processor. Is there anyway to perform hardware in the loop simulation where the Nios II would be running on a board while modelsim is simulating the design ? Does anyone have an advice as to how simulation times could be improved when involving Nios II processor ? Best regards, JF HassonArticle: 112778
dh2006 schrieb: > I've read much about Double Buffering, especially that it is good > practice (on Xilinx devices) to double buffer data signals (such as ADC > inputs), and place the double buffer in the IOB associated with the > pin. > > Can someone explain to me, what double buffering is and why you would > use it? Any links to reference information would be appreciated. > > Many thanks. Double buffering is one way of syncronising signals which are being passed between clock domains, primarily in order to prevent problems with metastability.Its not only xilinx devices in which this is used its used in any situation where signals which are asyncronous to some logic need to be syncronised.There are other methods which can be used to achieve the same thing.A google search on metestabilty will give you further information.Article: 112779
Even if I know exactly if and when, it's nothing that I can reveal on this public newsgroup. Although I not that worried about the Mico32. Most of MicroBlaze competition (and I also think that is the same for the other soft processor) is not other soft processor but rather standard processors. I just trying to get enough good performance and features in the Microblaze. Together with a low cost FPGA you can make a business case of replacing a standard processor with a soft processor inside the FPGA. Of course the customer needs to have a FPGA in the product already so they are familiar with FPGA and the soft processor is only a delta-cost of the extra needed LUTs. Customer totally unaware of FPGA are not very likely to in a new product start using FPGAs and at the same time start using soft processor. Göran "Finn S. Nielsen" <removfinnstadel@tiscali.dk> wrote in message news:456cc5c9$0$179$157c6196@dreader1.cybercity.dk... > So Göran, > > When will it be ready ;-) > > Lattice is already talking about that a MMU is on it's way.. > > Regards > > Finn > > > > "Göran Bilski" <goran.bilski@xilinx.com> skrev i en meddelelse > news:ekgq4k$t8d2@cnn.xsj.xilinx.com... >> Just one thing, MicroBlaze can of course have a MMU. >> Wonder what the idea this it's impossible come from? >> >> Göran Bilski >> >> <burn.sir@gmail.com> wrote in message >> news:1164647777.560172.119220@f16g2000cwb.googlegroups.com... >>> Thank you for your answer Jon, >>> >>> >>> The JTAG problem was expected, and is easy to fix (write your own JTAG >>> block). Regarding the MMU, well, I have heard the MB cannot be modified >>> to include a MMU, is the same true for Mico32? >>> >>> >>> The reason that I posted my previous questions in the first place was >>> that if you synthesize a Mico32 project with, say, Quartus II you will >>> notice that it cant fit in _any_ Cyclone II devices. The reason is that >>> the lm32_ram block is designed in such way that the Quartus synthesizer >>> cannot infer MK4 blocks... >>> >>> >>> So my question to the list: has _anyone_ tried this CPU on Altera >>> devices? >>> >>> >>> regards, burns (still waiting for my ECP2M kit) >>> > >Article: 112780
G=F6ran Bilski schrieb: > Even if I know exactly if and when, it's nothing that I can reveal on this > public newsgroup. > > Although I not that worried about the Mico32. > Most of MicroBlaze competition (and I also think that is the same for the > other soft processor) is not other soft processor but rather standard > processors. > > I just trying to get enough good performance and features in the Microbla= ze. > Together with a low cost FPGA you can make a business case of replacing a > standard processor with a soft processor inside the FPGA. > Of course the customer needs to have a FPGA in the product already so they > are familiar with FPGA and the soft processor is only a delta-cost of the > extra needed LUTs. > > Customer totally unaware of FPGA are not very likely to in a new product > start using FPGAs and at the same time start using soft processor. > > G=F6ran > G=F6ran, there defenetly are non-FPGA aware customers using FPGA -softcore CPUs and I think there will be more and more. Of course if there will be no more low cost large FPGAs from Xilinx then those customers are likely to use either Lattice ECP/M or Cyclone-3. Because smallest ECPM has more onchip memory than largest Spartan-3A !! I still hope Spartan-4 will not exclude large devices as 3e and 3a do This (SW people using FPGA softcore) may however be rather disappointing experience, as it is sometimes hard to explain the benefits of the softcore, specially if it lacks MMU AnttiArticle: 112781
John Williams schrieb: > Antti wrote: > > >>Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working? > > > > > same here :( > > all attempts to get MPMC2 DDR2 designs to work have failed so far > > have tested on custom V4 board with single 16bit device and on ML501 > > all attempts failing > > > > And same here (mch_opb_ddr2 not MPMC) - we've spent a week trying to get the > mch_opb_ddr2 core talking to a Micron 512Mb 32Mx16 -37E part on a PCIe board - > no luck. The board is OK - there's a MIG design that works fine. > > Webcase is in progress, we'll see what happens. > > In the process of trying to simulate the design, I discovered that the standard > practice of chaining one DCM's "locked" pin to the next DCM's "reset" pin is not > supported by the simulation libraries - you must have at least three clock > cycles on CLKIN before releasing reset or the simulated DCM refuses to start. > Sigh.. > > John John, the DDR2 issue gets more confusing: OPB_MCH_DDR2 (EDK 8.2 SP2) worked for me like magic, just out of box, all working, no issues PLB_DDR2 works on ML501 (but uses patched EDK core), well Xilinx reports that out of box PLB_DDR2 also works on ML501 (I have failed with it) there is customer report who got PLB_DDR2 working on custom board (but after getting patch from Xilinx FAE) MPMC2 has SERIOUS bug with the OPB interface, the datapath FIFO used just doesnt work at all, everything stalls on first read, tested both FPGA design and simulation I am now trying MPMC2 core with PLB selected as port interface, I hope this will work (I have problems at the moment with the OPB2PLB bridge but those are possible minor mis-config) For what my impressions are, is that DDR2 isnt so much harder than DDR at all, at least when you have single chip (and not SODIMM), if you happen to have config setup that is supported by the IP core the MIG test is something you should not trust 100% I have seen patches to MIG where in commentary it says, "ah this must be delayed by 2 clocks, or the error out will not work.." so make sure the MIG test really is reporting errors, that is inject errors and monitor the status AnttiArticle: 112782
MM schrieb:
> Antti,
>
> Sorry, it does actually produces the file but with the exactly the same
> problem as you described it... So, my question on your solution still
> stands...
>
> Thanks,
> /Mikhail
this is non working, generated by EDK 8.2
ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE bram_combined COMBINED [0x00000000:0x0002FFFF]
ADDRESS_RANGE RAMB16
BUS_BLOCK
END_BUS_BLOCK;
END_ADDRESS_RANGE;
ADDRESS_RANGE RAMB16
BUS_BLOCK
END_BUS_BLOCK;
END_ADDRESS_RANGE;
ADDRESS_RANGE RAMB16
BUS_BLOCK
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
the fix is to SPLIT the address space in seperate addresses spaces
so in each address space there is only one BUS_BLOCK
the in it seems to work, eg all blocks get "PLACED" ok
Antti
Article: 112783"PeteS" <peter.smith8380@ntlworld.com> wrote in message news:xJ2bh.63556$r4.20296@newsfe3-gui.ntli.net... > One of my vendors (reps, really) has expressed a desire to sell me Lattice > devices based on low standby power, low cost, the usual gumph. > > I am doing a major redesign of an existing unit and an FPGA seems to be > the logical way to go for a lot of the stuff onboard. I have used devices > from vendors A & X recently so I can reasonably compare their offerings in > this context. I am not up to speed on Lattice. > > So I have a question for those who have used the devices recently (in the > last couple of years preferably) > > 1. Are the free tools as decent (after the learning curve) as the > offerings from vendors A & X? (I do know there is no free version of > Modelsim for the freely downloadable version. Are there ways around that > as I have a full Modelsim license)? > > 2. What's the typical equivalence of the logic cell to the other vendors? > It's sometimes hard to compare the amount of logic so one can compare > truly equivalent devices. If someone has implemented the same core and has > numbers on usage, that would truly be an eye opener (but I won't be too > disappointed if nobody has such a thing). > > 3. Are the tools reliable? (that's relative to the other vendors of > course). > > These are, of course, only the first questions before I even commit to > _looking_ at a device; I just don't want to overload the thread. > > Also note I am not looking for flames or icing; just honest opinions :) > > Cheers > > PeteS I'm really glad you asked this. I recently (1st quarter this year) decided to give Lattice a try after being in the X camp since the very first 64 logic cell device. I moved over because I could get no sense out of the X distributor in the UK (there was only one but there is now annother so things may improve) and I just could not work out which devices were actually available and how much they would cost. I had none of these problems with Lattice so I have designed in an ECP15E device. I have had no problems with the device and only very minor problems with the tools. (I use AldecHDL as my primary simulator.) My application is not leading edge, is very low volume and not very price sensitive so you might well come to a different conclusion in other circumstances. So far I'm (very) happy. Michael Kellett www.mkesc.co.ukArticle: 112784
Hi Pete, We are investigating a port from A to L. Here is what I've learned so far > 1. Are the free tools as decent (after the learning curve) as the > offerings from vendors A & X? (I do know there is no free version of > Modelsim for the freely downloadable version. Are there ways around that > as I have a full Modelsim license)? Not as good as A, not as bad as X. There are some problems with their graphical flow. The java applications often die and stay in background eating cpu and ram :( I never start simulation from ispLever, so I cant help you with your other question. > 2. What's the typical equivalence of the logic cell to the other > vendors? It's sometimes hard to compare the amount of logic so one can > compare truly equivalent devices. If someone has implemented the same > core and has numbers on usage, that would truly be an eye opener (but I > won't be too disappointed if nobody has such a thing). I think ECP2 is pretty equal to Spartan3, but a little faster. Only a subset of cells can be used as SRL16. They also support fewer IO standards, on the other hand ECP2M has SERDES. I did a simple benchmark with few designs and the ECP2 almost always got higher fmax and lower area that XC3S and EP2C. BTW, www.fpga.ch has a comparision between A3P, EP1C and ECP1. > 3. Are the tools reliable? (that's relative to the other vendors of course). They use Synplify (and Precision) for synthesis. Not as good as Quartus or XST, but it does the job. Might need some tweaking however when inferring memories.Article: 112785
G=F6ran Bilski wrote: > Just one thing, MicroBlaze can of course have a MMU. > Wonder what the idea this it's impossible come from? I actually picked that up here in the NG. Anyway, since you obviously know more about MB than the random NG posters, I take it that it can be doneArticle: 112786
karollo@o2.pl wrote:
> > What signal you are talking about? Bidirectional ports? Did you ever
> > write to these signals?
>
> There are X(es) in the outputs. I'm sorry. I didn't describe it
> precisely. I've project in Altera and I want use it in actel (I don't
> use any altera library, it's pure vhdl)
> In Quartus d filp-flops, counters, registers etc. start from zeros, in
> model they are unkown at 0 ns and have x value through certain time.
> Do you know how change it in model to have known output values at 0
> time (forcing signals isn't the best idea).
>
> --
> Karl
I can think of three answers here:
1. You use the Quartus simulator. Whenever the output of quartus and
Modelsim differ, Modelsim is always right. So the correct answer _is_
'X', probably because you dont assert reset in the beginning of
simulation.
2. you actually mean post-synthesis simulation,
In pre-synthesis simulation, ('0' and 'X') yields '0', in
post-synthesis simulation on the other hand ('0' and 'X') yields 'X'.
Do a reset in the beginning of the simulation.
3.
In Altera you can decide the start value of memories and registers, in
Actel you cant do that.
Do a reset in the beginning of the simulation.
Article: 112787Hi! I am starting a DVI Board design. The purpose is to generate DVI data in an FPGA. interface it to an DVI transmitter from silicon image. There are quite a lot of data formats to support with dvi. a list is shown below. my question is ho to generate this pixel clocks, ranging from 52MHz to 165MHz. Can anyone give a hint? we are using a V5LXT with integrated PLL features. regards hans formatver hor FrRatePclk[MHz] Drate [Mbps] WUXGA 1920 1200 85 281,25 6750 WUXGA 1920 1200 75 245,25 5886 WUXGA 1920 1200 60 193,25 4638 WUXGA 1920 1200 50 158,25 3798 UXGA 1600 1200 85 235 5640 UXGA 1600 1200 75 204,75 4914 UXGA 1600 1200 60 161 3864 UXGA 1600 1200 50 131,5 3156 SXGA 1280 1024 85 159,5 3828 SXGA 1280 1024 75 138,75 3330 SXGA 1280 1024 60 109 2616 SXGA 1280 1024 50 88,5 2124 XGA 1024 768 85 94,5 2268 XGA 1024 768 75 82 1968 XGA 1024 768 60 63,5 1524 XGA 1024 768 50 52 1248Article: 112788
Hi all, I'm working with an virtex2pro and EDK. I need help on locking bus for sequential writing on a register. I would PPC write sequentially to a FIFO connected to OPB, and I'm trying to reduce timing. Anyone could help? ThanksArticle: 112789
On 2006-11-28, John_H <newsgroup@johnhandwork.com> wrote: > If you synthesize with tristate values, the synthesizer may implement your > bus_star or the roughly equivalent "1 if idle, 0 if there's bus contention" > like what the Spartan 2E's internal BUFTs implemented electrically. A big problem here is that you might have different behavior in simulation than in reality unless you take care. For example, if you assign z to some signals that are used as control signals you might have some problems as seen in the following example: if(controlsignal) begin Dosomething; end Dosomething will not happen in simulation because z is not true. However, it will do something in reality because the signal will in reality be 1 in this situation due to the pullup you described. (I guess you could add pullups or pulldowns to the signals in the source code to avoid this in Verilog.) But this still shows that you must be careful about this situation. My advice is to totally avoid tristates internally if you can avoid it. /AndreasArticle: 112790
Jon I will be happy to have a look at your perl script! Francesco jez-smith@hotmail.co.uk wrote: > Jon Beniston schrieb: > > > Quesito wrote: > > > Hi all, > > > I'm looking for a verilog to VHDL translator. > > > Does anybody can point me for a free tool please? > > > > emacs? > > > > Everybody wants something for free these days... How we supposed to > > earn a living? > > > > Cheers, > > Jon > I have a perl script that does most of the conversion work, but usualy > leaves the resuting file needing some editing.I don't know about free > though I mean whats it worth ???Article: 112791
hansman wrote: > Hi! > > I am starting a DVI Board design. The purpose is to generate DVI data > in an FPGA. interface it to an DVI transmitter from silicon image. > There are quite a lot of data formats to support with dvi. a list is > shown below. my question is ho to generate this pixel clocks, ranging > from 52MHz to 165MHz. Can anyone give a hint? > > we are using a V5LXT with integrated PLL features. > > > regards > hans > > > formatver hor FrRatePclk[MHz] Drate [Mbps] > WUXGA 1920 1200 85 281,25 6750 > WUXGA 1920 1200 75 245,25 5886 > WUXGA 1920 1200 60 193,25 4638 > WUXGA 1920 1200 50 158,25 3798 > UXGA 1600 1200 85 235 5640 > UXGA 1600 1200 75 204,75 4914 > UXGA 1600 1200 60 161 3864 > UXGA 1600 1200 50 131,5 3156 > SXGA 1280 1024 85 159,5 3828 > SXGA 1280 1024 75 138,75 3330 > SXGA 1280 1024 60 109 2616 > SXGA 1280 1024 50 88,5 2124 > XGA 1024 768 85 94,5 2268 > XGA 1024 768 75 82 1968 > XGA 1024 768 60 63,5 1524 > XGA 1024 768 50 52 1248 Is your intent to generate the frequencies inside the FPGA? If this is the case, you might find that you need to update the bitstream to change the DCM loop multiply and divide constants. This was at least true in Virtex 2 / Spartan 3. There are many options for frequency generation off-chip. Look at Cypress offerings (e.g. CY22392 but beware of jitter), and ICS (too many to list here). Some PLL chips allow you to route the feedback externally, allowing at least partial control of the frequency directly in the FPGA. Others have simple 2 or 3 wire interfaces to update internal registers. Most of these chips can take the reference directly from an inexpensive crystal, or you can drive them with an existing clock frequency. HTH, GaborArticle: 112792
Co-simulation with real hardware would take a LOT of software work for the API calls from the simulator to the hardware, and would require a pretty good interface between the computer runninng the simulation and the hardware. You might try creating your testbenches such that they are synthesizable, and load them into the chip too (assuming there's enough room). You can't use assert statements or text io, but you could set spare outputs that could be monitored with a scope or logic analyzer. With built-in wrap-around interfaces, the processor in the design could run a lot of tests. Andy jfh wrote: > Hi, > > I am presently involved in a project dealing with a pretty large design > in a Stratix II GX chip with a Nios II processor. Is there anyway to > perform hardware in the loop simulation where the Nios II would be > running on a board while modelsim is simulating the design ? Does > anyone have an advice as to how simulation times could be improved when > involving Nios II processor ? > > Best regards, > > JF HassonArticle: 112793
burn.sir@gmail.com writes:
{about Lattice}
> They use Synplify (and Precision) for synthesis. Not as good as Quartus
> or XST, but it does the job. Might need some tweaking however when
> inferring memories.
>
Can you provide more details? My experience to date has been that
Synplify is better than XST, especially on runtime, and almost all the
time on size & speed.
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 112794"hansman" <thehansman@gmail.com> writes: > Hi! > > I am starting a DVI Board design. The purpose is to generate DVI data > in an FPGA. interface it to an DVI transmitter from silicon image. > There are quite a lot of data formats to support with dvi. a list is > shown below. my question is ho to generate this pixel clocks, ranging > from 52MHz to 165MHz. Can anyone give a hint? > With a PLL - generate a line-clock and configure the PLL to multiply this up to the number of pixels (including sync widths) that you need for your chosen resolution. > we are using a V5LXT with integrated PLL features. > I guess that's a DCM rather than an analogue PLL. In which case the jitter on the multiplied signal is likely to be too high for the DVI chip to tolerate (as that has another PLL in it which multiplies up the pixel clock to multiplex the data bits down the DVI wires). Or does V-5 now have low enough jitter PLLs for this to work? When I did it, I used an external ICS1523 PLL, with a lineclock from the FPGA, to feed pixel clock back to the FPGA and to the DVI chip (a TI TFP410). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 112795
Hi all, I wonder if anyone here are in the same situation as me. I am think of buying a new PC, but wondering if I should wait for Windows Vista become available first. Have anyone try running FPGA tools (Xilinx Webpack, Modelsim XE, Quartus, Cygwin) on Windows Vista beta? Does it work okay? Or should I get a "Vista capable" PC now and upgrade later? (sound too much hassle to me, but it might be better?) Thanks. regards, JoeArticle: 112796
Martin Thompson wrote: >> we are using a V5LXT with integrated PLL features. > I guess that's a DCM rather than an analogue PLL. Nope, Virtex5 does indeed have analogue PLLs, half as many as DCMs. The FAE told us this was because of the increasing popularity of spread spectrum clocks (like in PCs), and the only way to handle those is a PLL, so Xilinx saw a demand there. Can't comment on how good they are (jitter-wise and such), Xilinx has not yet graced us with Virtex5-parts :) -- The FROM:-address in this posting is valid until the end of the month only, after that every e-mail sent to this address will bounce. If you want to contact me after that, try figuring out what the next valid address will be...Article: 112797
Hi all, Would anyone be able to direct me to (or provide me with) any materials related to this board that I've got. http://trifs.dyndns.org/xilinx%20board.jpg It's an Xilinx XC3020-50 chip on a board of which I cannot locate anything describing the layout or functions (dip switches/leds/connections/etc...). The only markings on the board are: Xilinx (1994 (C))(on front side) 0430456 rev 04 (on front side) 1280037 Rev 02 (on back side) I got this board thinking it would be good to continue my education with FPGA's, of which I'm just starting (so please go easy on me :>)). I've tried Xilinx's site and can only get documentation on the chip itself. Xilinx won't provide me with any support on this whatsoever! Internet searches turn up nothing. Is this really that old of a board/chip that I should just scrap this thing and try something else? Thanks for any input... ScottArticle: 112798
Joseph <joseph.yiu@obviously-not-a-valid-domain.com> wrote: >I wonder if anyone here are in the same situation as me. >I am think of buying a new PC, but wondering if I should >wait for Windows Vista become available first. >Have anyone try running FPGA tools (Xilinx Webpack, >Modelsim XE, Quartus, Cygwin) on Windows Vista beta? >Does it work okay? >Or should I get a "Vista capable" PC now and upgrade later? >(sound too much hassle to me, but it might be better?) What is two months waiting time worth to you ..? What hinders you to use MS-XP after Vista is released..? You most likely will pay for hardware that will be consumed by Vista Bells & Whistles that won't benefit your vhdl/verilog processing.Article: 112799
Antti, I've done as you say but something is not working, the updated bmm file is not being created at all... You said something before to the effect that after correcting the bmm file one can't use GUI anymore... What exactly did you mean? What is the correct syntax for the file with splitted address space? I used the one generated by 8.1. It looks like this: ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xfffe8000:0xfffeffff] BUS_BLOCK END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK plb_bram_if_cntlr_0_bram RAMB16 [0xfffe0000:0xfffe7fff] BUS_BLOCK END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK plb_bram_if_cntlr_2_bram RAMB16 [0xffff0000:0xffff7fff] BUS_BLOCK END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK plb_bram_if_cntlr_3_bram RAMB16 [0xffff8000:0xffffffff] BUS_BLOCK END_BUS_BLOCK; END_ADDRESS_BLOCK; So the keywords are a little different... I guess that's my problem... Do I need both ADDRESS_SPACE and ADDRESS RANGE? Thanks, /Mikhail "Antti" <Antti.Lukats@xilant.com> wrote in message news:1164790682.244386.47650@n67g2000cwd.googlegroups.com... > MM schrieb: > >> Antti, >> >> Sorry, it does actually produces the file but with the exactly the same >> problem as you described it... So, my question on your solution still >> stands... >> >> Thanks, >> /Mikhail > > > this is non working, generated by EDK 8.2 > > ADDRESS_MAP microblaze_0 MICROBLAZE 100 > ADDRESS_SPACE bram_combined COMBINED [0x00000000:0x0002FFFF] > ADDRESS_RANGE RAMB16 > BUS_BLOCK > END_BUS_BLOCK; > END_ADDRESS_RANGE; > ADDRESS_RANGE RAMB16 > BUS_BLOCK > > END_BUS_BLOCK; > END_ADDRESS_RANGE; > > ADDRESS_RANGE RAMB16 > BUS_BLOCK > > END_BUS_BLOCK; > END_ADDRESS_RANGE; > END_ADDRESS_SPACE; > > END_ADDRESS_MAP; > > the fix is to SPLIT the address space in seperate addresses spaces > so in each address space there is only one BUS_BLOCK > > the in it seems to work, eg all blocks get "PLACED" ok > > Antti >
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