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Hi, LUT usage goes down when some pipelining is added to large combinationnal functions because synthesis does not need to do as much logic replication to improve timings or use as many CLB resources (like LUTs) for signal buffering on high fanout paths. As for register balancing, if you enable moving the first/last FFs along with register balancing, XST usually does a pretty decent job relocating up to two registers - here, I mean two extra registers besides the input and output ones. Beyond that, results tend to vary wildly and are mostly underwhelming. After experimenting with pipelining some of my oldish code using XST's balancing, I feel like anything that needs more than two levels of automatic pipelining should be rewritten to be more explicitly pipelined - otherwise, it becomes difficult to figure out exactly what should be happening exactly when and this makes debugging more painful than necessary. Semi-automatic pipelining (up to two intermediate FFs) usually works well with XST and I have been consistently happy(*) with results ever since I started sticking to this as the upper limit of pipelining automation. (*) Well, as happy as one can be when Xilinx's software crashes every couple of hours under intensive use, when XST crashes on BRAM inference code copy-pasted from the XST coding style manual, etc. Patrick Dubois wrote: > Hello all, > > I realized something interesting today, adding registers in your design > can actually reduce the slice usage (in Virtex-II Pro). For example, I > started a design with minimal pilelining to keep it simple at first. > > Before pipelining, I had the following usage: > Slices: 2433 > Flip Flops: 2287 > LUT: 2981 (seems a bit high, might be a typo in my notebook) > > After pipelining, I get: > Slices: 1973 > Flip Flops: 2615 > LUT: 2069 > > I knew from the begining that pipelining would be needed but I didn't > realize that it could save me some slices (on top of the obvious max > frequency increase). > > I might as well throw in a question while I'm at it. Now I need to > pipeline further (need to go from 78 MHz to 100 MHz) but it gets more > complicated, I would need to pipeline the function "to_signed (from > float32)" from the VHDL-200X float_pkg. > Any suggestions on how to do that? I read somewhere that one can add an > extra level of registers, and let the tool figure out how to do the > register retiming. I would use xst with the "register_balancing yes" > flag, but I'm not sure how good xst is at register balancing. > > > Thanks. > > Patrick Dubois >Article: 112026
Hi all Does Microblaze (v 5.00) stall on store (to a non-BRAM memory) till it receives an ack, or can it process other instructions while this store is on fly? Thanks MuraliArticle: 112027
"nana" <nmichou@utk.edu> wrote in message news:1163510544.480878.182590@f16g2000cwb.googlegroups.com... > Helllo, > Does anyone know about transfering data between two xupv2p boards, that > is from one board to another? > I appreciate your help > > nmichou > Dear Nana Nmichou, You could display the data on a monitor driven by the XSGA port of one board, and use a USB webcam to read the data back into the other board. HTH, Syms.Article: 112028
Serialize it to 32 bit packets... rasic wrote: > How can I send a 256 bit data across a 32 bit bus/ Could any one please > help me with how I can do this using verilog. > ThanksArticle: 112029
Hi Murali, It can never proceed until the memory access is finished. MicroBlaze currently don't have an out-of-order exexcution. Göran "Murali" <vmurali@mit.edu> wrote in message news:455a9e33$0$558$b45e6eb0@senator-bedfellow.mit.edu... > Hi all > > Does Microblaze (v 5.00) stall on store (to a non-BRAM memory) till it > receives an ack, or can it process other instructions while this store is > on fly? > > Thanks > MuraliArticle: 112030
hi awa, I took a short glance at some papers about your topic. The term low level programming (model) seems to be used with multiple meanings, thats why you are confused. (me too, to be honest) One thing is programming on the assembly level, creating fast libraries for image processing algorithms. But then it is only refered as "low level programming" w/o "model". The other is the implementation of the basic algorithms. As in arithmetics on FPGAs, where you can choose between parallel, serial and pipelined architectures, the main question in image processing is: Using a sequential or a parallel approach. In both cases each approach has its advantages and disadvantages. The main disadvantage for FPGAs seems to be that (besides their ability to be reconfigurable, but that also needs some kind of control) they are not flexible enough when you want or need to change/adapt your algorithm to a specific problem. In Software, once the algorithm is written, you check how many Processors and Memory is available and look in the library for the best algorithm for your problem and (if applicable) share the data and (sub)programs dynamically over the processors. In hardware you don't have this flexibility, or have to use a large controlling overhead, which minimizes the processing gain you normally have by using FPGAs instead of µPs. In general an FPGA has the advantage of massive parralel computation power, but for immage processing, some algorithms have data depentant runtimes. So synchronizing results becomes an additional task. There may be an approach to overcome these problem. One is FPGA-internal processors making it a hardware software codesign,(Hardware for algorithms, software for data handling) but then it may be no longer seen as low level...? If you have to do image processing in a very specialized way (e.g. image based quality control in production flows) where the same kind of image has to be processed always in the same manner with one specialized piece of hardware the FPGA will surely beat any ordinary computer hardware. So, you have to look which field you are really working in. Scientific image processing or industrial image processing? Best regards Eilrt awa schrieb: > Hi, > > I am new in this area and would be happy to have some feedbacks. > > > Does anyone have a clear cut answer as to what really low level > programming model in image processing is? I have found different > definitions and getting confused. > > > My other question is, why does FPGA is said to have major disadvantage > in modelling at low level? > > > Thank you. >Article: 112031
Hi. On Virtex4, is is possible to connect a BRAM to both instruction and data OCM busses of the PPC? I would like the OCM to behave similar to a non-cached plb_bram, where data can be executed as code. I don't care whether code and data share the same address space or not. Regards, MarcArticle: 112032
Anyone knows the I/O impedance on SPARTAN3 board ? I didn't find it in datasheet!Article: 112033
Ok, understand. Thanks, sharp. Cheng sharp@cadence.com schrieb: > uvbaz wrote: > > I've write a script for this, but with no control statement. How can i > > control the running flow, namely: > > > > if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING.... > > ncvlog and ncelab return an exit status, like many executables under > UNIX. I don't know about the other tools you mentioned. > > With csh, you can test this with something like > > ncvlog -f ncvlog.args > if ($status != 0) then > echo "ncvlog failed" > exit > endif > > Other UNIX shells may use different mechanisms, but they should all > provide access to the exit status.Article: 112034
Google ibis si <olive_dominguez@yahoo.fr> wrote in message news:1163583585.438860.301460@b28g2000cwb.googlegroups.com... > Anyone knows the I/O impedance on SPARTAN3 board ? I didn't find it in > datasheet! >Article: 112035
Hi ,
I am in the process of configuring a Block RAM in a Xilinx device
with some constants.
My implementation has some set of constants which are in a
separate module and i want to
intialize them in the RAM block. Inorder to do this i have
created a Coregen of a single port memory and initialized with a .coe
file, which was created using the memory editor. When i synthesized it
i didn't find any Block RAM used. What would be the error?
Article: 112036Thang Nguyen wrote: > Hi, > > I try to build a simple program to run on PowerPC, which is HelloWorld. When I compile, the error is: > > make: gcc: Command not found make: *** [PortLinux1/HelloWorld] Error 127 > > I checked the environment variables, which are XILINX_EDK, and Path. Everything is ok. I also did try to set a variable GNU_TOOLS to the gnu, but it still not work. > > Please tell me how to set variable to run the compile. gcc is a native compiler. You want to use powerpc-eabi-gcc. Try putting CC=powerpc-eabi-gcc in your makefile. Cheers, JonArticle: 112037
Thanks a lot backhus. I really appreaciate your effort. The information is helpful. Thanks again. Cheers!Article: 112038
olive_dominguez@yahoo.fr wrote: > Anyone knows the I/O impedance on SPARTAN3 board ? I didn't find it in > datasheet! The IO impedance of Spartan3 pins depends on the IO standard selected. As already noted, you can get the IBIS files which specify (in excruciating detail) the properties of the IO drivers. Cheers PeteSArticle: 112039
gen_vlsi wrote: > Hi , > > I am in the process of configuring a Block RAM in a Xilinx device > with some constants. > My implementation has some set of constants which are in a > separate module and i want to > intialize them in the RAM block. Inorder to do this i have > created a Coregen of a single port memory and initialized with a .coe > file, which was created using the memory editor. When i synthesized it > i didn't find any Block RAM used. What would be the error? I want to add to the above statements that when i remove the comment line // synopsys translate_off and // synopsys translate_on i get an error during synthesis. I have listed the following error. ERROR:HDLCompilers:87 - "D:/Xilinx/bin/nt/block_ram/constants.v" line 84 Could not find module/primitive 'BLKMEMSP_V6_1' ERROR: XST failedArticle: 112040
Hi, i am looking for someone who has tried Synopsys VCS under Windows environment, also if ever who has tried the built-in PCI-X verification.Article: 112041
Hi All: Could anyone point me where can I get an example of VCD file? Or you have one and willing to share? I need one to learn gkWave. Thanks. -ToddArticle: 112042
Keep in mind that those timing specs are only good to some sigma, probably three, which means that there are some (very very few) devices that get shipped that don't meet their timing. Xilinx warrants those devices with free replacments (labor not included!), provided you can prove that their part is not meeting its specs. My point is, you need to have a reasonable margin to cover those one-in-a-million parts, or you need to be prepared to replace them when they fail. Since you have two devices that fail, and one that does not, I don't think this is _your_ issue. I suspect that clock jitter is not being completely/correctly taken into account. However the issue of commercial component specifications is real, and leads to significant derating in high reliability applications (military, space, medical, etc.) Andy Ray Andraka wrote: > PeteS wrote: > > > > Now come, Austin. If the tool tells me I have positive margin (however > > small) I expect that to be true. I've done designs where I calculated > > the worst case and had a _guaranteed_ margin of 8 ps. Note the word > > guaranteed. I thought the post-PAR analysis tools gave me guaranteed > > timings. > > > > > > That is true provided you have a jitter-free clock. The tools do not > know, nor can they predict how much jitter is on your clock. You need > to consider a jitter margin in your clock constraints, as any jitter > erodes the minimum clock period. Keep in mind that you not only have > the jitter introduced by the DCMs if you use them, but also jitter > inherent in your clock source plus jitter added by noise on the board > and more importantly by modulation of the VCC-IOs of the clock pins by > other pins switching on the bank or by fluctuations in the power rails. > If you subtract your cycle-to-cycle max jitter from the clock > constraint, then you wind up with guaranteed operation. > > In a lab environment, you can usually get away with ignoring the jitter, > as you usually won't be anywhere near the slow corner of voltage, > process and temperature. In the field though, not allowing for > sufficient jitter tolerance is likely to come back and bite you hard in > the shorts.Article: 112043
gen_vlsi wrote: > Hi , > > I am in the process of configuring a Block RAM in a Xilinx device > with some constants. > My implementation has some set of constants which are in a > separate module and i want to > intialize them in the RAM block. Inorder to do this i have > created a Coregen of a single port memory and initialized with a .coe > file, which was created using the memory editor. When i synthesized it > i didn't find any Block RAM used. What would be the error? Do you actually *use* the memory yet or are you just seeing if it initializes before you actually wire up the access to the BlockRAM?Article: 112044
Are you making up statistics (probably 3 sigma) or do you actually have direct experience or documentation to back up this rather bizarre claim? I have trouble with engineers who decide "this is the way things are" without a shred of proof. I hear it almost daily. - John_H Andy wrote: > Keep in mind that those timing specs are only good to some sigma, > probably three, which means that there are some (very very few) devices > that get shipped that don't meet their timing. Xilinx warrants those > devices with free replacments (labor not included!), provided you can > prove that their part is not meeting its specs. My point is, you need > to have a reasonable margin to cover those one-in-a-million parts, or > you need to be prepared to replace them when they fail. > > Since you have two devices that fail, and one that does not, I don't > think this is _your_ issue. I suspect that clock jitter is not being > completely/correctly taken into account. However the issue of > commercial component specifications is real, and leads to significant > derating in high reliability applications (military, space, medical, > etc.) > > AndyArticle: 112045
PeteS a =E9crit : > olive_dominguez@yahoo.fr wrote: > > Anyone knows the I/O impedance on SPARTAN3 board ? I didn't find it in > > datasheet! > > The IO impedance of Spartan3 pins depends on the IO standard selected. > As already noted, you can get the IBIS files which specify (in > excruciating detail) the properties of the IO drivers. > > Cheers > > PeteS I have read IBIS files, my I/O is :LVCMOS25-S-12mA. What's the impedance of this I/O standard ? Thanks.Article: 112046
John_H wrote:
> Do you actually *use* the memory yet or are you just seeing if it
> initializes before you actually wire up the access to the BlockRAM?
Hi John,
It was a mistake on my side.I used the .v files generated by core
gen. When i replaced the .v by .xco files it worked. Now i have a doubt
of how to use the same for simulation. Can anyone give sugestions. I am
using NC Verilog for simulation.
Article: 112047
Hi Tim,
"Tim" <gueneysu@crypto.rub.de> wrote in message
news:1163411558.398429.235150@m73g2000cwd.googlegroups.com...
> I will probably use a latency clock to wait for the carry to become
> available at the P port for the computation of the next chunk with
> carry input from a fabric source. Unfortunately, this reduces my the
> overall performance but it seems to be the only solution to me when
> using cascaded adders.
This is indeed probably the easiest and most resource-efficient approach. It
will reduce the overall latency of an accumulation operation, as you say.
However it might be possible to take two additions and interleave them on
the same DSP48 hardware on alternate cycles. With a bit of care, that could
give you maximum computational throughput in spite of the reduction in
latency.
Good luck!
-Ben-
Article: 112048http://www.pericom.com/faq/faq_results.php?subject=54 <olive_dominguez@yahoo.fr> wrote in message news:1163602703.107474.265360@e3g2000cwe.googlegroups.com... PeteS a écrit : > olive_dominguez@yahoo.fr wrote: > > Anyone knows the I/O impedance on SPARTAN3 board ? I didn't find it in > > datasheet! > > The IO impedance of Spartan3 pins depends on the IO standard selected. > As already noted, you can get the IBIS files which specify (in > excruciating detail) the properties of the IO drivers. > > Cheers > > PeteS I have read IBIS files, my I/O is :LVCMOS25-S-12mA. What's the impedance of this I/O standard ? Thanks.Article: 112049
John, I, too, have a problem with people making assumptions about our product quality. If you are interested, we do publish what our criteria are, and the probability that a part is a test escape of some sort, or fails upon first insertion, etc. is something we do document, and care deeply about. http://www.xilinx.com/products/quality/ Obviously, we strive like most companies for a '0 defect' goal, and like all companies, we somehow are unable to ship only perfect components (funny how the real world conspires against perfection). Since every bitstream is different for each application, and we don't know any of them, it makes assuring 100% perfection a daunting task, yet one that we willingly accept and strive towards. In fact, if you really want a component that is absolutely best tested for exactly your bitstream (design), then you should be using the EasyPath(tm) program, as that program has a customer program for the FPGA that exercises the paths and logic that you actually are going to depend on (based on your design). Austin
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