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"jacko" <jackokring@gmail.com> schrieb im Newsbeitrag news:1159821019.648658.10730@m73g2000cwd.googlegroups.com... > > Antti wrote: >> jacko schrieb: >> >> > hi >> > >> > IO has been the thoughts of late. As all IO is from or to 1K x 16 bit >> > words memory mapped buffers certain limits are placed on the devices >> [] >> > what else would people require in terms of modular cores? >> > >> > cheers. >> >> you are not doing the things in right order IMHO >> >> 1) Arch description > > Read the ISA and look at the circuit this early in the project. > I have. plenty many unknowns processor states? special registers? interrupts? exceptions? addressing ranges for diferent address spaces? all only open questions! >> 2) HDL testbench or fixture > > this will be the FORTH ROM and a modified FORTH-83 test suite. > anything that contains 'will be' means nothing. it either is or is not available. >> 3) toolchain + assembler compiler tests > > The operation of the base vocabularies will depend quite a lot on the > utility to which the design will be put. > hm - sorry by toolchain I did mean C compiler of course. nobofy wants forth unfortunatly. yes, I have programmed in forth back then when 80286 based machines did come out. I have even developed a single chip based computer based on PIC16F84 where forth like interpreter and interactive monitor editor all was fitted into 512 word ROM. but - there are plenty of forth FPGA CPU's available, and there seems to ZERO interest. now Java VM is actually a forth engine, but guess what? Sun is not offering forth as front end for their forth enginge, no Java language is something totally different (the forth VM is hidden from the user) so unless you have a C compiler front end, there will be equally zero interest to your processor as it zero interest to other currently available forth FPGA CPU's. >> 4) onchip bus infrastructure > > it will be avalon or wishbone, when i end up needing to use the on chip > bus for a first product development. > >> >> only when the above is finalized then there the >> peripherals make sense, unless the cores >> is working verified and supported by tested >> software tools, the existance (or lack of) >> peripherals makes absolutly no difference. > > i like to see where i'm headed, as well as where i am due to the > direction to head in is controlled by the final destination. the > pheripheral IO is on the agenda at the moment as this will decide the > high level structure of the API. I could do things to an order, but i > see no pink slips paying the bills, so i'll have to run it the way i > see it in the eye of the mind. > your total earnings from the project are estimated to be <= 100USD you can take a pink piece of paper and write that number onto it. > i was thinking of a track loop phosphorus-arsnic NMR factorizer by > gussian sum, but not now, but it may relate to the HAL generics. > ?! Sorry Jon if I sound like fun-killer to you. I am just giving my 2 cents. cheers AnttiArticle: 109676
Hello, Try this: http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html MariuszArticle: 109677
When designing using a Virtex 4 (VCCO_0 = 3.3V) and a XCF16PV(VCCO=3.3V and VCCJ=3.3V) at MASTER-SERIAL connection the special configuration pins "DONE", "PROG-B" and "INIT" need pull-up resistors. At which voltage rail should they be pulled up to? At 3.3V or 2.5V? When using a THEVENING termination for the CCLK, at which voltage should it be pulled up? In all those cases what value should the resistors have? I have used 100 Ohm for the thevening termination, 330 Ohm for INIT and DONE and 4.7K for PROG-B. In the ML401-2-3 reference schematic 2.5V is used for pull-up but in the Platform Flash Configuration guide (DS123) it says that I should pull the up to VCCO_0 that is 3.3 V in my case and in ML401_2_3 case also. Please help me, I am cofused. Thank you in advance, Tasos.Article: 109678
Hi everybody, I'm a Ph.D. student on robotics and i'm *totally* new to the world of FPGA and i need little help understanding some (i think) standard procedures. I'm using a Xilinx Microblaze (32bit) microcontroller (with EDK) and i'm triyng to implement a special control algorithm for a robot. Now the problems. Since the FPGA are volatile devices, i need a PROM to configure them at start-up. 1) how do i fill the PROM? I know there are different section (configuration, SW, user Data) but how do I fill each such sections using xilinx tools? 2) since the program and the data are big, how can I relocate them to an external memory such as a RAM? I know that using an appropriate linker script I can do that but it's not so clear to me how all works. (Should the program fit in the internal RAM of FPGA or it can reside all or in part in external RAM? Using the linker script at start-up the code is automatically copied in the right portion of RAM?) As you can see I'm totally new to this world. I've read about this issues (xapp482, xapp501, ds123,...) but all the documents are too much specific, what I need now is an idea on how all this stuff works, just to understand the flow and the tools I need. I know that this issues are *well* known to most of you and maybe you'll find boring explain this basic things but I'll appreciate any hint you can gave me. Thanks in advance, Andrea.Article: 109679
cbr_929rr wrote: > If www.opencores.org link does not work, try > http://www.opencores.org:8080/ > The port number fixed my problems with connecting. Thanks, DerekArticle: 109680
Norbert Stuhrmann wrote: > Hi Derek, > > Derek Simmons wrote: > > I'm looking for any helpful or constructive suggestions. > > You might have a look at the cordic algorithms. > > Regards, > > Norbert Stuhrmann The cordic projects on OpenCores were hits I found searching for algorithms. Not that I'm able to connect, unless somebody recommends otherwise I'm going to focus my investigation and research on them. Thanks, DerekArticle: 109681
Antti Lukats wrote: > "jacko" <jackokring@gmail.com> schrieb im Newsbeitrag > news:1159821019.648658.10730@m73g2000cwd.googlegroups.com... > > > > Antti wrote: > >> jacko schrieb: > >> > >> > hi > >> > > >> > IO has been the thoughts of late. As all IO is from or to 1K x 16 bit > >> > words memory mapped buffers certain limits are placed on the devices > >> [] > >> > what else would people require in terms of modular cores? > >> > > >> > cheers. > >> > >> you are not doing the things in right order IMHO > >> > >> 1) Arch description > > > > Read the ISA and look at the circuit this early in the project. > > > > I have. > plenty many unknowns > processor states? 1 pin to select user or super mode registers. > special registers? none as yet > interrupts? no interrupt controller yet, would be part of the pheriph devices, which toggles user super register set. > exceptions? no none of this either. but may be detected by user logic to toggle super/user pin. > addressing ranges for diferent address spaces? 16 bit address (or 32 if two joined, or 64 if 4 joined) and 2 bits to indicate which address register is used, and a fetch pin to indicate insruction fetch cycle. > all only open questions! > > >> 2) HDL testbench or fixture > > > > this will be the FORTH ROM and a modified FORTH-83 test suite. > > > > anything that contains 'will be' means nothing. > it either is or is not available. not yet available, wordlist.mdb in the project directory is the current state of word defininitions and word documentation. > > >> 3) toolchain + assembler compiler tests > > > > The operation of the base vocabularies will depend quite a lot on the > > utility to which the design will be put. > > > > hm - sorry by toolchain I did mean C compiler of course. > nobofy wants forth unfortunatly. no C compiler yet, and java may be more likely. although of course the full sun library will not be supplied. > yes, I have programmed in forth back then when 80286 based machines > did come out. I have even developed a single chip based computer based > on PIC16F84 where forth like interpreter and interactive monitor editor > all was fitted into 512 word ROM. ok > but - there are plenty of forth FPGA CPU's available, and there seems > to ZERO interest. i'm interseted, so i will develop and release things as they become needed for the first project using the indi. > now Java VM is actually a forth engine, but guess what? Sun is not > offering forth as front end for their forth enginge, no Java language > is something totally different (the forth VM is hidden from the user) makes a good native language for java if you ask me, but then people love the C code base. although c to forth translator does exist. > so unless you have a C compiler front end, there will be equally > zero interest to your processor as it zero interest to other currently > available forth FPGA CPU's. the cpu is not necessarily forth, i'm just doing forth. it's a flat address space cpu which runs a machine code with 4 (source and dest = 2-operand) instructions. > >> 4) onchip bus infrastructure > > > > it will be avalon or wishbone, when i end up needing to use the on chip > > bus for a first product development. > > > >> <snip> > > > your total earnings from the project are estimated to be <= 100USD > you can take a pink piece of paper and write that number onto it. i think i will have to design my own project first. on which i aim to make mony, after first product design, much more will be available for a user base. > > i was thinking of a track loop phosphorus-arsnic NMR factorizer by > > gussian sum, but not now, but it may relate to the HAL generics. > > > ?! http://groups.google.co.uk/group/comp.theory/browse_thread/thread/e0c8d0641fa3c2cc/?hl=en# and NMR needs odd number of protons. > Sorry Jon if I sound like fun-killer to you. > I am just giving my 2 cents. ok. i can take constructive critisism, and i am sure C will be done by someone some day, as the instruction set is very simple to emulate. but it wont be me today, as i have other things in the pipeline, and out of order execution is not yet available within the indi design. biggest selling point is arround 700 LEs and uses no BRAM or other resources for microcode and the like. to use it as a 16 bit just join the caryy out to the carry in, and connect your own level based interrupt source to the super/user pin. user the address and data bus to connect to 64K x16 bit words of RAM. cheersArticle: 109682
Andrew FPGA wrote: > > >What I'm looking for is a resource like, if it existed, Numerical > > >Receipes in HDL (VHDL/Verilog). > > Elementary Functions, Algorithms and Implementation by Jean-Michel > Muller. > No HDL code but the algorithms are there. I found a couple of people have recommended this book and when I did a quick search on Amazon it came highly recommended. I'm looking into getting a copy. Thanks, DerekArticle: 109683
Anastasios D. Salis napisal(a): > When designing using a Virtex 4 (VCCO_0 = 3.3V) and a XCF16PV(VCCO=3.3V and VCCJ=3.3V) at MASTER-SERIAL connection the special configuration pins "DONE", "PROG-B" and "INIT" need pull-up resistors. At which voltage rail should they be pulled up to? At 3.3V or 2.5V? When using a THEVENING termination for the CCLK, at which voltage should it be pulled up? In all those cases what value should the resistors have? I have used 100 Ohm for the thevening termination, 330 Ohm for INIT and DONE and 4.7K for PROG-B. In the ML401-2-3 reference schematic 2.5V is used for pull-up but in the Platform Flash Configuration guide (DS123) it says that I should pull the up to VCCO_0 that is 3.3 V in my case and in ML401_2_3 case also. I've got the similar issue, but Slave SelectMAP32 from microprocessor, Vcco = 3,3V. I haven't found special solution for this configuration in V4, so I use configuration from Spartan3 user guide (ds099.pdf 3.3V-Tolerant Configuration Interface). > > Please help me, I am cofused. I'm confused too :) Regards Jerzy GburArticle: 109684
> > It really depends on your precision and accuracy requirements. For > arbitrarily high precision, CORDIC is the way to go for sin provided you > can live with the latency. The other end of the spectrum is a look-up > table. There are intermediate solutions which are generally a > combination of angular reductions and interpolation that will get you a > reasonably high resolution without a huge look-up table. Linear > interpolation perhaps the easiest, and can be done with relatively > little hardware. A parabolic fit interpolation will get you > considerably smaller errors between table entries allowing a finer > resolution, and can be done with relatively low hardware complexity. I can live with the latency because the math unit I'm designing is pipelined. As long as I organize the operations putting the ones with longest latency first and at the cost of a multiplier or adder I should keep a couple of parallel tracks busy. > > For X**Y, it is easiest to work with normalized floating point as an > input, and then using interpolated LUTs. Normalizing limits the range > of the tables. For a general purpose trancendental function calculator, > your best bet might be a CORDIC-like iterative engine, as CORDIC and > CORDIC-like structures can handle trig, hyperbolic trig, logs and > exponents, and multiply and divide. > I'm comparing the trade off for using a lookup table to using an iterative process. I have designed a general purpose rasterizer. I can feed it a canned list of triangles in screen coordinates and it can render them shaded. I'm working my way backwards up the pipeline to design the geometry engine stage. Given the parameters for viewing transformations I'm adding the functionality to build the viewing transforms, using the object space coordinates calculate the world space coordinates and from the worldspace coordinates calculate the screen coordinates for the rasterizer. Right now I'm doing this with the attitude of a hobby but I would like to roll it over into something professional. Much of what I'm doing is iterative, it never amazes me when QuartusII finds a flaw in one of my state machines and decides to flatten it. Thanks, DerekArticle: 109685
Hi group I'm a newbee, so please bear with me if this does not make sense. I got a AVNet (MEMEC) Virtex 4 based developper kit based on the Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as "a 2.5V compatible JTAG chain header". The pinout is identical to what Xilinx seems to use (14 pins etc.). The docs seem to asume that one must use the Xilinx parallel cable IV which from what I understand seems to automatically sense the voltage needs of the target and is having other nice to have features. However, due to several reasons which are beond the scope of this post, I can't simply pick up the phone and order one from a supplier last not least also because I don't know any that would carry this item here in Switzerland. The net seems to be full of homebrew JTAG cable websites giving instructions to build you own. The question is can I use one of those? I'm a bit afraid that this will not work cause from what I understand they seem to be designed for 5V or 5V tolerant devices. What other options do I have? Any links to a schema of the Xilinx paralell cable IV or such to build my own JTAG cable running at 2.5V? I would also not mind to shell out the needed $$$ to get that original cable if I could easily purchase it somewhere online using paypal or a credit card and get it deliverd quickly. Any ideas? TIA MarkusArticle: 109686
Hi Andrea,
> I'm a Ph.D. student on robotics and i'm *totally* new to the world of
> FPGA
Welcome to the world of FPGA! Don't panic, you are very close to getting
where you want to go. All the questions you have asked are valid and
sensible.
> and i need little help understanding some (i think)
> standard procedures.
In fact, as you no doubt suspected all along, there aren't really any
hard-and-fast "standard procedures" for what you're interested in doing.
There are various standard techniques and approaches, but no One Right Way.
The specifics really vary from project to project.
You have correctly identified that the FPGA needs to be configured somehow -
this can be from a special PROM, or some other method, but ultimately the
FPGA image must be stored in non-volatile memory somewhere. Note that this
might be - but certainly doesn't have to be - the same non-volatile memory
that contains the application program code for your control algorithm.
> 1) how do i fill the PROM?
This will depend quite a lot on your board. Are you using a standard
development board (i.e. off-the-shelf from Xilinx, Avnet etc) or is it a
custom-built piece of robotics kit? Generally speaking the process of
formatting and downloading the PROM image will differ quite a lot from board
to board.
> 2) since the program and the data are big, how can I relocate them to
> an external memory such as a RAM?
So, if your application can be made to fit entirely within the block RAM
resources inside the FPGA, then there is no need for any separate external
application code: the FPGA will start running your program as soon as it's
configured. If it's bigger than that, then some sort of "bootloader" program
is required. This will sit in a lump of BRAM and will be run as soon as the
FPGA has configured. In the simplest case it would just jump directly to the
location where the program is stored in external non-volatile memory;
however, this is often quite slow. If there is SRAM or DRAM available, the
bootloader can copy the program from non-volatile storage into faster
volatile memory, and then execute it from there. It might also do some other
things like clearing some region of memory, for example.
Of course, if your program is bigger than your non-volatile storage, then
you can't really do much other than download it manually into SRAM/DRAM each
time. Or get your bootloader to download the application over ethernet or
something complicated like that.
Last time I did anything like this (which was a while ago), I had to write
the bootloader myself. It's not very hard, and there is usually an existing
reference point to start from. For some common cases and on "supported"
development boards, the EDK may now automate this (perhaps someone more
familiar with that side of things can fill in the blanks here).
The linker script merely tells the linker what memory address each section
of the compiled program should live in. This information is propagated into
the .elf file and can be used by bootloader-type applications, but the
linker script itself doesn't really play a part in the bootloading process.
Hope something in all this waffle is useful. I'm sure you will find plenty
of people on this newsgroup with helpful advice. You might also try
comp.arch.embedded for any issues that are more processor-related than
FPGA-related.
Good luck!
Cheers,
-Ben-
Article: 109687Markus Our Prog2 cable(ask for narrow head version) is available in the standard 14 way 2mm connector. Cost GBP£10. It is a Cable III look-alike as most third party cables are. Schematics for Cable IV are generally not in public domain and generally not replicated by anyone as far as I know. The only advantage of the Cable IV is the download speed. Our shop website has those listed under programming solutions for an easy order solution. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Markus Zingg" <m.zingg@nct.ch> wrote in message news:ahn4i25ir1pnpqbol22na85ggkrjeoam3m@4ax.com... > Hi group > > I'm a newbee, so please bear with me if this does not make sense. > > I got a AVNet (MEMEC) Virtex 4 based developper kit based on the > Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as > "a 2.5V compatible JTAG chain header". The pinout is identical to what > Xilinx seems to use (14 pins etc.). The docs seem to asume that one > must use the Xilinx parallel cable IV which from what I understand > seems to automatically sense the voltage needs of the target and is > having other nice to have features. However, due to several reasons > which are beond the scope of this post, I can't simply pick up the > phone and order one from a supplier last not least also because I > don't know any that would carry this item here in Switzerland. > > The net seems to be full of homebrew JTAG cable websites giving > instructions to build you own. The question is can I use one of those? > I'm a bit afraid that this will not work cause from what I understand > they seem to be designed for 5V or 5V tolerant devices. What other > options do I have? Any links to a schema of the Xilinx paralell cable > IV or such to build my own JTAG cable running at 2.5V? > > I would also not mind to shell out the needed $$$ to get that original > cable if I could easily purchase it somewhere online using paypal or a > credit card and get it deliverd quickly. Any ideas? > > TIA > > Markus >Article: 109688
I don't see where the "Parallel Cable III look-alike" PROG2 is 2.5V compliant since the Parallel Cable III doesn't work so well from 2.5V. I think I've gotten the III to work with a 3.3V supply for 2.5V JTAG but the IV or USB versions of the cable are certainly more robust. Perhaps the Xilinx online store could ship to Switzerland with a simple credit card purchase. The Parallel Cable IV doesn't include schematics but it does show what the input and output stages look like, easily replacing the simple buffers in the Parallel Cable III which does have full schematics. - John Handwork John Adair wrote: > Markus > > Our Prog2 cable(ask for narrow head version) is available in the standard 14 > way 2mm connector. Cost GBP£10. It is a Cable III look-alike as most third > party cables are. Schematics for Cable IV are generally not in public domain > and generally not replicated by anyone as far as I know. > > The only advantage of the Cable IV is the download speed. > > Our shop website has those listed under programming solutions for an easy > order solution. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > "Markus Zingg" <m.zingg@nct.ch> wrote in message > news:ahn4i25ir1pnpqbol22na85ggkrjeoam3m@4ax.com... >> Hi group >> >> I'm a newbee, so please bear with me if this does not make sense. >> >> I got a AVNet (MEMEC) Virtex 4 based developper kit based on the >> Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as >> "a 2.5V compatible JTAG chain header". The pinout is identical to what >> Xilinx seems to use (14 pins etc.). The docs seem to asume that one >> must use the Xilinx parallel cable IV which from what I understand >> seems to automatically sense the voltage needs of the target and is >> having other nice to have features. However, due to several reasons >> which are beond the scope of this post, I can't simply pick up the >> phone and order one from a supplier last not least also because I >> don't know any that would carry this item here in Switzerland. >> >> The net seems to be full of homebrew JTAG cable websites giving >> instructions to build you own. The question is can I use one of those? >> I'm a bit afraid that this will not work cause from what I understand >> they seem to be designed for 5V or 5V tolerant devices. What other >> options do I have? Any links to a schema of the Xilinx paralell cable >> IV or such to build my own JTAG cable running at 2.5V? >> >> I would also not mind to shell out the needed $$$ to get that original >> cable if I could easily purchase it somewhere online using paypal or a >> credit card and get it deliverd quickly. Any ideas? >> >> TIA >> >> MarkusArticle: 109689
Any body has updates on this???? Ashish wrote: > I have a problem in initiating a PLB _IPIF back to back transactions. > > I have integrated my IP backend with PLB-IPIF. > > My IP is User master while initiating transaction and then completes > the transaction as slave, on IPIF side. > > Once I am done with Write transaction initiated on PLB bus from IP > Master interface(through IPIF) and after receiving last_ack, I am > initiating another write transaction, but its fails to respond! > > The status after 1st write transaction is that Bus2IP_BE shows 80h and > Bus2IP_CE shows IP master chp enable asserted. What does it mean? > > I found nothing related to this in PLB_IPIF_V2_01.pdf > > Can anybody help me out in understanding the disconnects?Article: 109690
Jon Beniston schrieb: > Hal Murray wrote: > > >on LM32 all memories are on Wishbone bus making the access to BRAM > > >based memory block slower than the access to external memory (assuming > > >cache hit). > > > > Can you cheat and build a system with cache and no memory, then > > preload the cache with the data you want? > > As far as I can see, I don't think this is supported via the GUI yet, > but would of course be possible if you hacked the RTL to change the > cache memories and tags to be initialised with the correct data, which > should be fairly straightforward to do. > > However, this would not be as efficient as using the instruction ROM > and data RAM that are in the RTL, as you end up wasting resources on > memories for the cache tag RAMs which aren't needed, and all of the > cache refill logic etc.. > > Cheers, > Jon hm, I guess the LM32_RAM that is included when JTAG debugger is enabled is direct processor connected block RAM. as I had JTAG configured off this module was also out, so I only had wishbone block RAMs left in the system. For the custom instruction support there is anyway an update needed so I guess the access to direct CPU connected on chip memories will also be available then. Antti PS for those who want to play with LatticeMico32 on Xilinx platform I uploaded the ISE project navigator project that I used for testing, its rather minimal LM32 system tested to work in Virtex-4, available @ www.microfpga.com , download area...Article: 109691
Hi all, I'm about to convert the amplitude output from a Cordic to dB, 20*log(amp) that is. The output from the Cordic is 24 bits wide, the maximum value would thus be approximately 144.5 dB. It is sufficient with 12 bits resolution on the logarithm, 8 integer bits and 4 fractional bits. My idea is to create a look-up table out of BRAM in the FPGA, and since I want 12 bits resolution the size should not be larger than 2312 words (the largest value is 10010000.0111 which is equal to 2311 if the binary point is removed) each 12 bits wide. The problem has proved to be to create a clever address function though. Any thoughts or ideas I have forseen? I'm sure this has been done before, but some Googling didn't really help me in the right direction. Regards -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 109692
Thank you Ben! now I've a little clearer vision on how the things works, I found useful your answer to point two. Just few things are still not clear. Herein I'll refer to the Xilinx world: EDK, Microblaze as microprocessor, XC2v1000 as FPGA and XC18V04 as ISP PROM. Using EDK everything is easy because only pressing a button on the GUI it's possible to syshthetize the design, place&route, ... , download (using iImpact?) in the PROM. Then only pressing a button on the board, the FPGA is configured and everything works fine. Thinking on the section on a PROM (configuration, SW, User Data), I wonder how these sections are filled. The definition of the "HW" (microprocessor + peripherals) is in the configuration section? The program that I coded in C is in the SW section? The variables/constants I declared in the code are in the User Data Section? I think not... There is a way to exploit these sections (and an external volatile memory) to reduce the size of the FPGA I need for my application? I believe there is a way to use the FPGA resource almost only for the "HW" and to use other external devices for storing data/program. I'm still a little bit confused... Do you know some good site/book/document that can help me? thanks, AndreaArticle: 109693
Isn't the largest (scaled) value 1.111111111111? Logs are typically performed first with a shift until the MSbit of the scaled value is 1. The amount of shift is the log2 integer portion. The remaining bits are then used for the lookup to produce the fractional portion of the log2. If you need log10 or ln, you can multiply the complete log2 result (integer plus fractional) by 1/log2(10) or 1/log2(e), respectively. - John_H "Johan Bernspång" <xjohbex@xfoix.se> wrote in message news:efu25p$n17$1@mercur.foi.se... > Hi all, > > I'm about to convert the amplitude output from a Cordic to dB, 20*log(amp) > that is. The output from the Cordic is 24 bits wide, the maximum value > would thus be approximately 144.5 dB. It is sufficient with 12 bits > resolution on the logarithm, 8 integer bits and 4 fractional bits. > > My idea is to create a look-up table out of BRAM in the FPGA, and since I > want 12 bits resolution the size should not be larger than 2312 words (the > largest value is 10010000.0111 which is equal to 2311 if the binary point > is removed) each 12 bits wide. The problem has proved to be to create a > clever address function though. > > Any thoughts or ideas I have forseen? I'm sure this has been done before, > but some Googling didn't really help me in the right direction. > > Regards > -- > ----------------------------------------------- > Johan Bernspång, xjohbex@xfoix.se > Research engineer > > Swedish Defence Research Agency - FOI > Division of Command & Control Systems > Department of Electronic Warfare Systems > > www.foi.se > > Please remove the x's in the email address if > replying to me personally. > -----------------------------------------------Article: 109694
Hi, I have a project that have many files generated by Xilinx CoreGenerator. Now I put all those vhdl files generated by Xilinx CoreGenerator into my project. I want to put those files that never change into a library monitored by ModelSim software. I don't know how to create a ModelSim library. Please help. Thank you. WengArticle: 109695
Thomas Entner schrieb: > Hi Antti, > > have you any idea why it is that slow? Branch penalty? Or is the write that > slow? Does the performance improve with caches on? (I have not looked > closely at Mico32 yet, maybe it is intended to only be used with caches?) > > Regarding the GPL: I think it is sufficient if they clearly say that the > softare is GPL-licensed and if they provide you the source-code on request. > So they would be only violating the license if you ask them to provide you > the source-code and they say "No". Once you have the source-code, you are > free to publish it yourself on a web side (I am sure, you will ;-) > > Thomas > > www.entner-electronics.com > http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&sloc=01-01-08-11-48 LatticeMico32 GPL sources no need to ask, just get it. AnttiArticle: 109696
I'm seeing some unexpected behavior when using the Xilinx TNM constraint in a ucf file. I'm using the 8.2.03 version of the s/w. I have several groups of signals that cross clock domains. Normally, I've used the following and it works OK: TIMESPEC "ts_os_x3a" = FROM FFS(u_os_if/rd_burst) to FFS(upo_joey_if/xmit_data<*>) = 12; TIMESPEC "ts_os_x3b" = FROM FFS(u_fx2if/reg_brst_rd) to FFS(upo_joey_if/xmit_data<*>) = 12; I then tried: NET "u_os_if/rd_burst" TNM = x_rio_tx; NET "u_fx2if/reg_brst_rd" TNM = x_rio_tx; TIMESPEC "ts_os_x3" = FROM x_rio_tx to FFS(upo_joey_if/xmit_data<*>) = 12; and I was VERY surprised at the result. Instead of applying the constraint from the rd_burst and reg_brst_rd signals to the xmit_data<*> signals, it instead constrained a path from xmit_data<8> to xmit_data<15>. Is this yet another Xilinx bug or am I mis-using the TNM constraint? Thanks! John ProvidenzaArticle: 109697
You have a 'gmail' address; surely you have heard of Google? Google search for "modelsim create library". The link you want is the 2nd one.Article: 109698
vlib my_cores vlog -work my_cores core0.v HTH, Jim http://home.comcast.net/~jimwu88/tools/ Weng Tianxiang wrote: > Hi, > I have a project that have many files generated by Xilinx > CoreGenerator. > > Now I put all those vhdl files generated by Xilinx CoreGenerator into > my project. > > I want to put those files that never change into a library monitored by > ModelSim software. > > I don't know how to create a ModelSim library. > > Please help. > > Thank you. > > WengArticle: 109699
jacko wrote: > > ok. i can take constructive critisism, and i am sure C will be done by > someone some day, as the instruction set is very simple to emulate. but > it wont be me today, as i have other things in the pipeline, and out of > order execution is not yet available within the indi design. > > biggest selling point is arround 700 LEs and uses no BRAM or other > resources for microcode and the like. to use it as a 16 bit just join > the caryy out to the carry in, and connect your own level based > interrupt source to the super/user pin. user the address and data bus > to connect to 64K x16 bit words of RAM. and also the CAIN has to be connect to vcc to make address generation post pre inc/dec work, and the CAOUT can be chained to multiple indi16s to get 32 48 and 64 bit. when using 32, 48 or 64 the fetch signal can be used to direct the program opcode into all indi16 cpu units. any questions?? > > cheers
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