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Frank Buss wrote:
> Jim Granville wrote:
>
>
>>One stack machine, that is still small, but could help greatly with
>>software flows (being an already defined std)
>>is the Instruction List language of IEC 61131-1
>>
>>http://www.3s-software.com/index.shtml?CoDeSys_IL
>>
>>and
>>
>>http://en.wikipedia.org/wiki/Instruction_list
>
>
> This looks very interesting, because every command has only one operand,
> which make developing the core really easy and leaves much space for
> addressing modes etc. in an opcode, even with 8 bit opcodes.
>
> I'll try to mix this with my last addressing modes. I don't need "call",
> because this is only a jump, where the return address is stored somewhere
> (I don't need recursion).
>
> 4 bits: instruction
> lda: load accu
> sta: store accu
> or: accu = accu or argument
> xor: "
> and: "
> add: "
> sub: "
> cmp: "
> bcc: branch if carry clear
> bcs: branch if carry set
> bne: branch if zero set
> beq: branch if zero clear
> jmp: jump
> inp: read from port or special register (pc, flags, i/o ports, timer etc.)
> outp: write to port or special register
>
> I don't need it, but the last possible instruction could be rti, return
> from interrupt, which restores pc, accu and the flags, which are saved on
> interrupt entry. With inp/outp the interrupt address and frequency could be
> setup.
>
> 4 bits: address mode (pc relative, 16 bit argument, doesn't make much
> sense, so all useful combinations fits in 4 bits)
>
> immediate, 8 bit argument
> immediate, 16 bit argument
> immediate, no arguments, #0
> immediate, no arguments, #1
>
> 8 bit transfer width:
> address, 8 bit argument
> address, 16 bit argument
> address, pc relative, 8 bit argument
> address indirect, 8 bit argument
> address indirect, 16 bit argument
> address indirect, pc relative, 8 bit argument
>
> 16 bit transfer width:
> address, 8 bit argument
> address, 16 bit argument
> address, pc relative, 8 bit argument
> address indirect, 8 bit argument
> address indirect, 16 bit argument
> address indirect, pc relative, 8 bit argument
>
> The "pc relative" address modes adds the argument to the pc to get the
> value. This can be used for the branches and jumps for short jumps, but as
> well for using some kind of local variables. Let's try the swap algorithm:
>
> ; swap 6 byte source and destination MACs
> p1: .dw 0
> p2: .dw 0
> tmp: .db 0
> lda #5
> sta p1 (pc relative)
> lda #11
> sta p2 (pc relative)
> loop: lda (p1) (address indirect, pc relative)
> sta tmp (address, pc relative)
> lda (p2) (address indirect, pc relative)
> sta (p1) (address indirect, pc relative)
> lda tmp (address, pc relative)
> sta (p2) (address indirect, pc relative)
> lda p2 (pc relative)
> sub #1 (one byte, because #1 needs no operand)
> sta p2 (pc relative)
> lda p1 (pc relative)
> sub #1 (one byte, because #1 needs no operand)
> sta p1 (pc relative)
> bcc loop (pc relative)
>
> 37 bytes
>
> This is not as good as my RISC idea (20 bytes), but the code is much better
> to understand: you need not to think about it when reading and writing it.
> But maybe this is only because some ages ago I've written some demos and
> intros on C64 (6502), which uses a similiar instruction set :-)
>
> Do you think the core for this design would be smaller than PicoBlaze or my
> RISC idea?
The core can certainly be made very small, it depends on the datatypes
you decide to support. - I've been looking at the very similar, but
venerable MC14500 ICU into CPLDs ( effectvely IL with only Boolean type )
Note that the IL syntax allows brackets, and I think has an implicit
stack; a bit like reverse-polish calculators
- see this example I got from the web :
Example IL code, from the net ( derived from a ladder diagram ) :
Read as O:001/00 = I:000/00 AND ( I:000/01 OR ( I:000/02 AND NOT I:000/03) )
Label Opcode Operand Comment
START:
LD %I:000/00 (* Load input bit 00 *)
AND( %I:000/01 (* Start a branch and load input bit 01 OR(
%I:000/02 (* Load input bit 02 *) ANDN %I:000/03 (* Load
input bit 03 and invert *)
)
)
ST %O:001/00 (* SET the output bit 00 *)
With the implicit stack, your swap becomes
LD VarNameA
LD VarNameB
ST VarNameA
ST VarNameB
This also makes the assembler a little more complex, as it needs to
re-order, and be bracket aware, before final-code-generate :)
> BTW: There are some nice contructs possible for smaller code, like to use
> some kind of zero-page, like implemented in the 6502, because the lda/sta
> instructions could be used with 8 bit arguments addresses. But code size
> and speed is not so important for me, a small core is more important, and
> maybe easy to write assembler code, to avoid implementing a GCC backend for
> my CPU.
Another good reference site I've found, is this
http://www.tracemode.com/products/dev/
they offer a free ( 117MB ) version, I have not got the time to look at
yet.
Something like this, should (hopefully) allow simulation and
development of IL code, as the software aspects of this will be the key
elements.
If you can keep to a defined type/operator subset of IL, then this
should also be somewhat portable.
I did see that some of their IL examples, suggest two operands, but the
standards docs I have here, do not mention that ?
It could be that two operands simply does an implicit load of the first
one, and is done to make the code slightly more readable.
-jg
Article: 106951
Hi,
One thing that looks a little suspect -
the lines:
TMPOUT = DIN >> SHIFTp;
DOUT = TMPOUT[15:0];
are inside the always statement - and as shiftP is on the right hand
side, it should be in the sensitivity list.
I think moving these two lines outside, and making them assign
statements will get rid of your synthesis warning - as to what logic is
actually being produced - hard to say! but I'd imagne that this
construct would make behavioural different from post synthesis in
simulation.
Hope this helps,
Cheers
John
Daniel O'Connor wrote:
> KJ wrote:
>
> > Daniel O'Connor wrote:
> > Many times this symptom is a result of a timing violation. Check that
> > the setup time and the clock frequency as reported by the place and
> > route timing report is being met by whatever simulation model you have
> > driving the design.
>
> Yup, the requirements at the basic level are fairly modest, and my timing
> constraints are being met.
>
> > Also, check the list of warnings that pop out of the synthesis to look
> > for things that you shouldn't try to do in an FPGA. If you find them,
> > you'll probably need to get rid of them. Things like...
> > - Transparent latches
> > - Generating your own internal clocks (can be done, but only with
> > care).
>
> I need to generate an internal clock :(
> Any tips on how to do it properly?
> Hmm actually I can rejig the design to use an enable which is probably the
> right thing to do.
>
> > - Other warnings that pop out should also be perused to make sure you
> > understand why it is a warning and if this is a concern in your design.
> > As with software, many times a compile time warning is a run time (or
> > in your case timing simulation) error.
>
> I have had an odd one which does not appear affect the final result - I have
> a right shifter with a lookup table in front (for compatibility reasons) so
> I do..
> module shifter(DIN, SHIFT, DOUT);
> output [15:0] DOUT; // Data out
>
> input [31:0] DIN; // Data in
> input [3:0] SHIFT; // Amount to shift by (sort of)
>
> reg [15:0] DOUT;
> reg [31:0] TMPOUT;
> reg [3:0] SHIFTp;
>
> always @(DIN or SHIFT) begin
> case (SHIFT)
> 4'd13: // 8192 integrations (not possible in the old SA)
> SHIFTp = 13;
> 4'd14: // 16384 integrations (not possible in the old SA)
> SHIFTp = 14;
> 4'd15: // 32768 integrations (not possible in the old SA)
> SHIFTp = 15;
> 4'd12: // 0/1 integrations
> SHIFTp = 0;
> 4'd11: // 2 integrations
> SHIFTp = 1;
> [...]
> endcase // case(SHIFT)
>
> TMPOUT = DIN >> SHIFTp;
> DOUT = TMPOUT[15:0];
> end // always @ (DIN or SHIFT)
> endmodule // shifter
>
> This synthesises to a ROM table and a shifter which is what I want. However
> xst warns me that SHIFTp and TMPOUT are assigned but never used. I presume
> that it optimised them away or something.
>
> It also complains that SHIFTp is not in the sensitivity list of the always
> block.. Seems rather odd to me..
>
> >> Strangely I find that the results are fine but the final FIFO is either
> >> not clocking the data in properly, or not clocking it out properly..
> >>
> > This might be a clue as to where timing is being violated. Since this
> > was from an 'old' board I'm guessing that the FIFOs there were the
> > garden variety async FIFOs. Hopefully inside the FPGA you didn't try
> > to implement that but used a standard synchronous type instead.
>
> Yes they're async - IDT 720x.
>
> I am using the async FIFO core from Xilinx's coregen (and an ALU).
>
> >> However if I test it in isolation it works fine.
> > When you're testing it in isolation though I'll bet that the timing in
> > and out of the FIFO is not really the same as it is when inside the
> > full FPGA. When testing in isolation, if you were to apply stimulus at
> > the exact same time to this isolated FIFO it would not work in the same
> > manner as you're seeing it not work for you now.
>
> Hmm OK..
> What a pain :)
>
> > If it is a synchronous FIFO then are the clocks free running or gated?
> > If gated, then how that gating logic is implemented could be the
> > problem (once again though, this is just a manifestation of a timing
> > failure which can also be caught by full static timing analysis).
>
> It is an async core, although the clock signal is not free running, it is
> generated off the card by a PLD which is gating another clock.
> Unfortunately I can't change that aspect :(
>
> Based on my reading of the datasheet I don't think that is a problem as such
> because the only problem I would have is that the flags won't get updated,
> but this design does not use them.
>
> >> I have applied some basic timing constraints, and when looking at the
> >> resulting timing diagrams it seems that there is plenty of time for the
> >> data to be valid on the input side of the final FIFO before the write
> >> clock is applied.
> >
> > What about all the timing inside of the device though? What is the
> > timing report telling you there? If there are multiple clocks involved
> > then moving data from one clock domain to the other needs to be done
> > properly.
>
> The thing is that the "clocks" aren't free running at all, they're all
> derived from the same base clock and gated with a PLD (or 3) and then piped
> down the backplane to the card I am designing.
>
> So I think in practise I am not actually going from one clock domain to
> another..
>
> I captured some sample signal information and have been using that as my
> test suite. In it, the control signals for the final FIFO where I am seeing
> the problem the data is clocked in and then clocked out later - at no time
> are both sides of the FIFO being clocked..
>
> I'm about to see if there is a way to peer inside the FIFO black box so I
> can tell if it's the read or write side that is at issue.
>
> Thanks for your reply!
>
> --
> Daniel O'Connor software and network engineer
> for Genesis Software - http://www.gsoft.com.au
> "The nice thing about standards is that there
> are so many of them to choose from."
> -- Andrew Tanenbaum
> GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C
Article: 106952hi i am looking for any step by step guide to use uclinux on the starter kit. i try the site: http://muranaka.info/pukiwiki/pukiwiki.php?MicroBlaze%20uClinux%20and%20Spartan-3E%20Starter%20Kit#content_1_0 but i didnt find anything in english or spanish. just japanese. thanks you DavidArticle: 106953
polkid@gmail.com wrote: > Okay here's my problem, > > My company got a dev board from Avnet with a Xilinx Virtex 4 FX12 FPGA > on it. > > So Xilinx sends us ISE 8.2i to use per our lisense. > > Avnet sends us EDK 8.1i to use. > > They won't work together! I get an error everytime I try to start up > either XPS or EDK. Avnet says they sent me the most up to date version > of the software that they have, and to download EDK 8.2i from the > Xilinx website, but I can't find anywhere on their website to acutally > download it! > > Any suggestions? You should be able to download ISE 8.1i from the xilinx web site. Its either that or wait for EDK 8.2i to come out. -JeffArticle: 106954
"Jeff Cunningham" <jcc@sover.net> schrieb im Newsbeitrag news:44ebc099$0$15483$4d3efbfe@news.sover.net... > polkid@gmail.com wrote: >> Okay here's my problem, >> >> My company got a dev board from Avnet with a Xilinx Virtex 4 FX12 FPGA >> on it. >> >> So Xilinx sends us ISE 8.2i to use per our lisense. >> >> Avnet sends us EDK 8.1i to use. >> >> They won't work together! I get an error everytime I try to start up >> either XPS or EDK. Avnet says they sent me the most up to date version >> of the software that they have, and to download EDK 8.2i from the >> Xilinx website, but I can't find anywhere on their website to acutally >> download it! >> >> Any suggestions? > > You should be able to download ISE 8.1i from the xilinx web site. Its > either that or wait for EDK 8.2i to come out. > -Jeff EDK 8.2 and EDK 8.2 SP1 ar both out since yesterday AnttiArticle: 106955
"David" <aresolimpico@gmail.com> schrieb im Newsbeitrag news:1156300564.875777.302880@i42g2000cwa.googlegroups.com... > hi > i am looking for any step by step guide to use uclinux on the starter > kit. > i try the site: > http://muranaka.info/pukiwiki/pukiwiki.php?MicroBlaze%20uClinux%20and%20Spartan-3E%20Starter%20Kit#content_1_0 > but i didnt find anything in english or spanish. just japanese. > thanks you > David > hm checked the images from that site in XSIM and they work just fine. I dont have the boards so can not test in hardware but I assume they will defenetly work as well anttiArticle: 106956
Serious question: Does Altera's PLL's offer an advantage (veratility, jitter, etc) over Xilinx's DCM's? I'm to understand that the DCM is not a PLL, correct? What is the working principal behind the DCM (any literature links?) This question arises from an upcoming design where we have three serial LVDS interfaces that need to go into a V2PRO part. I implemented this interface within an Altera Stratix part without a problem; but I'm told by the group responsible for the V2PRO design that their FPGA doesn't have the resources to handle the aforementioned interface, which will necessitate putting deserializers on the board at an added cost. Here's some information on the LVDS interface: Each interface has its own clock and 3 serialized lanes, for a total of 3 clocks (45MHz) and 9 x 7 deep (315MHz fast clock) serialized lanes. Much obliged, RobArticle: 106957
Rob wrote: > Serious question: Does Altera's PLL's offer an advantage (veratility, > jitter, etc) over Xilinx's DCM's? I'm to understand that the DCM is not a > PLL, correct? What is the working principal behind the DCM (any literature > links?) > > This question arises from an upcoming design where we have three serial LVDS > interfaces that need to go into a V2PRO part. I implemented this interface > within an Altera Stratix part without a problem; but I'm told by the group > responsible for the V2PRO design that their FPGA doesn't have the resources > to handle the aforementioned interface, which will necessitate putting > deserializers on the board at an added cost. > > Here's some information on the LVDS interface: > Each interface has its own clock and 3 serialized lanes, for a total of 3 > clocks (45MHz) and 9 x 7 deep (315MHz fast clock) serialized lanes. > > Much obliged, > Rob The Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet pages 61-64 go into little detail about the DCM compared to the Virtex-II Pro and Virtex-II Pro X FPGA User Guide pages 89-121 which goes into great detail about working with the DCM. Neither document seems to illustrate the tapped delay-line structure at the root of the "Delay Locked Loop" like those found in so many devices these days (such as DDR memories). There might be a better description deeper into the text than I cared to review. A Phase Locked Loop will tend to give much better phase noise. The DLL reacts *immediately* to an input phase change, where the PLL doesn't. There are advantages and disadvantages to each. External Serializer/Deserializers are not necessarily your best option. Instead consider using a clock generator capable of reasonably clean 315 MHz generation such as the IDT5V9885 (good to 550 MHz). You might get the performance you need. - John_HArticle: 106958
I am write Veriuser=3D $LMC_HOME/lib/pcnt.lib/swiftpli_mti.dll after line
; List of dynamically loaded objects for Verilog PLI applications in
fime modelsim.ini but this line deteted automatically.
Question : That line comment or not comment?
Jim Wu =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):
> Have you checked AR 22214?
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=3Dyes&getPa=
gePath=3D22214
>
>
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
>
> axalay@gmail.com wrote:
> > Modelsim report is:
> >
> > # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
> > # // ModelSim SE 6.1b Sep 8 2005
> > # //
> > # // Copyright Mentor Graphics Corporation 2005
> > # // All Rights Reserved.
> > # //
> > # // THIS WORK CONTAINS TRADE SECRET AND
> > # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
> > # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
> > # // AND IS SUBJECT TO LICENSE TERMS.
> > # //
> > # do {test_clock.fdo}
> > # ** Warning: (vlib-34) Library already exists at "work".
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > # -- Compiling module stm4ser
> > #
> > # Top level modules:
> > # stm4ser
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > # -- Compiling module dcm1
> > #
> > # Top level modules:
> > # dcm1
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > # -- Compiling module clock
> > #
> > # Top level modules:
> > # clock
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > # -- Compiling module test_clock
> > #
> > # Top level modules:
> > # test_clock
> > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > # -- Compiling module glbl
> > #
> > # Top level modules:
> > # glbl
> > # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock
> > glbl
> > # Loading work.test_clock
> > # Loading work.clock
> > # Loading work.dcm1
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_check
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost
> > # Loading work.stm4ser
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT
> > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT
> > # Loading work.glbl
> > # ** Warning: (vsim-PLI-3003)
> > C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.v(=
18339):
> > [TOFD] - System task or function '$lm_model' is not defined.
> > # Region:
> > /test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1
> > # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
> > # .main_pane.workspace
> > # .main_pane.signals.interior.cs
> > # No errors or warnings.
> > # Break at test_clock.tfw line 82
> > # Simulation Breakpoint: Break at test_clock.tfw line 82
> > # MACRO ./test_clock.fdo PAUSED at line 17
> >
> > In this report I'm not andestend warning. All off signals from RocketIO
> > module is x-state. But all of oter modules simulate succes.
> >=20
> > :) And sorry my very bad english
Article: 106959
Hi All,
I've released the first version of my Xilinx JTAG programmer for
Win32/Linux.
Supports Parallel III Cable and Digilent USB. Check and of message for
supported devices!
http://sourceforge.net/projects/xilprg
This is a very first version, so please be patient with me and provide
as much info as possible if you report a bug!
Zoltan
zoltan_csizmadia at yahoo dot com
Supported operations:
---------------------
Detect device chain:
detect
Erase device:
erase pos
E.g.: erase 1
Program device:
program [-bit|-bin|-mcs] pos file
E.g.: program 1 c:\untitled.mcs
program 2 download.bit
Read device:
read [-bin|-mcs] pos file
E.g.: read 1 c:\untitled.mcs
Select programmer cable:
Xilinx Parallel III
cable xil3 [ioaddr]
Digilent USB
cable dusb
Supported cables:
-----------------
Xilinx Parallel III
Win32: giveio.sys must be installed to enable user-mode I/O access!
Digilent USB
Win32: Digilent driver must be installed!
Linux: libusb must be installed!
Supported devices [Detect/Erase/Program/Read]:
----------------------------------------------
Xilinx Spartan-2 [D P ]
Xilinx Spartan-2E [D P ]
Xilinx Spartan-3 [D P ]
Xilinx Spartan-3E [D P ]
Xilinx Virtex [D P ]
Xilinx VirtexE [D P ]
Xilinx Virtex-2 [D P ]
Xilinx Virtex-2 Pro [D P ]
Xilinx Virtex-4 [D P ]
Xilinx Virtex-5 [D ]
Xilinx XCF00S Platform Flash [DEPR]
Xilinx XC18V00 Platform Flash [DEPR]
Xilinx XCF00P Platform Flash [D ]
Xilinx XCR3000XL CPLD [D ]
Xilinx XC9500 CPLD [D ]
Xilinx XC9500XL CPLD [D ]
Xilinx XC9500XV CPLD [D ]
Article: 106960
Thanks! When I write line Veriuser=3D
$LMC_HOME/lib/pcnt.lib/swiftpli_mti.dll agayn end start simulate -
simulate succesful!. But when I start to compilyate library - this line
deleted agayn. Whay?
axalay@gmail.com =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):
> I am write Veriuser=3D $LMC_HOME/lib/pcnt.lib/swiftpli_mti.dll after line
>
> ; List of dynamically loaded objects for Verilog PLI applications in
> fime modelsim.ini but this line deteted automatically.
> Question : That line comment or not comment?
>
>
>
> Jim Wu =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0):
>
> > Have you checked AR 22214?
> >
> > http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=3Dyes&get=
PagePath=3D22214
> >
> >
> > HTH,
> > Jim
> > http://home.comcast.net/~jimwu88/tools/
> >
> > axalay@gmail.com wrote:
> > > Modelsim report is:
> > >
> > > # Reading C:/Modeltech_6.1b/tcl/vsim/pref.tcl
> > > # // ModelSim SE 6.1b Sep 8 2005
> > > # //
> > > # // Copyright Mentor Graphics Corporation 2005
> > > # // All Rights Reserved.
> > > # //
> > > # // THIS WORK CONTAINS TRADE SECRET AND
> > > # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
> > > # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
> > > # // AND IS SUBJECT TO LICENSE TERMS.
> > > # //
> > > # do {test_clock.fdo}
> > > # ** Warning: (vlib-34) Library already exists at "work".
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > > # -- Compiling module stm4ser
> > > #
> > > # Top level modules:
> > > # stm4ser
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > > # -- Compiling module dcm1
> > > #
> > > # Top level modules:
> > > # dcm1
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > > # -- Compiling module clock
> > > #
> > > # Top level modules:
> > > # clock
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > > # -- Compiling module test_clock
> > > #
> > > # Top level modules:
> > > # test_clock
> > > # Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
> > > # -- Compiling module glbl
> > > #
> > > # Top level modules:
> > > # glbl
> > > # vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps test_clock
> > > glbl
> > > # Loading work.test_clock
> > > # Loading work.clock
> > > # Loading work.dcm1
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.BUFG
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.IBUFG
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.DCM
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_divide_by_2
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_maximum_period_che=
ck
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.dcm_clock_lost
> > > # Loading work.stm4ser
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_CUSTOM
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT
> > > # Loading C:\Xilinx\verilog\mti_se\unisims_ver.GT_SWIFT_BIT
> > > # Loading work.glbl
> > > # ** Warning: (vsim-PLI-3003)
> > > C:/Xilinx/verilog/mti_se/unisims_ver/unisims_ver_SmartWrapper_source.=
v(18339):
> > > [TOFD] - System task or function '$lm_model' is not defined.
> > > # Region:
> > > /test_clock/UUT/module1/GT_CUSTOM_INST/gt_1/gt_swift_1/I1
> > > # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
> > > # .main_pane.workspace
> > > # .main_pane.signals.interior.cs
> > > # No errors or warnings.
> > > # Break at test_clock.tfw line 82
> > > # Simulation Breakpoint: Break at test_clock.tfw line 82
> > > # MACRO ./test_clock.fdo PAUSED at line 17
> > >
> > > In this report I'm not andestend warning. All off signals from Rocket=
IO
> > > module is x-state. But all of oter modules simulate succes.
> > >=20
> > > :) And sorry my very bad english
Article: 106961Joseph H Allen schrieb: > Hello, > > Suppose I have a PCIe core in an FPGA on a PCIe card plugged into a modern > PC. What read latency should I expect? How much time is it from when I > submit a request to the PCIe core to read from the PC's main memory to when > I get back the first datum from the PCIe core? How does this compare to > PCI-X? The bottom line for all PCI variants if you want performance is: DON'T READ. Not only the PCI standards but also the chipsets are designed around the concept that data is written back by a bus master device. On some modern mainboards we see something like 10 PCI33 clock cycles between consecutive reads by the processor. Those reads are adjacent assembler instructions in the source code. This means that the chipset one the mainboard thinks really hard about these read accesses and maybe takes a nap inbetween. What we also see is that one 128-bit read instruction is split into two 64-bit read accesses on PCI and PCIe. Kolja SulimmaArticle: 106962
Hi I want to allocate memory but it doesn't work. If I use xil_malloc I can not allocated enough memory, pointer to NULL is returned. Whem I want to use malloc, I get the following error: ./microblaze_0/lib//libc.a(malloc.o): In function `malloc': malloc.o(.text+0x8): relocation truncated to fit: R_MICROBLAZE_SRW32 .sdata malloc.o(.text+0x20): relocation truncated to fit: R_MICROBLAZE_SRW32 .sdata collect2: ld returned 1 exit status I edit the heap size too. Can anybody help me? cu EmpArticle: 106963
fpgakid@gmail.com wrote: > I've released the first version of my Xilinx JTAG programmer for > Win32/Linux. > > Supports Parallel III Cable and Digilent USB. Check and of message for > supported devices! > > http://sourceforge.net/projects/xilprg Why not just port xc3sprog to Windows? -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 106964
Hi Does has anyone experienced problems with modelsim running slowly? I am not talking about simulation speed but rather when I have signals open in the wave window. There is a delay with zooming in and scrolling before it actually happens. Its not like I have a slow pc either. Cheers JonArticle: 106965
That is what I did to solve the problem. I am still curious how the problem started though. /Johan Jeroen Tenbult wrote: > Hello Johan, > > I had the same map error. Only thing to do is to create a complete new > project and start all over again. > > Regards, > > Jeroen > > > "Johan Bernspång" <xjohbex@xfoix.se> schreef in bericht > news:ece9jc$mok$1@mercur.foi.se... >> Hi all, >> >> I came back from vacation yesterday, and full of ideas I started to work >> where I left before the holidays. The first thing that happens is that I >> can't map my design anymore. The vhdl is exactly the same as earlier, and >> the only difference in the map report is the lines regarding related and >> unrelated logic below: >> >> Design Summary >> -------------- >> Number of errors: 0 >> Number of warnings: 130 >> Logic Utilization: >> Number of Slice Flip Flops: 7,351 out of 21,504 34% >> Number of 4 input LUTs: 5,267 out of 21,504 24% >> Logic Distribution: >> Number of occupied Slices: 5,505 out of 10,752 51% >> Number of Slices containing only related logic: 5,505 out of 5,505 >> 100% >> Number of Slices containing unrelated logic: 0 out of 5,505 >> 0% >> *See NOTES below for an explanation of the effects of unrelated >> logic >> Total Number 4 input LUTs: 6,045 out of 21,504 28% >> Number used as logic: 5,267 >> Number used as a route-thru: 310 >> Number used as Shift registers: 468 >> >> Number of bonded IOBs: 132 out of 456 28% >> IOB Flip Flops: 5 >> IOB Master Pads: 55 >> IOB Slave Pads: 55 >> IOB Dual-Data Rate Flops: 26 >> Number of Block RAMs: 42 out of 56 75% >> Number of MULT18X18s: 40 out of 56 71% >> Number of GCLKs: 5 out of 16 31% >> Number of DCMs: 1 out of 8 12% >> Number of BSCANs: 1 out of 1 100% >> >> Number of RPM macros: 26 >> Total equivalent gate count for design: 3,057,923 >> Additional JTAG gate count for IOBs: 6,336 >> Peak Memory Usage: 266 MB >> >> Following the design summary is a note regarding related logic. >> >> In my old map report none of this related logic stuff is present. But I >> can't really understand why the mapper fails due to this since none of the >> logic is unrelated. >> >> I am pretty sure that my code hasn't changed during my vacation. Does ISE >> know that there is a new version out and it wants me to upgrade? ;-) >> >> Has anyone experienced this before? >> >> Regards >> Johan >> >> -- >> ----------------------------------------------- >> Johan Bernspång, xjohbex@xfoix.se >> Research engineer >> >> Swedish Defence Research Agency - FOI >> Division of Command & Control Systems >> Department of Electronic Warfare Systems >> >> www.foi.se >> >> Please remove the x's in the email address if >> replying to me personally. >> ----------------------------------------------- > > -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 106966
For me it usually does something like that when the resolution is set to something very high, like ps... Ben "maxascent" <maxascent@yahoo.co.uk> wrote in message news:p_udnTDzM6NHl3HZnZ2dneKdnZydnZ2d@giganews.com... > > Hi > > Does has anyone experienced problems with modelsim running slowly? I am > not talking about simulation speed but rather when I have signals open in > the wave window. There is a delay with zooming in and scrolling before it > actually happens. Its not like I have a slow pc either. > > Cheers > > JonArticle: 106967
Daniel O'Connor schrieb: > fpgakid@gmail.com wrote: > > I've released the first version of my Xilinx JTAG programmer for > > Win32/Linux. > > > > Supports Parallel III Cable and Digilent USB. Check and of message for > > supported devices! > > > > http://sourceforge.net/projects/xilprg > > Why not just port xc3sprog to Windows? > > -- > Daniel O'Connor software and network engineer > for Genesis Software - http://www.gsoft.com.au > "The nice thing about standards is that there > are so many of them to choose from." > -- Andrew Tanenbaum > GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C while everybody likes it in its own sandbox better. AnttiArticle: 106968
jacko schrieb: > Sylvain Munaut wrote: > > > Antti Lukats wrote: > > > "Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> schrieb im > > > Newsbeitrag news:44eb5529$0$32429$ba620e4c@news.skynet.be... > > >> Hi everyone. > > >> > > >> I was just wondering if someone knew where to find documentation about > > >> the Xilinx Virtual Platform. > > >> > > >> I'm interested in writing simulation models for my own cores. Since > > >> those cores have external interface, they can't be autogenerated and > > >> they're critical to my application ... (the code will do nothing > > >> without them). > > >> > > >> Currently, I've managed by a few hacks to do pretty much what I > > >> want but I'd like to know if there is any documentation about it ? > > >> Because I didn't find much ;( > > >> > > >> Sylvain > > > > > > no there isnt - thats the reason I working on XSIM the only simulator up > > > today that succesfully runs MicroBlaze uClinux unmofied images > > > > Well, I got it to run ... but I thought there might be a doc to be sure > > I was doing it right. > > > > I saw xsim > > > > > is pretty fun to see peripherals like > > > > > > sd card > > > systemace > > > ide disk > > > i2c rtc > > > video display > > > pictiva oled > > > > > > to work from the microblaze simulator :) > > > > > > the plugin API for the XSIM simulator is also available. fully documentated > > > ! > > > > Well, I tried to find the link again on xilant.com but I just couldn't ... > > > > And the last time I saw it, it was windows only and I'm a linux guy ... > > A shame though because a nice simulator would definitly be useful > > > got altera stuff as xilinx seems to send multiple emails welcoming me > to the ISE, but never gives up the program. > > cheers what program should they give up!? isnt the webPack enough for you? AnttiArticle: 106969
Martin Schoeberl wrote: > What do you mean with 'very close to the hardware'? I try to > avoid vendor specific library elements as much as possible and > stay with plain VHDL. If you mean that the VHDL coding style > is more hardware oriented, than I agree. Yes, this was what I mean, e.g. figures 5.6 to 5.9 of your thesis, where you describe the processor pipeline with gates and which is implemented like this in VHDL. But maybe this is the normal case and I'm just to new to VHDL to write and interconnect components in this way. http://www.jopdesign.com/thesis/thesis.pdf > I started directly > in an FPGA implementation and did almost no simulation. Why not? When I was implementing my CRC32 check for my network core, I've tested the algorithm with a VHDL testbench (ethernet packet send and receive works at 10 Mbit and 100 Mbit on my Spartan 3E starter kit now). The turnaround times are faster with simulation and it is very easy to debug it, instead of debugging a synthesized core in hardware. The same was true for my DS2432 ROM id reader, where I've written the testbench, first and then implemented the reader. http://www.frank-buss.de/vhdl/spartan3e.html -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 106970
> Hi > Does has anyone experienced problems with modelsim running slowly? I am > not talking about simulation speed but rather when I have signals open in > the wave window. There is a delay with zooming in and scrolling before it > actually happens. Its not like I have a slow pc either. I get similar symptoms if the simulation is still running in the background. Is that it? Nial.Article: 106971
Yes I do have it set to 10ps, so maybe that is the reason.Article: 106972
fpgakid@gmail.com <zcsizmadia@gmail.com> wrote: > Hi All, > I've released the first version of my Xilinx JTAG programmer for > Win32/Linux. > Supports Parallel III Cable and Digilent USB. Check and of message for > supported devices! > http://sourceforge.net/projects/xilprg ... I tried to give an empty password for the login and got: > cvs login: authorization failed: server xilprg.cvs.sourceforge.net > rejected access to /cvsroot/xilprg for user anonymous Anything special to care for? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 106973
Uwe Bonnes schrieb: > fpgakid@gmail.com <zcsizmadia@gmail.com> wrote: > > Hi All, > > > I've released the first version of my Xilinx JTAG programmer for > > Win32/Linux. > > > Supports Parallel III Cable and Digilent USB. Check and of message for > > supported devices! > > > http://sourceforge.net/projects/xilprg > > ... > > I tried to give an empty password for the login and got: > > cvs login: authorization failed: server xilprg.cvs.sourceforge.net > > rejected access to /cvsroot/xilprg for user anonymous > > Anything special to care for? > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- just click on "Files" and select suitable mirror. both the binaries and sources are downloadable! AnttiArticle: 106974
Jim Granville wrote: > The tiniest CPUs do not need a stack, and interupts do not need to be > re-entrant, so a faster context switch is to re-map the Registers, Flags > (and even PC ? ) onto a different area in BRAM. > You can share this resource by INTs re-map top-down, and calls re-map > bottom up - with a hardware trap when they collide :) Once you get into seeing clearly the relationship between features and cost a lot can be removed. Interrupts can be removed at extremely low cost to applications. Both the Microchip PIC12 and Freescale RS08 do not have interrupts. In the RS08 C compiler we developed some software IP to where possible go into a power down mode and launch execution threads that compiled as execution to completion. The threads are typically short and a as a side effect run to completion makes local re-use easy C compilers implemented for small processors work well with out either a data or subroutine return stack. Two of the processors we have written compilers for in the last couple years both used an assessable return register. Flow control analysis in the compiler make nested subroutines user transparent. The instruction set reduction in the RS08 from the S08 parent had a 4-6% impact on application performance. Walter..
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