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ghelbig@lycos.com schrieb: > They have re-designed their web site. Hope you read Swedish. > > http://www.realfast.se/RFIPP/products/sierra/sierra.shtml > > > Antti wrote: > > Xilinx website still has links to it > > > > http://www.realfast.se/RFIPP/HWSW/system/system.shtml > > > > but all reference to the Sierra RTOS now point to "page not found" any > > idea what happened? > > > > Antti thanks! I was searching at their website, even landed at the prevas website, but as soon as change language at prevas to english then sierra information is not there. looks like realfast has sold sierra product to a company that has no clue about FPGAs. AnttiArticle: 105976
> Hi Xesium, > > If you use BSB to generate your design, the default setting is actually > not a Harvard architecture system. So no extra 2KB. :) > > If you need Harvard architecture, from my experience, you need add a > separate BRAM controller and BRAMs. > > Wayne Hi Wayne, so you mean that the address space that it shows which is from 0000 to ffff is the address space for both instruction and data? So how is it ordered? how does it distinguish between data and instruction? Because I think the compiler doesn't really consider it (At least I think)? And also I have this problem that I want to profile my application when it is executed on Microblaze but I don't know which address to set as profiling_mem. Can I assign or should I assign an address beyond the address space for data and instruction? Thanks,Article: 105977
Hi guys, I'm trying to profile my application while it is running on microblaze. However I have a problem in setting profile_mem configuration. My LMB instruction and data address space spans from 0000 to ffff which is 64KB. I really don't know which address to assign for the profiler to profile the application. For some addresses (like 0x00010000) while executing it generates an error which says "Unexpected Debug Trap Condition occured. Microblaze current PC value is 0x18. Possible causes could be stack overflow, corrupt code or data section. To continue reset microblaze or configure FPGA". To me it sounds like I'm using an address space which I shouldn't use but still I don't know which address space I should use for the profiler either. Also for some addresses it generates gmon.out file but when I want to extract its information with -p option it says that gmon.out file is not in a.out format. Do you have any idea how I can profile my application with these problems? Thanks a lot beforehand, AmirArticle: 105978
On 3 Aug 2006 07:51:25 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >http://xilant.com/content/view/45/2/ > >soon... > Does anybody know which things will change (to better, I hope) form MB4 to MB5? ZaraArticle: 105979
Xesium wrote: > Hi guys, > I'm trying to profile my application while it is running on microblaze. > However I have a problem in setting profile_mem configuration. My LMB > instruction and data address space spans from 0000 to ffff which is > 64KB. I really don't know which address to assign for the profiler to > profile the application. For some addresses (like 0x00010000) while > executing it generates an error which says "Unexpected Debug Trap > Condition occured. Microblaze current PC value is 0x18. Possible causes > could be stack overflow, corrupt code or data section. To continue > reset microblaze or configure FPGA". To me it sounds like I'm using an > address space which I shouldn't use but still I don't know which > address space I should use for the profiler either. Also for some > addresses it generates gmon.out file but when I want to extract its > information with -p option it says that gmon.out file is not in a.out > format. > Do you have any idea how I can profile my application with these > problems? > > Thanks a lot beforehand, > > Amir Hi Amir, The address space for code and data is controlled by linkscript. You can also see the memory usage by 'mb-objdump --syms xx.elf'. Good luck, WayneArticle: 105980
Weng Tianxiang wrote: > I am a newbie in the field and really like to learn more. But I am > determined to learn all those things you have mentioned better. > What books can you suggest for me to buy and read about the fields? Hmm. Not sure I'd recommend books - they tend to be too theoretical. If I were you I'd enter some of the search words into wikipedia and google and read any technical papers you find that look authoritative. <http://en.wikipedia.org/wiki/Data_compression> is a good start. Code can also be useful, though often very cryptic - people who write compressors are often very bad at writing readable code. What's the source of your data? Are the 64 bits broken into fields, say 4x16-bit fields? What patterns might you expect? Do the values tend to cluster around a certain range, or tend to be close to previous readings? All these things affect the predicability of your data and so are intimately connected with the compression approach you must choose.Article: 105981
"sovan" <sovan.kundu@gmail.com> writes:
> I am trying to simulate RocketIO MGT in VCS. When I do
> vcs -lmc-swift-template GT_SWIFT
> it says it couldn't find libswift.so library. I am using Red Hat
> Enterprise Linux WS release 3. What files/directories should I look for
> to confirm if the SmartModel Library is installed in VCS? or any better
> way to find if VCS is setup properly for SmartModel simulation.
It's been a couple years since I did this, but in my scripts I have
something like:
TARGET_OPS="... -y $ISE_HOME/smartmodel/$xsmarch/wrappers/vcs -lmc-swift"
LDFLAGS="$LDFLAGS -L$ISE_HOME/smartmodel/$xsmarch/installed_$xsmarch/lib/$xsmlibd"
LP=$ISE_HOME/smartmodel/$xsmarch/installed_$xsmarch/lib/$xsmlibd
if test -z "$LD_LIBRARY_PATH"
then
LD_LIBRARY_PATH=$LP
else
LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$LP
fi
export LD_LIBRARY_PATH
LMC_HOME=$ISE_HOME/smartmodel/$xsmarch/installed_$xsmarch
export LMC_HOME
...
$VCS_HOME/bin/vcs ... $TARGET_OPS ...
The xmarch and xsmlibd variables are set by my configure script if I'm
running on solaris or linux etc.
case $target in
i?86-pc-linux-gnu|\
x86_64-unknown-linux-gnu) xsmarch=lin ;
xsmlibd=x86_linux.lib ;;
sparc-sun-solaris*) xsmarch=sol ;
xsmlibd=sun4Solaris.lib ;;
*) xsmarch=unknown ;;
esac
I home this helps
Petter
--
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A: Top-posting.
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Article: 105982Hi Martin, where do the memory data input / write strobe/ read strobe inputs come from, pins or registers ?=20 Rgds Andr=E9Article: 105983
Hi, What OS are you using ? Rgds Andr=E9Article: 105984
>where do the memory data input / write strobe/ read strobe inputs >come from, pins or registers ? For the test they come from pins. Therefore, the setup and hold times for the pins are very long, but this not the issue. The maximum frequency is determined by the memory blocks between the input registers (address, write data) and the memory or output register (read data). MartinArticle: 105985
Hello, I have designed a CardBus Design, which is very similar to pci with full master functionality. The main aim of this card is to transfer a huge amount of data to and from PC RAM to the CardBus card. But in master read mode I very often get a target retry. The fact of an target retry (in this case the pc is the target) is not abnormal but I have scanned the pci bus and I have seen a lot of target retries in series -> sometimes more then 100 in a row. This is absolute unacceptable due to the poor bus performance -> so my fifo's run out of data. The common pc memory (ram) is locked from driver and is set as non cacheable. I hope that somebody can help me in this issue. I am not really sure if this is a hardware or a software (driver) problem. With kind regards Nico PresserArticle: 105986
> The board will be used to test radiation tolerance techniques, but > background radiation is too high to put a PC nearby for control. (and > want to use it afterwards:) If everything else fails, you might dedicate an old (disposable) PC to this job. Put it right next to the FPGA, and remote-control it over ethernet with Remote Desktop (comes with WinXP). MarcArticle: 105987
ALuPin@web.de wrote: > Hi, > What OS are you using ? > > Rgds > Andr=E9 Windows XP SP2. I just wanted to add that the error dialog Matlab reports after crashing is titled "Visual C++ Runtime Library Error".Article: 105988
Which version of ISE? Is it 32-bit or 64-bit? Last I checked, Smartmodel is not available for the 64-bit ISE. If you use ISE 8.1 32-bit, you need to run "compxlib" first to compile the smartmodel library and then set up LD_LIBRARY_PATH accrodingly. HTH, Jim http://home.comcast.net/~jimwu88/tools/ sovan wrote: > I am trying to simulate RocketIO MGT in VCS. When I do > vcs -lmc-swift-template GT_SWIFT > it says it couldn't find libswift.so library. I am using Red Hat > Enterprise Linux WS release 3. What files/directories should I look for > to confirm if the SmartModel Library is installed in VCS? or any better > way to find if VCS is setup properly for SmartModel simulation. > > Thanks, > Sovan.Article: 105989
Weltraumbaer wrote: > Hello, > > I have designed a CardBus Design, which is very similar to pci with > full master functionality. The main aim of this card is to transfer a > huge amount of data to and from PC RAM to the CardBus card. But in > master read mode I very often get a target retry. The fact of an target > retry (in this case the pc is the target) is not abnormal but I have > scanned the pci bus and I have seen a lot of target retries in series > -> sometimes more then 100 in a row. This is absolute unacceptable due > to the poor bus performance -> so my fifo's run out of data. The common > pc memory (ram) is locked from driver and is set as non cacheable. > > I hope that somebody can help me in this issue. I am not really sure if > this is a hardware or a software (driver) problem. > > With kind regards > Nico Presser Use significantly larger FIFOs. You can end up with the bus locked out while cache flush operations are going on or other operations that use the processor memory interconnect that hooks up to the PCI interface. If there's other PCI activity, changing the latency timer value could help out. Some processors or bridges will retry a transaction rather than hold the bus for a first burst of a series. Some processors take a memory-read-multiple as a one cache-line transaction but prefetch the next cache-line while others interpret the request as 2 cache-lines at once. Read up on your processor's PCI interface.Article: 105990
These are finally in stock for those who have been after them. John Adair Enterpoint Ltd.Article: 105991
John_H wrote: > Weltraumbaer wrote: >> Hello, >> >> I have designed a CardBus Design, which is very similar to pci with >> full master functionality. The main aim of this card is to transfer a >> huge amount of data to and from PC RAM to the CardBus card. But in >> master read mode I very often get a target retry. The fact of an target >> retry (in this case the pc is the target) is not abnormal but I have >> scanned the pci bus and I have seen a lot of target retries in series >> -> sometimes more then 100 in a row. This is absolute unacceptable due >> to the poor bus performance -> so my fifo's run out of data. The common >> pc memory (ram) is locked from driver and is set as non cacheable. >> >> I hope that somebody can help me in this issue. I am not really sure if >> this is a hardware or a software (driver) problem. We learned the hard way that PCI is just not intended to read at high data rates. Some chipset will even split a single 128-bit read (SSE2 move) of the CPU into two PCI accesses. You can't really expect the chipset to be nicer to your expansion board than it is to the CPU. I would not really on getting any read bursts larger than a cache line to work without tuning chipset specific registers. Kolja SulimmaArticle: 105992
That will not work, Even an old PC has power supplies. The first thing to pop near a radiation source is often the power transistors in the power supplies. Then, there is destructive SCR latch up that any device may suddenly experience (unless the vendor has already tested it in a beam - which for a PC is laughable). Basically, a PC represents a collection of the least tested, most unreliable components when it comes to neutron or proton beams. For heavy ions, they will fall like a house of cards, within minutes. The above does not even cover operation without crashing. We have seen vendors leaving beam facilities who were unable to do any testing because stray particles upset not only upset their components, but upset the equipment they were trying to use to set up and measure (don't forget the power supply for the device under test!). We also use long cables. The cables sometimes have to be specially constructed, as all signals require a ground next to them to eliminate cross talk, and coiling a cable (to store its slack) may add cross talk right back in (the cable must remain non-overlapping). Our longest cable is 30 meters, however, and that appears to do what we need it to do. We did not require any buffers, drivers, etc. Just good SI engineering over a long, low loss cable (yes, we ran simulations). The other issue is that any metals in whatever is near or in the beam may be activated (become radioactive), and storing a bunch of activated stuff is not something that you want to discuss with your plant safety people. The experiments themselves are left to "cool off" (most active isotopes to decay) for a couple of months. I would hate to add to that more stuff that I can't use, access, or move. Since Xilinx is the second largest user of Los Alamos LANSCE beam time (Intel is the first), we have been there, done that. This also means that if you need any information on neutrons, protons, or heavy ions, Xilinx has all the data you need to design your system: on the ground, or in space. Which as it turns out, is good, as anything from a lcd TV, to an automobile navigation system, to a cell base station or network router switch, will be subject to atmospheric neutrons from cosmic rays. Knowing that Xilinx FPGAs will not undergo destructive latch up, and are robust to upsets becomes just a matter of design, not one that will later back-fire on you, and get you fired. Austin jetmarc@hotmail.com wrote: >> The board will be used to test radiation tolerance techniques, but >> background radiation is too high to put a PC nearby for control. (and >> want to use it afterwards:) > > If everything else fails, you might dedicate an old (disposable) PC to > this job. Put it right next to the FPGA, and remote-control it over > ethernet with Remote Desktop (comes with WinXP). > > Marc >Article: 105993
Hi, I am to build a fpga system that captures data from external signals and store it to DDR, also after the capture data must be transferred to the PC via PCI bus via DMA or so. So this is a CAPTURE-to-DDR DDR-to-PCI... How is this sytem implemented?Article: 105994
Hello, I'm relatively new to FPGA programming and looking for some advice. I have an application that needs reliable, high bandwidth (+50 MHz), access to a few Megs worth of RAM and I am wondering how I should go about this. I am working with the Xilinx ML403 development board which has the Virtex-4 FX12 FPGA and 64 MB of DDR SDRAM. My intention is to implement my project as a peripheral component of a processor system generated by EDK. The three possible ways I have come up with for implementing this part of my project are: 1. Use the EDK memory controller core as a separate peripheral on the PLB and have a software application to transfer data between it and my peripheral. This seems to be the easiest option to implement but I doubt that it will give me the performance I need. Also it will tie up the processor. 2. As before I could use the EDK memory controller core as a separate peripheral on the PLB however this time I could implement my peripheral as a master on the PLB bus. I believe that this would allow my peripheral to directly access the SDRAM controller without interference of/with the processor. However I do not know how difficult it is to write a PLB bus master and I do not know how to predict how detrimental other traffic on the PLB bus will be to the available bandwidth for my application. 3. Finally I could integrate the SDRAM controller into my peripheral. This clearly would be the highest bandwidth solution, however it seems the most technically complicated. As I mentioned I am a relative beginner with FPGA programming and am looking for advice on how to proceed. I would also greatly appreciate any links to example projects or documentation that might be relevant to this project. Thanks in advance for the help! Regards, -DanArticle: 105995
Hi Martin, The 210MHz is correct for Cyclone II M4K in SDP (simple dual port) mode with dual, non-PLL clocks. The speed for Cyclone II M4K in SDP mode with a single, non-PLL clock is 235Mhz. - Subroto Datta Altera Corp.Article: 105996
Thanks for your replies. It turns out that I needed to first program with impact and then start chipscope. Seems a bit stupid to have to do this but at least it works JonArticle: 105997
I have took a Xilinx design through synplify and then started ise from synplify to place and route. The problem is I have some coregen components and when I try and place and route it complains about missing edif files. I can find these files in the synplify directory but how do I tell ise about them? Cheers JonArticle: 105998
In the Xilinx ISE GUI, right-click on Implementation or Translate in the Processes window, the Translate Properties include a "Macro Search Path" where you can browse-to and specify the directory that holds any extra edif or nco files. "maxascent" <maxascent@yahoo.co.uk> wrote in message news:Q5udnegNE8Bq907ZRVn_vA@giganews.com... > > I have took a Xilinx design through synplify and then started ise from > synplify to place and route. The problem is I have some coregen components > and when I try and place and route it complains about missing edif files. > I > can find these files in the synplify directory but how do I tell ise about > them? > > Cheers > > JonArticle: 105999
Hi, I am using a FFT core block on Xilinx Virtex-4 FPGA. On simulating a 1024 point FFT with a 64 bit 10 MHz PRBS, I seem to see the FFT data coming out as steps of zeros and FFs. My ADC samples this data at 1.5GHz, so the peak is at the very end of the spectrum as per Matlab simulations I would like to know if there are any more ways to check the FFT core in realtime by probably giving in a 10 MHz sine wave signal. Thanks in advance for all suggestions and feedback, Vivek
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Compare FPGA features and resources
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