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Hi Antti, In Spartan3E Starter Kit can we use FX2 processor to reporgram the FPGA ? have some application like that and would like to know whether it works before trying in actual board rgds bijoyArticle: 105801
bijoy schrieb: > Hi Antti, > > In Spartan3E Starter Kit can we use FX2 processor to reporgram the FPGA ? > > have some application like that and would like to know whether it works before trying in actual board > > rgds bijoy sure the FX2 can be used to load the FPGA! the FX2 and the CPLD are 'duplica' of Xilinx platform cable - you may have to reprogram the CPLD also in order to have the comms done (or if you figure out the way the original CPLD code works then you can keep that). There is software available for FX2 that fully emulated Altera USB blaster - so you could take that firmware, implement simple wire-bypass in the CPLD and then use Altera Quartus programmer to play back impact generated SVF/STAPL files to program the FPGA AnttiArticle: 105802
Uwe: > Isn't there an option to set the JTAG CLK speed in impact? The speed setting in impact apparently doesn't apply to my Parallel Cable 3. > Another option beside the USB Extender is to convert the levels to a > RS422/485 signal and use a twisted pair cable. This is exactly what i'm doing, with an RS485 driver and receiver on each end of my cable. I'm getting 230kbps on the system for serial communication:), but I think my transmission delay is too large for Impact to be happy. I measured the duration of a clock pulse to be as little as 1us - with a delay of 800ns, the reading of data fails. Jim: Hazardous as in high energy particles, especially protons and neutrons. The board will be used to test radiation tolerance techniques, but background radiation is too high to put a PC nearby for control. (and want to use it afterwards:) It is inside a faraday cage, so even very high speed wireless options are also out. I'm using a differential line pair for every input signal - the R485 is only used as a repeater and receiver pair, with no other 485 protocol on top of it. Right now I'm looking into the open source options, hoping I can do (slower) readback with openwince-jtag. thank you!Article: 105803
Hello Wayne. Nice to hear from you. I will send you an email attaching my ISE file (project file) alongwith it. As our freind here suggested,I am trying to get a student edition of Active HDL but I am also interested in knowing more about the tool. It looks like there have to be certain libraries included for a program to compile properly. I know that it is different from C/C++ compilers wherein depending on what we intend to do in our program, we have to include libraries for that. But here in VHDL it seems that an actual physical directory (like the isi_temp) seems to get created and I wonder if my project files should also reside in that same directory or should be linked to that library in any way. Also does a library gets physically mapped into a directory on the hard drive? Anyway, I will send you a separate email because I don't know how do I add attachments to this message. If I know do let me know so that I may attach the files here itself. Hoping to hear from you soon, Aijaz Baig. quickwayne@gmail.com wrote: > aijazbaig1@gmail.com wrote: > > Hello Freinds. > > I am a newcomer to the field of programmable logic devices and I am > > currently trying to teach myself VHDL. I hope to learn some VHDL before > > the next semester starts. > > My sole purpose as of now is not to actually synthesise stuff but just > > to simulate the various designs that I may try to create. I am using > > the xilinx ISE webpack 8.2 on a windows XP machine. > > Below I am trying to implement a design called ones_cnt wherein the > > counter just counts the number of ones in a 4 bit array and prints the > > result in a binary format.To understand the concept of configuration > > declarations I have declared multiple architectures and I am trying to > > use the configuration declaration statement to select one the them. > > > > Heres my code. Its a lil big may be but I hope you guys would have a > > look. > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > > ---- Uncomment the following library declaration if instantiating > > ---- any Xilinx primitives in this code. > > --library UNISIM; > > --use UNISIM.VComponents.all; > > > > entity ones_cnt is > > Port ( A : in STD_LOGIC_VECTOR (2 downto 0); > > C : out STD_LOGIC_VECTOR (1 downto 0)); > > end ones_cnt; > > > > architecture Algorithmic of ones_cnt is > > begin > > process(A) > > variable NUM: INTEGER range 0 to 3; > > begin > > NUM := 0; > > for I in 0 to 2 loop > > if A(I) = '1' then > > NUM := NUM + 1; > > end if; > > end loop; > > case NUM is > > when 0 => C <= "00"; > > when 1 => C <= "01"; > > when 2 => C <= "10"; > > when 3 => C <= "11"; > > end case; > > end process; > > end Algorithmic; > > > > use work.all; ----- this is the line where the error is flaged!! see > > below for details. > > architecture STRUCTURAL of ones_cnt is > > component MAJ3C > > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > > end component; > > component OPAR3C > > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > > end component; > > for all: MAJ3C use entity MAJ3(AND_OR); > > for all: OPAR3C use entity OPAR3(AND_OR); > > begin > > COMPONENT_1: MAJ3C > > port map (A,C(1)); > > COMPONENT_2: OPAR3C > > port map (A,C(0)); > > end STRUCTURAL; > > > > entity AND2 is > > port (I1,I2: in BIT; O: out BIT); > > end AND2; > > architecture BEHAVIORAL of AND2 is > > begin > > O <= I1 and I2; > > end BEHAVIORAL; > > > > entity OR3 is > > port (I1,I2,I3: in BIT; O: out BIT); > > end OR3; > > architecture BEHAVIORAL of OR3 is > > begin > > O <= I1 or I2 or I3; > > end BEHAVIORAL; > > > > use work.all; > > entity MAJ3 is > > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > > end MAJ3; > > architecture AND_OR of MAJ3 is > > component AND2C > > port (I1,I2: in BIT; O: out BIT); > > end component; > > component OR3C > > port (I1,I2,I3: in BIT; O: out BIT); > > end component; > > for all:AND2C use entity AND2(BEHAVIOR); > > for all:OR3C use entity OR3(BEHAVIOR); > > signal A1,A2,A3: BIT; > > begin > > G1: AND2C > > port map (X(0),X(1),A1); > > G2: AND2C > > port map (X(0),X(2),A2); > > G3: AND2C > > port map (X(1),X(2),A3); > > G4: OR3C > > port map (A1,A2,A3,Z); > > end AND_OR; > > > > entity AND3 is > > port(I1,I2,I3: in BIT; > > O: out BIT); > > end AND3; > > architecture BEHAVIORAL of AND3 is > > begin > > O <= I1 and I2 and I3; > > end BEHAVIORAL; > > > > entity OR4 is > > port(I1,I2,I3,I4: in BIT; > > Z: out BIT); > > end OR4; > > architecture BEHAVIORAL of OR4 is > > begin > > Z <= X1 or X2 or X3 or X4; > > end BEHAVIORAL; > > > > use work.all > > entity OPAR3 is > > port (X: in BIT_VECTOR(2 downto 0); Z: out BIT); > > end OPAR3; > > architecture AND_OR of OPAR3 is > > component AND3C > > port (I1,I2,I3: in BIT; O: out BIT); > > end component; > > component OR4C > > port (I1,I2,I3,I4: in BIT; O: out BIT); > > end component; > > for all:AND3C use entity AND3(BEHAVIORAL); > > for all:OR4C use entity OR4(BEHAVIORAL); > > signal A1,A2,A3,A4: BIT; > > begin > > G1: AND3C > > port map (X(2),not X(1),not X(0),A1); > > G2: AND3C > > port map (not X(2),not X(1),X(0),A2); > > G3: AND3C > > port map (X(2),X(1),X(0),A3); > > G4: AND3C > > port map (not X(2),X(1),not X(0),A4); > > G5: OR4C > > port map (A1,A2,A3,A4,Z); > > end AND_OR; > > > > architecture MACRO of ones_cnt is > > begin > > C(1) <= MAJ3(A); > > C(2) <= OPAR(A); > > end MACRO; > > > > configuration Trial of ones_cnt is > > for STRUCTURAL > > end for; > > end Trial; > > > > Heres the log report generated by the compiler: > > Started : "Check Syntax". > > Running vhpcomp > > Compiling vhdl file "E:/Xlinx_ISE/workbench/ones_cnt.vhd" in Library > > isim_temp. > > Entity <ones_cnt> compiled. > > Entity <ones_cnt> (Architecture <algorithmic>) compiled. > > ERROR:HDLParsers:3014 - "E:/Xlinx_ISE/workbench/ones_cnt.vhd" Line 55. > > Library unit work is not available in library isim_temp. > > Parsing "AND2_stx.prj": 0.38 > > > > Process "Check Syntax" failed > > > > > > I do not know where am I going here as my VHDL code seems to be ok but > > may be I am missing some tool-specific information here like having > > certain libraries declared or something like that. I am completely new > > to this field and I would sincerely appreciate if someone guides me > > through the very difficult phase of getting started which I suppose you > > guys might have gone through too in your yesteryears. :) > > > > Looking forward to hearing from you, > > > > Best Regards, > > Aijaz. > > Hi Aijaz, I tried but I can't reproduce the error. Can you zip your > project and send it to me? I am nowadays studying VHDL as well and I > have some VHDL expert colleagues here. > > WayneArticle: 105804
HI, thanks for your good replys. So you mean that the FIFO16 should be work fine as they use counters instead of the empty/full flags. Thats good. However I still have the problems that the testbench which writes data and reads the data back sometimes looses some data. The data pattern looks like: FFFF000, AAAA5555, 5555AAAA, 99996666 When this pattern is written and read back every eight time the first two 32 bit words are corrupted and the Error signal is asserted. Is this the problem you mentioned joe with the idelay? THe idelay is configured by an idelayctrl instance. So should i remove this and manually configure the idelay blocks using the INC and CE signals? To which value should I configure the idelay blocks, e.g. how many INC+CE assertions do I need? thx a lot, Heiner Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > Joseph Samson wrote: > > heinerlitz@gmx.de wrote: > > > Hi, > > > I finally got to run the MIG created DDR2 for VIrtex4 devices > > > controller. However I have two problems with the controller: > > > > > > 1. I am observing the ERROR signal which is created by the dataCompare > > > module. It goes high every 8th read pulse. Could this be related to the > > > FIFO16 bug? > > > > I don't have the DDR2 source code with me at home, but I'm pretty sure > > that the FIFO16 use was limited to the write data and the > > address/command. The write data FIFO has 2 different clocks, but the > > FIFO read clock is 90 degrees out of phase with FIFO write clock, so I > > think it is not a problem. I had problems with the address/command FIFO. > > The FIFO would be empty, but the DDR2 controller thought that the FIFO > > had data, so it would repeatedly read the same address. > > In the xxx_ddr2_controller.vhd file, they register the empty signal of > the fifo. And > it should not be registred. If you remove this register level, it works > fine. > > Also, they do use FIFO16 but when they use it with synchronous clock, > they > don't care about the flags, they use a separate counter to know how > many > data are present so there should be no problem. > > Beware if you replace the command fifo. I've replaced it by a simple > SRL fifo > (to gain some space and 1 BRAM), and I was bitten ;) The fifo CANNOT > become > empty for a cycle then become not empty again, if the operation before > and after > the empty were both read in the same row, you'll get one more data than > you > asked for ... > > Also, the timing parameters generated by the MiG tool are overly > conservative ... > (I think they messed up their formula). Check in simulation, you'll see > it waits quite > too loog (sometime twice too much ;) > > > > SylvainArticle: 105805
Antti, Is there anything that you don'know about FPGAs? Unfortunatelly I am not satisfied with couple of IO pins for BSCAN. I need 16 bit pipe transfers. I will just connect my Avnet S3E board (with FX2 on it) to Xilinx S3E starter kit and use the cripled S3E100 (on Avnet board) as a route-through. I wonder if Hydra modules come up with a decent driver (PC and EDK module) for on-board USB2.0 (with a source code of course). Thanks, Guru Antti wrote: > bijoy schrieb: > > > Hi Antti, > > > > In Spartan3E Starter Kit can we use FX2 processor to reporgram the FPGA ? > > > > have some application like that and would like to know whether it works before trying in actual board > > > > rgds bijoy > > sure the FX2 can be used to load the FPGA! > the FX2 and the CPLD are 'duplica' of Xilinx platform cable - you may > have to reprogram the CPLD also in order to have the comms done (or if > you figure out the way the original CPLD code works then you can keep > that). > > There is software available for FX2 that fully emulated Altera USB > blaster - so you could take that firmware, implement simple wire-bypass > in the CPLD and then use Altera Quartus programmer to play back impact > generated SVF/STAPL files to program the FPGA > > AnttiArticle: 105806
HI, you just instantiate the iddr buffer and drive it with a single SDR clock. You dont need the 180phase clk. The idddr then provides the data on the two output data busses. One data value at the positive clk edge and one at the negative clock edge. heinerArticle: 105807
Thanks anticipate ... i have bought ML455 board... but that haven't documentation... someone can help me???? Bye.Article: 105808
Hello Brad, Brad Smallridge wrote: > I infer a Xilinx BRAM with a VHDL constant array. But when I change a single > value in this array, ISE resynthesizes the entire design. There must be a > quicker way. Depending on your target device, you can easily reverse-engeneer the bitstream and update the BRAM values in there directly. I think xilinx themselves provide info about how to do this. I'm sure they do for LUT table values. This may be more worry than you want, though. JBArticle: 105809
Hi Brad, look for Informations about the DATA2MEM tool. Then you can change your Memory contents and generate new Bitfiles in an instant. The documentation is a little poor, but hter's lot's of stuff in this group about it. Have a anice synthesis Eilert Brad Smallridge schrieb: > I infer a Xilinx BRAM with a VHDL constant array. But when I change a single > value in this array, ISE resynthesizes the entire design. There must be a > quicker way. > > Brad Smallridge > aivision > > >Article: 105810
Hi, I want to know how many fields Huffman encoding thoery are used. As I can counted, 1. In Window operating system, similar encoding is used to conpress text files; 2. Text compression in ZIP files; 3. JPEG fram compression; 4. MPEG format compression? which one uses it? Wireless communication? Any other applications? Thank you. WengArticle: 105811
heinerlitz@gmx.de wrote: > HI, > > thanks for your good replys. So you mean that the FIFO16 should be work > fine as they use counters instead of the empty/full flags. Thats good. > > However I still have the problems that the testbench which writes data > and reads the data back sometimes looses some data. The data pattern > looks like: > FFFF000, AAAA5555, 5555AAAA, 99996666 > > When this pattern is written and read back every eight time the first > two 32 bit words are corrupted and the Error signal is asserted. Is > this the problem you mentioned joe with the idelay? > > THe idelay is configured by an idelayctrl instance. So should i remove > this and manually configure the idelay blocks using the INC and CE > signals? To which value should I configure the idelay blocks, e.g. how > many INC+CE assertions do I need? I did not mention any problems with idelay. In fact, I said "The IDELAY part that looks at the data strobes seems to work OK". The signals that I changed were rd_en_rise and rd_en_fall in pattern_compare8.v . I suspect that not everyone will see this circuit misbehave. When it works correctly, it sets the strobes for the delays unique to your board. --- Joe Samson Pixel Velocity > > thx a lot, Heiner > > > > Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > > >>Joseph Samson wrote: >> >>>heinerlitz@gmx.de wrote: >>> >>>>Hi, >>>>I finally got to run the MIG created DDR2 for VIrtex4 devices >>>>controller. However I have two problems with the controller: >>>> >>>>1. I am observing the ERROR signal which is created by the dataCompare >>>>module. It goes high every 8th read pulse. Could this be related to the >>>>FIFO16 bug? >>> >>>I don't have the DDR2 source code with me at home, but I'm pretty sure >>>that the FIFO16 use was limited to the write data and the >>>address/command. The write data FIFO has 2 different clocks, but the >>>FIFO read clock is 90 degrees out of phase with FIFO write clock, so I >>>think it is not a problem. I had problems with the address/command FIFO. >>>The FIFO would be empty, but the DDR2 controller thought that the FIFO >>>had data, so it would repeatedly read the same address. >> >>In the xxx_ddr2_controller.vhd file, they register the empty signal of >>the fifo. And >>it should not be registred. If you remove this register level, it works >>fine. >> >>Also, they do use FIFO16 but when they use it with synchronous clock, >>they >>don't care about the flags, they use a separate counter to know how >>many >>data are present so there should be no problem. >> >>Beware if you replace the command fifo. I've replaced it by a simple >>SRL fifo >>(to gain some space and 1 BRAM), and I was bitten ;) The fifo CANNOT >>become >>empty for a cycle then become not empty again, if the operation before >>and after >>the empty were both read in the same row, you'll get one more data than >>you >>asked for ... >> >>Also, the timing parameters generated by the MiG tool are overly >>conservative ... >>(I think they messed up their formula). Check in simulation, you'll see >>it waits quite >>too loog (sometime twice too much ;) >> >> >> >> Sylvain > >Article: 105812
Hi, AND2, AND2B1, AND2B2 are 3 types of AND2.. When XST infers any one of these 3, schematic editor gives it name as simple AND2.. AND2 : O <= I1 and I0; AND2B1 : O <= I1 and (not I0); ANDB2 : O <= (not I1) and (not I0); So, don't go by naming convention - the functionality will be as you expected. Regards, Krishna bijoy wrote: > Hi I am viewing the RTL schematic generated by the Xilinx ISE (7.1 with SP$)tool for a vhdl statement > > <= '1' when (a = '1' and b = '0') else '0'; > > am seeing in the rtl schematics as 'C' as the output of an AND gate with input to the AND gate as 'A' , 'B'. > > no NOT gate is implemented on the 'B' input ? > > is it a BUG ? > > Thanks in advance > > bijoyArticle: 105813
Weng Tianxiang wrote: > Hi, > I want to know how many fields Huffman encoding thoery are used. > > As I can counted, > 1. In Window operating system, similar encoding is used to conpress > text files; > 2. Text compression in ZIP files; > 3. JPEG fram compression; > 4. MPEG format compression? which one uses it? > > Wireless communication? > > Any other applications? > > Thank you. > > Weng I am sure in JPEG and MPEG.Article: 105814
Hi Bijoy, no, it's a beetle. Because it's so old. :-) In 7.1 the rtl schematics became oversimplified, and had no inverted inputs anymore. I hope the newer versions behave better, but i haven't tested it. have a nice synthesis Eilert bijoy schrieb: > Hi I am viewing the RTL schematic generated by the Xilinx ISE (7.1 with SP$)tool for a vhdl statement > > <= '1' when (a = '1' and b = '0') else '0'; > > am seeing in the rtl schematics as 'C' as the output of an AND gate with input to the AND gate as 'A' , 'B'. > > no NOT gate is implemented on the 'B' input ? > > is it a BUG ? > > Thanks in advance > > bijoyArticle: 105815
Hi Brad, That DATA2MEM tool sound like the way to go, must check it out. I suspect (haven't tried it) you could use the FPGAEditor with a command such as: setattr comp onchip_ram_top/block_ram_1/BU5 INIT_01 0000000000000000000000000000000000000000000000000000000800000f00 This would avoid synthesis and par, somewhat similar to the DATA2MEM tool. It is also probably also worth mentioning that you can put an entry in your UCF file such as: INST "onchip_ram_top/block_ram_1/BU5" INIT_01= 0000000000000000000000000000000000000000000000000000000800000f00; This way you still have to PAR after changes but don't need to resynthesize. I would imagine this would override initialization values set in the hdl. Vivian --Sandbyte backhus wrote: > Hi Brad, > look for Informations about the DATA2MEM tool. > Then you can change your Memory contents and generate new Bitfiles in an > instant. > > The documentation is a little poor, but hter's lot's of stuff in this > group about it. > > Have a anice synthesis > Eilert > > Brad Smallridge schrieb: > >> I infer a Xilinx BRAM with a VHDL constant array. But when I change a >> single value in this array, ISE resynthesizes the entire design. There >> must be a quicker way. >> >> Brad Smallridge >> aivision >> >> >>Article: 105816
jvdh (johannes.vanderhorst@gmail.com) wrote: : This might be slightly OT for an FPGA group, but maybe someone has run : into a similar problem before: : I'd like to connect my FPGA, via JTAG, to my PC, 100m away. Due to a : hazardous environment, putting the PC any closer isn't feasible One approach, nicely agnostic to the deviecs and manifactuers etc, would be to extend the physical JTAG signals with fibre transcievers. I guess that doesn't work for Vref directly... :-) Assuming fibres aren't killed by the radiation...Article: 105817
Hello Heiner, Thanks for your response. I guess this option of IDDR will work for Virtex 4 FPGA. However my FPGA of interest is Virtex II Pro. I am sorry for not mentioning the type of device in my earlier mail. I will appreciate your further suggestions. Kind regards, Venkat. heinerlitz@gmx.de wrote: > HI, > > you just instantiate the iddr buffer and drive it with a single SDR > clock. You dont need the 180phase clk. The idddr then provides the data > on the two output data busses. One data value at the positive clk edge > and one at the negative clock edge. > > heinerArticle: 105818
Hello,
I can give some brief info about fpga's boards with ARM as I did
spent time finding them out previously.
- Non Xilinx : Actel has ARM7 Evaluation Board.
www.actel.com
- ARM provides some evaluation Boards
www.arm.com
- Fujitsu's ARM based SoC design kit based on MB87Q1100.
Google MB87Q1100 and find out.
Thanks
Rao
Vivek Menon wrote:
> Ron wrote:
> > You might have more luck if you *requested* information instead of
> > "requiring" it.
Article: 105819Hi, > I suspect (haven't tried it) you could use the FPGAEditor with a command > such as: > > setattr comp onchip_ram_top/block_ram_1/BU5 INIT_01 > 0000000000000000000000000000000000000000000000000000000800000f00 > > This would avoid synthesis and par, somewhat similar to the DATA2MEM tool. Yet another equivalent possibility would be to do the same on the XDL file and to convert back to the ncd. JBArticle: 105820
Below are directly copied from the library guide: VHDL Instantiation Template -- IFDDRRSE: Double Data Rate Input Register with Sync. Clear, -- Sync. Preset -- and Clock Enable. Virtex-II/II-Pro, Spartan-3 -- Xilinx HDL Libraries Guide version 7.1i IFDDRRSE_inst : IFDDRRSE port map ( Q0 => Q0, -- Posedge data output Q1 => Q1, -- Negedge data output C0 => C0, -- 0 degree clock input C1 => C1, -- 180 degree clock input CE => CE, -- Clock enable input D => D, -- Data input (connect directly to top-level port) R => R, -- Synchronous reset input S => S -- Synchronous preset input ); -- End of IFDDRRSE_inst instantiation Verilog Instantiation Template // IFDDRRSE: Double Data Rate Input Register with Sync. Clear, Sync. // Preset and Clock Enable. Virtex-II/II-Pro, Spartan-3 // Xilinx HDL Libraries Guide version 7.1i IFDDRRSE IFDDRRSE_inst ( .Q0(Q0), // Posedge data output .Q1(Q1), // Negedge data output .C0(C0), // 0 degree clock input .C1(C1), // 180 degree clock input .CE(CE), // Clock enable input .D(D), // Data input (connect directly to top-level port) .R(R), // Synchronous reset input .S(S) // Synchronous preset input ); // End of IFDDRRSE_inst instantiation HTH, Jim http://home.comcast.net/~jimwu88/tools/ Venkat wrote: > Hello Heiner, > Thanks for your response. I guess this option of IDDR will work for > Virtex 4 FPGA. However my FPGA of interest is Virtex II Pro. I am sorry > for not mentioning the type of device in my earlier mail. I will > appreciate your further suggestions. > > Kind regards, > Venkat. > > heinerlitz@gmx.de wrote: > > HI, > > > > you just instantiate the iddr buffer and drive it with a single SDR > > clock. You dont need the 180phase clk. The idddr then provides the data > > on the two output data busses. One data value at the positive clk edge > > and one at the negative clock edge. > > > > heinerArticle: 105821
Guru schrieb: > Antti, > > Is there anything that you don'know about FPGAs? Sure! I know that LatticeXP2 will be LARGE (compared to XP) and has serdes, but I dont know other details :( > Unfortunatelly I am not satisfied with couple of IO pins for BSCAN. I > need 16 bit pipe transfers. I will just connect my Avnet S3E board The BSCAN is pretty much documented and fun to use. > (with FX2 on it) to Xilinx S3E starter kit and use the cripled S3E100 > (on Avnet board) as a route-through. > I wonder if Hydra modules come up with a decent driver (PC and EDK > module) for on-board USB2.0 (with a source code of course). > > Thanks, > > Guru hydraxc modules do come with some USB code of course what is currently available is 1) working standalone application demo for USB Mass Storage class device. eg you plug the USB cable to PC and then the miniSD is visible has removable disk from the PC host. 2) minimal HOST standalone demo, enumerates internal HUB, set hib port on, and reads Device descriptor from external device 3) from Philips is optainable http://www.semiconductors.philips.com/products/connectivity/usb/products/download/ source code for the uclinux host driver, this is however not fully suitable for microblaze-uclinux :( well from this driver here is some terminal log from hydraxc-uclinux: # mount -t usbfs none /proc/bus/usb # cd proc # cd bus # cd usb # cat devices T: Bus=01 Lev=00 Prnt=00 Port=00 Cnt=00 Dev#= 1 Spd=480 MxCh= 1 B: Alloc= 0/800 us ( 0%), #Int= 0, #Iso= 0 D: Ver= 2.00 Cls=09(hub ) Sub=00 Prot=01 MxPS= 8 #Cfgs= 1 P: Vendor=0000 ProdID=0000 Rev= 2.04 S: Product=USB PHCI Root Hub S: SerialNumber=802f7c00 C:* #Ifs= 1 Cfg#= 1 Atr=40 MxPwr= 0mA I: If#= 0 Alt= 0 #EPs= 1 Cls=09(hub ) Sub=00 Prot=00 Driver=hub E: Ad=81(I) Atr=03(Int.) MxPS= 2 Ivl=256ms we do not have this driver fully working (but hopefully will have soon). As of open-source linux driver we are looking for solution (the Philips driver is not available as open-source unfortunatly) As of hardware side the ISP1761 can be connected to EDK system using OPB_EMC and is visible as memory mapped peripheral. The host drivers, well it depends what class you implement for CDC or mass storage there are no PC drivers needed AnttiArticle: 105822
jvdh <johannes.vanderhorst@gmail.com> wrote: > Uwe: > > Isn't there an option to set the JTAG CLK speed in impact? > The speed setting in impact apparently doesn't apply to my Parallel > Cable 3. > > Another option beside the USB Extender is to convert the levels to a > > RS422/485 signal and use a twisted pair cable. The FTDI FT2232 happily generates serial protocols. I have a modified version of Andrew Rogers's xc3sprog thats talks JTAG to XC3S and XCF via FT2232. It knows about JTAG speed. Let me know if you are interested (and willing to give feedback). -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 105823
Hi, I am working with a project from Memec for the Virtex-4 FX12. The directory name has a 7.1 after the name of the project, and when I open it in XPS, it says that it was created with a different version. I'm using 8.1.02i So I let it update, and I get a few warnings, the same three, repeated 4 times. Project Files updated successfully. Now trying to update IP versions... WARNING:MDT - D:\EDK_Projects\V4FX12MM TEMAC Design - 7.1\V4FX12MM_TEMAC_Design\pcores\ll_temac_v1_00_b\data\ll_temac_v2_1_0.mpd line 110 Unknown PORT subproperty VEC[3:0] WARNING:MDT - D:\EDK_Projects\V4FX12MM TEMAC Design - 7.1\V4FX12MM_TEMAC_Design\pcores\opb_v20_v1_10_b\data\opb_v20_v2_1_0.mpd line 51 Unknown PORT subproperty TYPE WARNING:MDT - D:\EDK_Projects\V4FX12MM TEMAC Design - 7.1\V4FX12MM_TEMAC_Design\pcores\opb_v20_v1_10_b\data\opb_v20_v2_1_0.mpd line 53 Unknown PORT subproperty TYPE INFO:MDT - The installed version of EDK tools is 8.1.02, while project was created with version 8.1 Done. After the above line it repeates the errors 3 times. Any insight to how I can fix these errors? I searched this group and saw someone with a similar problem and the replied answer was the look in the /hw folder of the install dir. But I don't know what I should be looking for. As it appears the IPs are in the pcores dir in the project dir? no? Should I try to open it and not update the cores? Thanks for any help!Article: 105824
HI, ok I observed the clk_count_rise and clk_count_fall signals which acctually decide when the data is taken over into the fifos. I had the hope that the value of the above mentioned signals would toggle and that the value would be different if the read out data is corrupt but it isnt. the clk_count signals have always the same value. So still no solution why some of the read out data is corrupted. I really wonder why always the eights data value is corrupt... heiner Joseph Samson schrieb: > heinerlitz@gmx.de wrote: > > HI, > > > > thanks for your good replys. So you mean that the FIFO16 should be work > > fine as they use counters instead of the empty/full flags. Thats good. > > > > However I still have the problems that the testbench which writes data > > and reads the data back sometimes looses some data. The data pattern > > looks like: > > FFFF000, AAAA5555, 5555AAAA, 99996666 > > > > When this pattern is written and read back every eight time the first > > two 32 bit words are corrupted and the Error signal is asserted. Is > > this the problem you mentioned joe with the idelay? > > > > > THe idelay is configured by an idelayctrl instance. So should i remove > > this and manually configure the idelay blocks using the INC and CE > > signals? To which value should I configure the idelay blocks, e.g. how > > many INC+CE assertions do I need? > > > I did not mention any problems with idelay. In fact, I said "The IDELAY > part that looks at the data strobes seems to work OK". The signals that > I changed were rd_en_rise and rd_en_fall in pattern_compare8.v . I > suspect that not everyone will see this circuit misbehave. When it works > correctly, it sets the strobes for the delays unique to your board. > > > --- > Joe Samson > Pixel Velocity > > > > > thx a lot, Heiner > > > > > > > > Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > > > > > >>Joseph Samson wrote: > >> > >>>heinerlitz@gmx.de wrote: > >>> > >>>>Hi, > >>>>I finally got to run the MIG created DDR2 for VIrtex4 devices > >>>>controller. However I have two problems with the controller: > >>>> > >>>>1. I am observing the ERROR signal which is created by the dataCompare > >>>>module. It goes high every 8th read pulse. Could this be related to the > >>>>FIFO16 bug? > >>> > >>>I don't have the DDR2 source code with me at home, but I'm pretty sure > >>>that the FIFO16 use was limited to the write data and the > >>>address/command. The write data FIFO has 2 different clocks, but the > >>>FIFO read clock is 90 degrees out of phase with FIFO write clock, so I > >>>think it is not a problem. I had problems with the address/command FIFO. > >>>The FIFO would be empty, but the DDR2 controller thought that the FIFO > >>>had data, so it would repeatedly read the same address. > >> > >>In the xxx_ddr2_controller.vhd file, they register the empty signal of > >>the fifo. And > >>it should not be registred. If you remove this register level, it works > >>fine. > >> > >>Also, they do use FIFO16 but when they use it with synchronous clock, > >>they > >>don't care about the flags, they use a separate counter to know how > >>many > >>data are present so there should be no problem. > >> > >>Beware if you replace the command fifo. I've replaced it by a simple > >>SRL fifo > >>(to gain some space and 1 BRAM), and I was bitten ;) The fifo CANNOT > >>become > >>empty for a cycle then become not empty again, if the operation before > >>and after > >>the empty were both read in the same row, you'll get one more data than > >>you > >>asked for ... > >> > >>Also, the timing parameters generated by the MiG tool are overly > >>conservative ... > >>(I think they messed up their formula). Check in simulation, you'll see > >>it waits quite > >>too loog (sometime twice too much ;) > >> > >> > >> > >> Sylvain > > > >
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