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Tommy Thorn wrote: > Antti wrote: > >>the first partition must be FAT16, windows selects FAT32 as default >>try reformatting with FAT16 (select FAT in format options) > > > Thanks Antti, I should have known better. > > In my defense, "FAT" is the only option presented to me, but I should > obviously format it in Linux. > > Any help with the original problem? > In the majority of cases, the issue is improper formatting of the CF. So did you try again after reformatting? (Use Linux or mkdosfs to format). /SivaArticle: 109626
Hi all,
I discovered that I _lose messages_ when using an Fast Simplex Link (FSL)
to transfer data from one MB to another using the interruptable macros
putfsl_interruptible and getfsl_interruptible (BTW, I'm using EDK 8.1i
SP2). I'm not losing any messages when I use the non-interruptible
versions (putfsl, getfsl) or when I replace only one interruptible version
with a non-interruptible version.
So in short the following combinations of getfsl and putfsl work:
putfsl, getfsl;
putfsl_interruptible, getfsl;
putfsl, getfsl_interruptible;
The not working combination is:
putfsl_interruptible, getfsl_interruptible;
Does anyone has any idea why this may be the case, and how to fix this
problem?
Below is some example of code that loses messages is the following (Please
note that I omit the programme entry point bits):
-The code for the first MicroBlaze:
char* message = "hello world\r\n";
void hello (void)
{
int i;
xil_printf ("(hello started)\n");
for (i = 0; message[i] != 0; i++)
{
putfsl_interruptible(message[i], 0);
}
putfsl_interruptible(0xFF, 0);
xil_printf ("(hello done)\n");
return;
}
-The code for the second MicroBlaze:
void world (void)
{
xil_printf ("world started \r\n");
unsigned char c;
int message = 0;
getfsl(message, 0);
c = (char) message;
while (c != 0xFF)
{
xil_printf("%c",c);
getfsl_interruptible(message, 0);
c = (char) message;
}
xil_printf ("\r\n");
xil_printf ("world gone \r\n");
return;
}
BTW, I replaced the putfsl_interruptable macro with the following due to
problems with the originally supplied version:
#define putfsl_interruptible(val, id) \
asm volatile ("\n1:\n\tnput\t%0,rfsl" #id "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")
The source for this macro is Sylvain Munaut who posted it in Message-ID:
<444687b5$0$32429$ba620e4c@news.skynet.be>
In Message-ID: <e2bnik$dq317@xco-news.xilinx.com> Austin Lesea from Xilinx
states that this macro seems to be correct.
Cheers
Bernhard
--
William of Ockham, Albert Einstein, and Stephen Hawking walk into a bar.
Bartender: Oh, NO! Not another bloody parallel programming joke.
Article: 109627don't forget : Always reboot (and halt) windows when something goes wrong... around midnight I turn off computer, and on again... now it is ok ... but there is something strange with that usb link...Article: 109628
David Ashley wrote: > Weng Tianxiang wrote: > > Hi David, > > I never use DOS commands and all options are accessable through Xilinx > > ISE window system so that I don't know how to answer any questions > > about it. > > > > Weng > > Aha! So your list was just describing your own way of development, > it wasn't meant as advice as to how best to do development. > > Thanks-- > Dave > > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architecture Hi David, I never said what I have listed is the best one in performance, but it really saves me a lot. I never pay attention to what has already been built in Xilinx ISE. I never spend time doing unnecessary things. What I pay most of my attention to is to write right logic that runs fastest in the market! Thank you, Xilinx engieers, who provide a really reliable platform to let me do my best and make my money and my living. Thank you. WengArticle: 109629
Try http://arstechnica.com/paedia/r/ram_guide/ram_guide.part3-1.html SandeepArticle: 109630
Ben Twijnstra wrote: > Hi KJ, > >> On the SOPC Builder side of things I can flatly state that the tool itself >> is very poor for anything other than the most minimal of 'programmable >> systems on a chip'. > > I was told that this was also recognized by Altera themselves, and that SOPC > Builder will have had a complete overhaul in Quartus II 6.1. The PTF file > will be gone (I vaguely remember a slide mentioning XML combined with > something else as the replacement). > > Having designed and debugged a few SOPC Builder bits and pieces, I can't say > how happy I am that Altera finally took this horribly over-evolved > proof-of-concept code behind the barn and shot it. Kudos to the guys that > kept it going in the meantime, and I'm really curious about the successor. > > As a sidenote, if you run SOPC Builder on Solaris or Linux, you'll cream > your pants over the speed at which the generator runs on those platforms - > the generator is written in Perl and doesn't need the Cygwin emulation > there. I've witnessed tenfold speed improvements on large (30+ components) > designs. > Cygwin is a great piece of work, but there are three things it does badly, all of which hit SOPC Builder. You can get endless trouble if you have more than one installation on the same machine, especially if one application (i.e., Quartus/SOPC Builder) selfishly adds its own copy to your path, and it is slow at creating new processes and working with files (because it has to add Posix semantics on top of Windows). For Quartus/SOPC Builder, Altera would do much better by shipping a native windows perl interpreter - then we would get close to *nix speed. > Best regards, > > > > Ben > > >Article: 109631
Agreed, A Toulouse, Austin Peter Alfke wrote: > Yes, errata are somewhat sensitive information. Different from the > usual marketing spiel, they admit and explain warts. But that's life, > and microprocessors have paved the way to consider errata as facts of > life.. > Our PR folks may not like the idea that the "bad competiton" gets hold > of it, but that would really underestimate their cleverness. They get > it anyhow... > And I think the press has better things to do than run anybody's errata > up the flagpole. > So, there really is no rational reason to treat errata like a state > secret... > Peter Alfke, from home. > ======================== > John_H wrote: > >>zwsdotcom@gmail.com wrote: >> >>>All this is a bit moot anyway. Xilinx has no rational reason to make >>>people jump through these flaming hoops to get basic information about >>>their parts. If they want people to go with other vendors whose >>>procedures are less broken, they're going the right way about it. >> >> >>Are errata considered at least *slightly* sensitive information? It's >>true that people can falsify registration information to get the info, >>but those getting the errata (as opposed to the data sheet) should agree >>to some specific issues regarding the errata; a good way to track that >>the agreement was accepted is with a registration. >> >>While I understand there should be nothing like the experience you've >>seen to stand between an engineer and an errata, should this information >>be made available without condition? Ar is it just that the hoops >>should be simpler? > >Article: 109632
Peter Alfke schrieb: > Yes, errata are somewhat sensitive information. Different from the > usual marketing spiel, they admit and explain warts. But that's life, > and microprocessors have paved the way to consider errata as facts of > life.. > Our PR folks may not like the idea that the "bad competiton" gets hold > of it, but that would really underestimate their cleverness. They get > it anyhow... > And I think the press has better things to do than run anybody's errata > up the flagpole. > So, there really is no rational reason to treat errata like a state > secret... > Peter Alfke, from home. > ======================== there is one more issue to it - the errata (some errata docs) are available after click through kind of online NDA, but the documents itself have no NDA information in it, eg there is no notice that the document should be treated as if it is under NDA. There is at least some danger here, namly if your fellow engineer saves this document on some public download area in your company, or gives you a printed of copy of the errata document, then you are not aware that the original document was actually only available under online NDA - those if you make public comments on something related to that document then this could be classified as NDA infirgment - but you had no way knowing that the docuement was initialy classified. So IMHO the online NDA for the errata sheets is nonsense, either really NDA (properly signed!) and proper notice on the docs that are under NDA or then open access to the errata sheets. AnttiArticle: 109633
Hi just some results for LatticeMico32: * no cache * code and data in Block RAMs testing with software loop sw r0,r0,0x100 bri -1 this loop executes in 28 system clock cycles! simulation done with Xilinx ISE built-in simulator ISIM, using coregen for addsub and block RAM components. Antti PS as much as I see Lattice is at time of writing violating GPL license or does anyone know where to download the GPL licensed source code of the LatticeMico32 GNU toolchain !?Article: 109634
bart schrieb: > it's my humble understanding that Mico32 is truly RTL, i.e. we do not > use any library elements, so it should be portable. (although, of > course, we'd like for you to buy our chips!) > rgds, > Bart Borosky, Lattice, online marketing manager > > > > Source yes, but not RTL. My guess it's lots of instantiated primitives, > > thus not portable. Bart, please look at http://latticeblogs.typepad.com/frontier/2006/09/soft_processor_.html#comments its full of adult avertizing! I was about to post a comment there, but when I see that spam there... brr! AnttiArticle: 109635
Is there something I must do first before I copy or move a project to another place on my computer?Article: 109636
Gery schrieb: > Is there something I must do first before I copy or move a project to > another place on my computer? make a backup! :) in 8.2 things seem to be getting better. I have succesfully cloned ISE 8.2 (even with EDK as subproject) into fresh empty directories, and the newly copied project worked without any need for any fixup. this may not always be so depending on your project so just make a backup, then copy files to new location and try it out AnttiArticle: 109637
First I made a copy of my project folder and then I started to modify the project in the new folder. Then I noticed that ISE had made changes in the original project folder too. So I will follow your advice of making a backup before. "Antti" <Antti.Lukats@xilant.com> wrote in message news:1159786826.477312.155960@c28g2000cwb.googlegroups.com... > Gery schrieb: > >> Is there something I must do first before I copy or move a project to >> another place on my computer? > > make a backup! :) > > in 8.2 things seem to be getting better. > I have succesfully cloned ISE 8.2 (even with EDK as subproject) > into fresh empty directories, and the newly copied project > worked without any need for any fixup. > > this may not always be so depending on your project so just make > a backup, then copy files to new location and try it out > > Antti >Article: 109638
Gery schrieb: > First I made a copy of my project folder and then I started to modify the > project in the new folder. Then I noticed that ISE had made changes in the > original project folder too. > > > > So I will follow your advice of making a backup before. > > > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1159786826.477312.155960@c28g2000cwb.googlegroups.com... > > Gery schrieb: > > > >> Is there something I must do first before I copy or move a project to > >> another place on my computer? > > > > make a backup! :) > > > > in 8.2 things seem to be getting better. > > I have succesfully cloned ISE 8.2 (even with EDK as subproject) > > into fresh empty directories, and the newly copied project > > worked without any need for any fixup. > > > > this may not always be so depending on your project so just make > > a backup, then copy files to new location and try it out > > > > Antti > > it depends how files are added to the original project, if they use absolute path, then the cloned project would reference them from old location. if you have installed Lattice LatticeMico32 then in directory C:\LatticeMico32\MicoSystem\gtools\bin is a text file editise.txt it talks how to use the iseEdit.tcl script to import and export setting from Xilinx .ISE files AnttiArticle: 109639
Stefan Tillich wrote: > Hi, > > I'm investigating the possibility to replace an Spartan-2E (xc2s400e) > with an Spartan-3E (xc3s1200e) device on a PCB. > > The core voltage drops from 1.8V to 1.2V. Has anyone experience > regarding the footprint differences (easy/hard/impossible to adapt) and > any other differences which must be taken into account? > > Regards, > > Stefan Read the FPGA configuration section CLOSELY. The JTAG pins and the dedicated configuration pins are powered from VCCAUX (2.5V). The other non-dedicated configuration pins are powered from Bank2 VCCO pins. I know of two designs this was over looked (1 was mine !!!) and it did cause problems that needed a board re-layout. My design was drawing MUCH more current than it should have and I tracked it down to this. I wish Xilinx would put out a "Gottcha FAQ" that have the top changes from the previous family that will point out problems when moving to the new family.Article: 109640
Hi Antti, have you any idea why it is that slow? Branch penalty? Or is the write that slow? Does the performance improve with caches on? (I have not looked closely at Mico32 yet, maybe it is intended to only be used with caches?) Regarding the GPL: I think it is sufficient if they clearly say that the softare is GPL-licensed and if they provide you the source-code on request. So they would be only violating the license if you ask them to provide you the source-code and they say "No". Once you have the source-code, you are free to publish it yourself on a web side (I am sure, you will ;-) Thomas www.entner-electronics.com "Antti" <Antti.Lukats@xilant.com> schrieb im Newsbeitrag news:1159784088.316718.15260@i42g2000cwa.googlegroups.com... > Hi > > just some results for LatticeMico32: > * no cache > * code and data in Block RAMs > > testing with software loop > > sw r0,r0,0x100 > bri -1 > > this loop executes in 28 system clock cycles! > > simulation done with Xilinx ISE built-in simulator ISIM, > using coregen for addsub and block RAM components. > > Antti > PS as much as I see Lattice is at time of writing violating GPL license > or does anyone know where to download the GPL licensed source code of > the LatticeMico32 GNU toolchain !? >Article: 109641
> > have you any idea why it is that slow? Branch penalty? Or is the write that > slow? Does the performance improve with caches on? (I have not looked > closely at Mico32 yet, maybe it is intended to only be used with caches?) You really do need to enable caches if you want high performance, then you should be able to get near single cycle execution (i.e. considering branch penalties, cache refills etc). Cheers, JonArticle: 109642
Jon Beniston schrieb: > > > > have you any idea why it is that slow? Branch penalty? Or is the write that > > slow? Does the performance improve with caches on? (I have not looked > > closely at Mico32 yet, maybe it is intended to only be used with caches?) > > You really do need to enable caches if you want high performance, then > you should be able to get near single cycle execution (i.e. considering > branch penalties, cache refills etc). > > Cheers, > Jon well if the only memories are on chip Block RAMs then caches should not be needed, for Xilinx MicroBlaze LMB and PPC OCM buses the BRAMs work like always_hit cache memories. on LM32 all memories are on Wishbone bus making the access to BRAM based memory block slower than the access to external memory (assuming cache hit). LM32 does fit nicely into small XP devices like XP3, but only without cache so the requirement to have always caches to achive any normal clock-per cycle ration seems like severly limiting factor for LM32 OpenFire (opensource MicroBlaze clone) would run in Lattice silicon way faster then then LM32 (if execution from on-chip memory is compared) AnttiArticle: 109643
I have a Xilinx EDK based design for a Virtex II Pro using the PowerPC Processor. The PPC subsystem from EDK is a submodule of an ISE based schematic design. There are about 7 cores around the PPC and all was working fine. Then I added a second GPIO for some input lines and it won't run at all anymore. So, I want to add some timing constraints for the clocks. However when I do so ISE complains; I added these lines to the UCF file: NET "sys_clk_s" TNM_NET = "sys_clk_s"; TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" 10 ns HIGH 5; ISE says it can't find sys_clk_s in the design. So I tried these variations of the net name (PPD_DDR is the EDK project name): PPC_DDR/sys_clk_s PPC_DDR\sys_clk_s PPC_DDR_stub/sys_clk_s PPC_DDR_stub\sys_clk_s all with the same result. How am I supposed to refer to a net in the EDK design in the ISE .ucf file?Article: 109644
Hi all, a quick update from my side. Testing has revealed that we seem to do something wrong in our `interrupt when data available' code for the FSL. When disabling the generation of interrupts the putfsl_interruptible and getfsl_interruptible macros work. I'm puzzled why interrupt generation should result in a loss of messages on the FSL. Does anybody has an idea why this may be the case? Cheers Bernhard -- William of Ockham, Albert Einstein, and Stephen Hawking walk into a bar. Bartender: Oh, NO! Not another bloody parallel programming joke.Article: 109645
Antti. > > well if the only memories are on chip Block RAMs then caches should not > be needed, for Xilinx MicroBlaze LMB and PPC OCM buses the BRAMs work > like always_hit cache memories. > > on LM32 all memories are on Wishbone bus making the access to BRAM > based memory block slower than the access to external memory (assuming > cache hit). This is why it is relatively slow. > LM32 does fit nicely into small XP devices like XP3, but only without > cache so the requirement to have always caches to achive any normal > clock-per cycle ration seems like severly limiting factor for LM32 If you look through the RTL, there is some support for this. I'm sure Lattice will enable it via the GUI in a latter version. Cheers, JonArticle: 109646
Jon Beniston schrieb: > Antti. > > > > well if the only memories are on chip Block RAMs then caches should not > > be needed, for Xilinx MicroBlaze LMB and PPC OCM buses the BRAMs work > > like always_hit cache memories. > > > > on LM32 all memories are on Wishbone bus making the access to BRAM > > based memory block slower than the access to external memory (assuming > > cache hit). > > This is why it is relatively slow. > > > LM32 does fit nicely into small XP devices like XP3, but only without > > cache so the requirement to have always caches to achive any normal > > clock-per cycle ration seems like severly limiting factor for LM32 > > If you look through the RTL, there is some support for this. I'm sure > Lattice will enable it via the GUI in a latter version. > > Cheers, > Jon lets hope the local-memory interface will be available and documented without it (and no cache) the performance is really bad. I have it now running in Virtex-4 doing a maximum speed loop incrementing a register and writing it to GPIO complete program as .COE for Xilinx coregen: memory_initialization_radix=16; memory_initialization_vector= 98000000, B8000800, 34210001, 5801E000, E3FFFFFE, 2800E000; xor r0,r0,r0 mv r1,r0 addi r1,r1,1 sw (r0+0xE000),r1 ; this is short store to GPIO base bi -2 This loop emits 181KHz on GPIO(0) at 12MHz system clock, so for 100Mhz clock the max IO toggle rate would be 1.5MHz :( AnttiArticle: 109647
Hi, I'm working on interfacing I2S audio and am new at doing this. Could someone describe how I2S serial data (20-bit left justified format) is converted to parallel format and the Channel status, Valid and Z bits are generated. Any links to VHDL/Verilog code would also be of great help. Thanks, cbrArticle: 109648
cbr_929rr schrieb: > Hi, > I'm working on interfacing I2S audio and am new at doing this. Could > someone describe how I2S serial data (20-bit left justified format) is > converted to parallel format and the Channel status, Valid and Z bits > are generated. Any links to VHDL/Verilog code would also be of great > help. > > Thanks, > cbr google: i2s verilog after 12 seconds you are there: http://www.opencores.org:8080/projects.cgi/web/i2s_interface/overview is it really so hard to find that you have to ask? AnttiArticle: 109649
Thanks for the quick reply. The link seems to be working now but I've had trouble accessing opencores even a few minutes ago. I am not able to find info on how to generate the control bits in the description or the code. It would be very helpful if someone could describe this. Thanks, Cbr Antti wrote: > cbr_929rr schrieb: > > > Hi, > > I'm working on interfacing I2S audio and am new at doing this. Could > > someone describe how I2S serial data (20-bit left justified format) is > > converted to parallel format and the Channel status, Valid and Z bits > > are generated. Any links to VHDL/Verilog code would also be of great > > help. > > > > Thanks, > > cbr > > google: i2s verilog > > after 12 seconds you are there: > > http://www.opencores.org:8080/projects.cgi/web/i2s_interface/overview > > is it really so hard to find that you have to ask? > > Antti
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