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pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > manu <manuel.pezzin@free.fr> wrote: > >>Hello, >>for the moment, I use SVN to manage different versions of te VHDL code >>of my projects. >>I'd like to manage my xilinx projects based on my VHDL code too. >>Until now, I just put the <project>.ise and <project>.ucf files under >>version control and it was enough to be rebuild the whole project. >>Now, I've added an embedded processor to my ISE design and I'm a bit >>confused because there a huge set of automatically generated files. I'd >>like to keep under version control just the minimum set of files >>required to rebuild the whole project. I think there's at least the >><project_up>.xmp, <project_up>.mhs and <project_up>.mss files, but is it >>enough ? >>Any idea ? > > > Use: ls -uAlF ,ie the last access time of the file(s). Quite hand sometimes > to find out which files that are actually used. > > might differ for posix systems. > .xmp .mhs and .mss is enough to rebuild the edk part. Don't forget any customized linkerscripts/makefiles and, of course, the software source files. FrankArticle: 105526
Guys, I'm looking at using some MGT tiles in which just the transmitter is used. >From the user guide:- Powering Unused Transceivers Since there are clocking resources for each MGT tile that are powered from the AVCCAUXRXB and AVCCAUXMGT, there must be careful placement of used/unused MGTs to reduce the amount of power pins that must be filtered. From this, and if I don't use any receivers in the column, I deduce that I can leave AVCCAUXRXA unfiltered. Right? Ta, Syms.Article: 105527
Hi Jan, What I want is not let Xilinx ISE to generate a state machine code for me, but I want ISE to print a flow graph of a state machine written in VHDL. Thank you. WengArticle: 105528
Hi, Does anyone here have experience with the ADC08D1500 Dev board from National Semiconductor?? When I contacted NS, they in turn asked me to contact Xilinx and I am not sure whom to contact regarding the FPGA design on the NS board. Any suggestions?? Can the Xilinx folk on this grp help?? Vivek Vivek Menon wrote: > Hi, > I am trying to implement a correlator block in a Virtex-4 FPGA. This > FPGA is connected to an ADC08D1500 chip and the board is set up such > that 4096 samples are collected and the 8-bit data is sent to the USB > controller which in turn serializes it and sends it to the host PC. > Initially I thought of going ahead with the bit correlator, but that's > not what I want. I want a 2 input corrrelator that correlates the data. > Let me know if anyone has a sample code or has experience working with > National Semiconductor ADC08D1500 dev board. > Thanks, > VivekArticle: 105529
Antti wrote: > Subhasri krishnan schrieb: > > > Hi, > > Our latest prototype board doesnt produce any output and even a simple > [] > > The status of GTS_CFG_B and GWE are different. Is this of significance? > > > > Thanks > > Subhasri.K > > in your log for failing there is also > > DONEIN input from DONE pin : 0 > > meaning the FPGA is not configured at all, so first troubleshoot until > you get done=1 > > then look further. > the GWE is also important, but start troubleshooting done=0 issue Hi, I thought so too. That the FPGA isnot configured. But what does this mean? INFO:iMPACT:580 - '1':Checking done pin ....done. 'done' pin has gone high? - Thanks SubhasriArticle: 105530
Dear Jan, This part is not a problem at all. What I need to do is to keep the number of 2Khz pulses same as the main 50Hz changes. In perfect condition there are fourty 2Khz cycles within one 50Hz period (20ms/500us). When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also chance accordingly to stay in lock. My system clock is 60MHz. I implemented a JK phase detector, a K-counter and a DCO in order to generate 2KHz pulses and this system operates at system clock. The output locks to exact 50Hz very quickly (fed from signal generator), but when I change the reference clock to, lets say, 50.1Hz it starts drifting. Any help appreciated. Many thanks, Rasit Jan Panteltje wrote: > On a sunny day (25 Jul 2006 03:34:12 -0700) it happened "raso" > <rasit.sahin@yahoo.co.uk> wrote in > <1153823652.202609.67390@m79g2000cwm.googlegroups.com>: > > >Hello everyone, > > > >I would like to ask if it is possible to generate 2Khz clock signal > >from 50Hz main frequency > > It is important to filter the mains frequency first from spikes and the like. > Then perhaps create a pulse at zero crossing to drive the PLL.Article: 105531
On a sunny day (25 Jul 2006 07:45:49 -0700) it happened "raso" <rasit.sahin@yahoo.co.uk> wrote in <1153838749.560177.182570@b28g2000cwb.googlegroups.com>: >Dear Jan, > >This part is not a problem at all. > >What I need to do is to keep the number of 2Khz pulses >same as the main 50Hz changes. You mean per 50 Hz period. >In perfect condition >there are fourty 2Khz cycles within one 50Hz period (20ms/500us). >When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also >chance accordingly to stay in lock. Yes. >My system clock is 60MHz. I implemented a JK phase detector, a >K-counter and a DCO in order to generate 2KHz pulses and this system >operates at system clock. The >output locks to exact 50Hz very quickly (fed from signal generator), >but when I change the reference clock to, lets say, 50.1Hz it starts >drifting. Well, I dunno, but I did something like that with 4046 PLL in the 1980ties, divide the 2 kHz to 100 Hz, compare with 100Hz zero crossing derived filtered mains pulses. The issue is the loop filter (lock in range and stability) and loop gain. You need to read up on PLL design perhaps. All I know :-)Article: 105532
Thanks, I figured it out. My c-programming is rusty...I had a different error, that once fixed solved the problem. Siva Velusamy wrote: > > group). I'm trying to write C-code (within Xilinx Platform Studio) to > > determine the remainder after an integer division. So if I say > > > > num = 13/10; > > rem = 13%10; > > > > then num = 1 and rem = 3. > > > > I'm getting an error stating "invalid operands to binary %" when I try > > to build. > > You might want to check if your code compiles fine on an Intel machine. > '%' as an operation only makes sense for integers. > > > > > What I surmise is that % is trying to convert to a binary format rather > > than obtaining the desired remainder result. I would also assume that > > I need to include the correct header file in order to perform the > > remainder operation. > > If num & rem are int's, then you don't need any headers. > > > > > However, I'm having trouble determining what math functions are > > available w/in microblaze and the associated symbols needed to perform > > desired functions (i.e., how to determine an integer remainder). > > > > When I'm configuring microblaze in fpga hardware, should I use floating > > point? I can't find any math include file under > > <design>/microblaze_0/include. > > > > That depends on whether you need the hardware FPU or not. The GNU > includes are typically in $XILINX_EDK/gnu > > /SArticle: 105533
raso schrieb: > What I need to do is to keep the number of 2Khz pulses > same as the main 50Hz changes. In perfect condition > there are fourty 2Khz cycles within one 50Hz period (20ms/500us). > When 50Hz changes (+/- 0.5Hz), 2KHz pulse period should also > chance accordingly to stay in lock. Sure, otherwise it wouldnt be a PLL. But remember, 0.1 Hz change from 50 Hz is 1/500 = 2 promille = 2000 ppm. Is the pull range of the PLL wide enough? Try changes of +/-50 ppm and see how it works. Than increase the deviation. Regards FalkArticle: 105534
> I know some folx here have pretty good idea as to what might be > possible with FPGAs, > as far FFT/DCTs are concerned. Do you think a board can designed (price > does NOT matter) > that can rediacally improve the situation ? I talked to DivX and Nero last year about building an accelerator card for doing their encoding. They were both very excited at the idea. Unfortunately, the company I work for decided not to pursue that path. I think it would be a very fun project. I've done JPEG encoding on FPGA boards before. It took about three months of development time for one engineer. I assume MPEG2 would be three times that. MPEG2 might need some SRAM for the frame buffer. Concerning MPEG4, well, that's a whole other beast. MPEG4 uses wavelets, which are scatter-gather algorithm based. Those algorithms are a pain in the butt to code on FPGA. And the only way you would ever make them faster than a CPU is if you had some fast SRAM and a lot of it. Incidentally, I've seen some MPEG4 cores for sale. You would not want to develop that yourself. Concerning a board, well, dang it people, this is what I've been crying for for years! Just build a simple board with four Spartan3 chips in a loop. Put some cheap SRAM and DRAM sockets on there with two PCIe 4x controller chips and we have done deal. It would cost $0.5 Mil to develop the board, a fast driver, and get all the bugs out, but in the end you could sell millions of the "general purpose accelerator card" for $300 a piece. Various software vendors would ship modules for use with that board when detected.Article: 105535
Hi, I am having problems synthesizing the fft module generated for Virtex-4 xc4vlx15. The files generated are only for simulation. Any suggestions?? VivekArticle: 105536
Yes, but...
Assuming the signals that those concurrent assignments depend on are
driven from clocked processes, they do not update until after the
clock, which means they are the registered (delayed) values.
Also, see below:
process (clk) is
begin
if rising_edge(clk) then
var := (var - 1) mod var_limit;
out1 <= var = 0; -- registered comparison of combinatorial var
(i.e. var - 1) with 0
end if;
out2 <= var = 0; -- combinatorial comparison of registered var with 0
end process;
Note that both out1 and out2 have the same cycle-accurate behavior.
Note also that if both out1 and out2 exist, Synplify will combine them
and use out1 for both.
Andy
KJ wrote:
> Andy wrote:
> > With variables, you don't have to wait an extra clock in single process
> > descriptions.
> >
> With concurrent signal assignments that are outside of the process you
> don't have to wait an extra clock either.
>
> KJ
Article: 105537"Brannon" <brannonking@yahoo.com> wrote in message news:1153842715.347358.213790@m73g2000cwd.googlegroups.com... <snip> > Concerning a board, well, dang it people, this is what I've been crying > for for years! Just build a simple board with four Spartan3 chips in a > loop. Put some cheap SRAM and DRAM sockets on there with two PCIe 4x > controller chips and we have done deal. It would cost $0.5 Mil to > develop the board, a fast driver, and get all the bugs out, but in the > end you could sell millions of the "general purpose accelerator card" > for $300 a piece. Various software vendors would ship modules for use > with that board when detected. Just curious: How would one connect two PCIe 4x ports in one card? Or would PICe 8x (or PCI 16x) be a better way to go?Article: 105538
Oh, and BTW, there's an error in the user guide. UG076 v3.0 fig. D-2 shows a LM385 with 100mA going through it. That's bad, abs max is 30mA. Cheers, Syms. http://cache.national.com/ds/LM/LM185-1.2.pdf "Symon" <symon_brewer@hotmail.com> wrote in message news:44c613aa$1_1@x-privat.org... > Guys, > I'm looking at using some MGT tiles in which just the transmitter is used. > > From the user guide:- > > Powering Unused Transceivers > Since there are clocking resources for each MGT tile that are powered from > the AVCCAUXRXB and AVCCAUXMGT, there must be careful placement of > used/unused MGTs to reduce the amount of power pins that must be filtered. > > From this, and if I don't use any receivers in the column, I deduce that I > can leave AVCCAUXRXA unfiltered. Right? > > Ta, Syms. >Article: 105539
> I think it would be a very fun project. I've done JPEG encoding on FPGA > boards before. It took about three months of development time for one > engineer. I assume MPEG2 would be three times that. MPEG2 might need > some SRAM for the frame buffer. > For a simple progressive encoder that's probably about right. Add all the b-frame/interlace field/frame coding tools and things get rather more hairy. A large RAM is very likely required to store the reference frames for motion estimation. > Concerning MPEG4, well, that's a whole other beast. MPEG4 uses > wavelets, which are scatter-gather algorithm based. Those algorithms > are a pain in the butt to code on FPGA. And the only way you would ever > make them faster than a CPU is if you had some fast SRAM and a lot of > it. Incidentally, I've seen some MPEG4 cores for sale. You would not > want to develop that yourself. > I think the majority of applications use the simple and advanced simple profiles where wavelets are not required. Not sure that they are needed in main profile either. Still, there are plenty of scary algorithms in mpeg-4 left to implement. Of course for an encoder you can ignore whatever algorithms you don't like, but quality inevitably suffers if you do that too often. > Concerning a board, well, dang it people, this is what I've been crying > for for years! Just build a simple board with four Spartan3 chips in a > loop. Put some cheap SRAM and DRAM sockets on there with two PCIe 4x > controller chips and we have done deal. It would cost $0.5 Mil to > develop the board, a fast driver, and get all the bugs out, but in the > end you could sell millions of the "general purpose accelerator card" > for $300 a piece. Various software vendors would ship modules for use > with that board when detected. > Fully custom encoders are incredibly complex beasts - professional ones often have tens of DSP's and FPGA's on board. I think a board which accelerated motion estimation and left residual coding (and thus the rate distortion optimisation process and the majority of differences between codec standards) up to the CPU would be a reasonable solution. Cheers, AndyArticle: 105540
Using variables for the register itself also means that the register can be read back internally, which you can't do with the output port signal. Variable assignment/update overhead during simulation is less than that of signals. Using variables for the registers, then a final output signal assignment from the variable (within the process) removes the need for a separate combo process or concurrent assignment, and the simulation overhead involved with that too. Andy KJ wrote: > Mike Treseler wrote: > > Simpler because *all* of my registers are variables. > > There is no need to interpose a signal. Just > > > > my_out_port <= my_out_reg_v; > > > > > I'll go with just 'different' on this one, it doesn't seem better, > worse or simpler to me since the only reason for that line of code is > because the probably more logically complicated assignment that occurs > to the variable could just as easily have assigned it to the output > signal in the first place. But there are times when even I use > variables inside a clocked process too so I don't really disagree. > > KJArticle: 105541
Andy wrote: > Using variables for the register itself also means that the register > can be read back internally, which you can't do with the output port > signal. > We were discussing true outputs signals (i.e. not needed internally). If the signal is needed internally than the coding effort is identical, in one case you declare a signal, the other you declare a variable. > Variable assignment/update overhead during simulation is less than that > of signals. > Agreed, I measured something around 10% hit for using signals with some sample code a while back. Assuming that the actual simulation time itself is ~10-25% of the total sim/analyze/debug/fix cycle time (the other 75-90% being analyzing, debugging, fixing) than this speed up saves you about 1-2.5% of the total amount of time you spend getting a design working. Whether or not those numbers are representative of what you see or not, the point is that the additional amount of test coverage that one gets is not inversely proportional to actual simulation time. > Using variables for the registers, then a final output signal > assignment from the variable (within the process) removes the need for > a separate combo process or concurrent assignment, But the coding effort is the same, it's just a question of whether you put that code inside a process or out in a concurrent assignment. There's nothing inherently 'pure' or 'better' or anything about whether everything fits into one process or not. In this particular case you're comparing code that is darn near equivalent no matter what metric you choose to grade it against. > and the simulation overhead involved with that too. Agreed previously. KJArticle: 105542
Andy wrote: > Yes, but... > > Assuming the signals that those concurrent assignments depend on are > driven from clocked processes, they do not update until after the > clock, which means they are the registered (delayed) values. So what? I typically don't care about waiting a delta cycle delay, when you put them up on a wave window to debug they all happen at the same time. <snip> > Note that both out1 and out2 have the same cycle-accurate behavior. > Note also that if both out1 and out2 exist, Synplify will combine them > and use out1 for both. And this can be written in a functionally equivalent manner using a process and concurrent assignments and it will synthesize to the exact same thing....equivalent. KJArticle: 105543
KJ wrote:
> Andy wrote:
>> Using variables for the register itself also means that the register
>> can be read back internally, which you can't do with the output port
>> signal.
>>
> We were discussing true outputs signals (i.e. not needed internally).
That's not what I was talking about.
I use output registers as working registers as well.
search for serial_out_v in http://home.comcast.net/~mike_treseler/uart.vhd
for an example.
-- Mike Treseler
Article: 105544Hi, I have a problem with my Spartan-3 Starter Board from Digilent (FPGA xc3s400-5ft256). The clock (at pin T9) is always HIGH so the combinational logic works well but obviously the sequential logic doesn't work (flip-flops don't transition). The first thing I did when I bought the board was check it with s3demo and it worked fine, but later (I didn't change anything), after the first programing clycles the problem arose. The oscillator on the board (50MHz) works well, I think the problem is in the FPGA itself or with de tools (I use ISE 8.1i without Service Packs). Any idea? Sorry for my poor english. Thanks, JaviArticle: 105545
Hi All, I'm trying to create a serial link operating at 2.5Gbps or higher using all 8 MGTs on the ML321 board. I modified a code that was used to create a 8 MGT link on a ML310 board. (Changed the MGT,Phase align, Clock instantiations/locations in the ucf file, and changed references in the verilog code accordingly) The Xilinx University Program's "Using High Speed Serial Links using Aurora IP' was used as a starting point. The code was modified so that a 1 MGT aurora module is instantiated 8 times I keep getting these errors while trying to place & route in ISE: ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has to be PAD41 or PAD237 I've checked to make sure that clock & MGTs are defined correctly in the ucf file, and referenced appropriately in the verilog code. The code seems to work on the ML310 board. Any ideas on what could cause such an error and how I can fix it? Thanks, BilluArticle: 105546
raso wrote: >Hello everyone, > >I would like to ask if it is possible to generate 2Khz clock signal >from 50Hz main frequency >using an ADPLL. I have tried SN297 circuit implementation, but couldn't >achieve it. > > The 74LS297 has a VERY narrow lock range, compared to traditional analog PLL's. It is generally a fraction of a percent, but I think there is a setting that gives you a couple percent range. It works fine for syncing between a data source running on one xtal clock, from another xtal clock. You would need a digital clock (quartz crystal) that is at some multiple of 50 Hz (not too hard). Then, you'd need a couple of long counter chains to do the divide down. Are you using an HLL library version of the 74LS297 circuit? If so, where did you get it? I happen to use the real TI chip in one device I built, and a synthesizable version might be good to know about. JonArticle: 105547
Mike Treseler wrote: > That's not what I was talking about. > I use output registers as working registers as well. > Actually at the time, we were just talking about output registers specifically. <Pasting from 4 up in this thread> ** Mike said ** > Output register variable values > are assigned directly to out ports. ** KJ said *** And this is better (or just different) than output register signals values being assigned to out ports? <Pasting from 3 up in this thread> ** Mike said ** > Simpler because *all* of my registers are variables. > There is no need to interpose a signal. Just > my_out_port <= my_out_reg_v; ** KJ said ** I'll go with just 'different' on this one, it doesn't seem... ---- I think we've beaten this one over the head enough, back to woyk. KJArticle: 105548
Ok, I'm going to answer myself. The solution is to use a IBUFG component from Xilinx Library Unisim, but Why? Very interesting issue... I'm investigating this more deeply. Javi ha escrito: > Hi, > > I have a problem with my Spartan-3 Starter Board from Digilent (FPGA > xc3s400-5ft256). The clock (at pin T9) is always HIGH so the > combinational logic works well but obviously the sequential logic > doesn't work (flip-flops don't transition). > > The first thing I did when I bought the board was check it with s3demo > and it worked fine, but later (I didn't change anything), after the > first programing clycles the problem arose. > > The oscillator on the board (50MHz) works well, I think the problem is > in the FPGA itself or with de tools (I use ISE 8.1i without Service > Packs). Any idea? > > Sorry for my poor english. > > Thanks, > JaviArticle: 105549
billu schrieb: > I'm trying to create a serial link operating at 2.5Gbps or higher using > all 8 MGTs on the ML321 board. I modified a code that was used to > create a 8 MGT link on a ML310 board. (Changed the MGT,Phase align, > I keep getting these errors while trying to place & route in ISE: > > ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has > to be PAD41 or PAD237 > ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has > to be PAD41 or PAD237 > ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has > to be PAD41 or PAD237 > ERROR:Place:482 - Bref comp BOTTOM_BREF_CLK_P locked incorrectly. Has > to be PAD41 or PAD237 > > I've checked to make sure that clock & MGTs are defined correctly in > the ucf file, and referenced appropriately in the verilog code. The > code seems to work on the ML310 board. Any ideas on what could cause > such an error and how I can fix it? Looks like you mixed up the top/botton MGTs and the corresponding BREF_CLKs. Remember, those are very dedicaded low jitter clocks with very resticted conectivity. Check again. Regards Falk
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