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Thanks for your answers!Article: 81026
Hi everyone,
why doesn't this synthesize:
architecture Behavioral of datacontroller is
type states is std_logic_vector(4 downto 0);
constant stateStart : states := "00001";
constant stateWait : states := "00010";
constant stateTrigger : states := "00100";
constant stateHold : states := "01000";
constant stateRead : states := "10000";
signal holdoff : std_logic;
signal holdoff_counter_enable, holdoff_counter_reset : std_logic;
component counter19bit
Port ( clk, ce, reset : in std_logic;
preset : in std_logic_vector(19 downto 0);
c : out std_logic;
q : out std_logic_vector(18 downto 0));
end component;
begin
[SNIP]
It's directly taken from the book "VHDL made easy".
I'm using Xilinx Webpack 6.3i!
Thanks
Preben Holm
Article: 81027Mike Treseler wrote: > >>WARNING:Xst:819 - C:/XilinxProjects/DigScope/counter11bit.vhd line 21: >>The following signals are missing in the process sensitivity list: >> preset. > > >>I don't understand why this signal should be in the sensitivity-list! > > > It shouldn't. Yes it should. Take a close look at the code. > Ignore or disarm the warning. The warning can be safely ignored for synthesis (at least with all synthesis tools I have seen). And assuming preset never changes, it can be safely ignored for simulation. But if preset does change, the simulation will not match the hardware. The correct fix is to write the code correctly, not ignore the the warnings. Laurent has the correct fix. -- My real email is akamail.com@dclark (or something like that).Article: 81028
Hi, list,
I got a few questions when I was using the XILINX webpack software for a
homebrew small project. I appreciate your answers.
1. Will the software try to use a global clock network to route a non-clock
signal, if the signal drives many inputs?
2. I have a set of signals that drive many non-clock inputs. The software
gives worning, saying that I need to use clock network to route those
signals, since they drive one or more clock inputs (while they don't). Is
this problem somehow associated with question 1?
3. What is the drawback of using clock network to drive non-clock inputs?
The software gives warning about that.
4. How can I tell the software not to use global clock network for a certain
signal? It drives the clock input of only one cell.
5. The software gives warnings about latches. I use latches for input
registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
REG<=HOST_DATA")? I see no advantage of clocked register here, since my
target FPGA's cell has both async input pin and clock pin.
regards,
vax, 9000
Article: 81029Hi everyone, I just want to have the filename of the Webpack 7.1 installer for linux? ThanksArticle: 81030
vax, 9000 wrote:
> 5. The software gives warnings about latches. I use latches for input
> registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
> them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
> REG<=HOST_DATA")?
Yes, but consider using the same clock for all of your registers.
Use the D and CE inputs for logic.
> I see no advantage of clocked register here, since my
> target FPGA's cell has both async input pin and clock pin.
I expect that you will someday.
-- Mike Treseler
Article: 81031Hello, I've been hearing a lot about DSP Builder and was curious if it is worth learning? Can anyone share their experience pros/cons? Are they any good references I could pick and teach myself? Thanks, joeArticle: 81032
Duane Clark wrote:
> Yes it should. Take a close look at the code.
Sorry. You are correct.
It should be a synchronous load.
-- Mike Treseler
Article: 81033> > This is interesting. During the power supply design, a lot of pain > went into the sequencing. > In attempting to reproduce the problem, are you testing in an actual system with all boards and I/O connected in the usual configuration, or in the lab with just the problematic board on a bench supply? > > A few of the parts have problems when the power is > not brought up correcly. > Does that result in any symptoms like your FPGA config problem, or is everything so locked up that you can't tell ? Without the power-up sequencing, do you get destructive failures? If not a destructive failure mode, can you briefly disconnect (not clamp) the +5.0 V supply to the board, with -5.2V present, and see what level the +5.0V plane on the board goes to? Or, intentionally disable/break the supply sequencer and power cycle. > > The problem so far seems to have happened not during power cycles > of the instruments, but while the instruments are in their normal > run mode. > Do you have an AC disturbance/brownout generator to see how the supply sequencer for the +5.0 and -5.2 rails behaves during a brief AC dropout ? Is one supply rail much more heavily loaded than the other, so it would dip faster on an AC brownout? > > Yes, it's real negative ECL. 100H603s are used for the translation. > Hmmm, that also rings some faint old warning bells- I seem to recall having problems once after I redesigned a card to replace some obsolete translators with either the '602 or '603. Symptoms were field returns with either a failed bit or two on the '60x, or occasionally a part that looked it like had undergone some sort of latchup/runaway and self destructed. BrianArticle: 81034
I have used it during some month for a trainee and it is really easy too use, if you already use simulink , it is the same thing. You could use all matlab functions to generate your stimuli and analyze result. But I think it's mainly powerfull for signal processing application not for making state machine or thing like that. For reference look at simulink ref , if you know well matlab/simulink well you are ready to use dsp builder. The way we used it during my internship was to make some part of the design with DSP Builder then generate the netlist (i'm not sure that really a netlist it's a *.vqm file) and integrated to the the final project in quartus I ask my self if there is not already an other tool non-dependant of a FPGA firm that t just convert a simulink file to vhdl or verilog, it probably need some specific library but it should be too hard to implement such tool. alexis <jjlindula@hotmail.com> a écrit dans le message de news: 1111002471.929510.152890@z14g2000cwz.googlegroups.com... > Hello, I've been hearing a lot about DSP Builder and was curious if it > is worth learning? Can anyone share their experience pros/cons? Are > they any good references I could pick and teach myself? > > Thanks, > joe >Article: 81035
show more of your code because with this we couldn't help you so much, and what are you error message?? "Preben Holm" <64bitNOnoNOSPAM@mailme.dk> a écrit dans le message de news: 423883a2$0$29277$14726298@news.sunsite.dk... > Hi everyone, > > why doesn't this synthesize: > > > architecture Behavioral of datacontroller is > type states is std_logic_vector(4 downto 0); > constant stateStart : states := "00001"; > constant stateWait : states := "00010"; > constant stateTrigger : states := "00100"; > constant stateHold : states := "01000"; > constant stateRead : states := "10000"; > > signal holdoff : std_logic; > signal holdoff_counter_enable, holdoff_counter_reset : std_logic; > > component counter19bit > Port ( clk, ce, reset : in std_logic; > preset : in std_logic_vector(19 downto 0); > c : out std_logic; > q : out std_logic_vector(18 downto 0)); > end component; > begin > [SNIP] > > > It's directly taken from the book "VHDL made easy". > I'm using Xilinx Webpack 6.3i! > > > Thanks > Preben HolmArticle: 81036
"vax, 9000" <vax9000@gmail.com> a écrit dans le message de news:
d1a050$902$1@charm.magnus.acs.ohio-state.edu...
> Hi, list,
> I got a few questions when I was using the XILINX webpack software for a
> homebrew small project. I appreciate your answers.
>
> 1. Will the software try to use a global clock network to route a
> non-clock
> signal, if the signal drives many inputs?
NO, If you want to use global clock network you should infer a global clock
buffer (bufg) component ,
> 2. I have a set of signals that drive many non-clock inputs. The software
> gives worning, saying that I need to use clock network to route those
> signals, since they drive one or more clock inputs (while they don't). Is
> this problem somehow associated with question 1?
> 3. What is the drawback of using clock network to drive non-clock inputs?
> The software gives warning about that.
> 4. How can I tell the software not to use global clock network for a
> certain
> signal? It drives the clock input of only one cell.
> 5. The software gives warnings about latches. I use latches for input
> registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
> them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
> REG<=HOST_DATA")? I see no advantage of clocked register here, since my
> target FPGA's cell has both async input pin and clock pin.
>
> regards,
> vax, 9000
Article: 81037
I'll add my view for all your questions:
"vax, 9000" <vax9000@gmail.com> wrote in message
news:d1a050$902$1@charm.magnus.acs.ohio-state.edu...
> Hi, list,
> I got a few questions when I was using the XILINX webpack software for a
> homebrew small project. I appreciate your answers.
>
> 1. Will the software try to use a global clock network to route a
non-clock
> signal, if the signal drives many inputs?
Of the recent Xilinx FPGAs, I'm only aware of the Virtex-4 as having the
global clock signals available as logic inputs. The other families only
allow the physical global clock lines to feed clocks (perhaps also clock
enables and resets, I forget what I last saw in the FPGA Editor tool). The
software expects that your signal is either a clock or it isn't and tries to
gear up for the one or the other.
> 2. I have a set of signals that drive many non-clock inputs. The software
> gives warning, saying that I need to use clock network to route those
> signals, since they drive one or more clock inputs (while they don't). Is
> this problem somehow associated with question 1?
Because the tool sees "a" clock that it's trying to treat as a clock, it
wants to throuw in the BUFG to get onto the clobal clock lines. But you
want logic.
> 3. What is the drawback of using clock network to drive non-clock inputs?
> The software gives warning about that.
The signal gets routed through the BUFG to go to the one item that's
clocked. I've seen a mixed-use signal jump off at the input to the BUFG and
go to the rest of the logic from there rather than routing normally. That's
not necessarily how things are done now.
> 4. How can I tell the software not to use global clock network for a
certain
> signal? It drives the clock input of only one cell.
Try the synthesis directive BUFFER_TYPE (set to "none") to force your clock
to be understood as a non-global.
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0055_16.html#wp240059
or http://tinyurl.com/69mly
> 5. The software gives warnings about latches. I use latches for input
> registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
> them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
> REG<=HOST_DATA")? I see no advantage of clocked register here, since my
> target FPGA's cell has both async input pin and clock pin.
Most synthesizers have a form they like to produce latches without warnings.
Check your language reference to see about implementation templates. (I'd
point you the right way if I'd used XST in the past).
> regards,
> vax, 9000
glad to (try to) help,
- John_H
Article: 81038
I'll add my view for all your questions:
"vax, 9000" <vax9000@gmail.com> wrote in message
news:d1a050$902$1@charm.magnus.acs.ohio-state.edu...
> Hi, list,
> I got a few questions when I was using the XILINX webpack software for a
> homebrew small project. I appreciate your answers.
>
> 1. Will the software try to use a global clock network to route a
non-clock
> signal, if the signal drives many inputs?
Of the recent Xilinx FPGAs, I'm only aware of the Virtex-4 as having the
global clock signals available as logic inputs. The other families only
allow the physical global clock lines to feed clocks (perhaps also clock
enables and resets, I forget what I last saw in the FPGA Editor tool). The
software expects that your signal is either a clock or it isn't and tries to
gear up for the one or the other.
> 2. I have a set of signals that drive many non-clock inputs. The software
> gives warning, saying that I need to use clock network to route those
> signals, since they drive one or more clock inputs (while they don't). Is
> this problem somehow associated with question 1?
Because the tool sees "a" clock that it's trying to treat as a clock, it
wants to throuw in the BUFG to get onto the clobal clock lines. But you
want logic.
> 3. What is the drawback of using clock network to drive non-clock inputs?
> The software gives warning about that.
The signal gets routed through the BUFG to go to the one item that's
clocked. I've seen a mixed-use signal jump off at the input to the BUFG and
go to the rest of the logic from there rather than routing normally. That's
not necessarily how things are done now.
> 4. How can I tell the software not to use global clock network for a
certain
> signal? It drives the clock input of only one cell.
Try the synthesis directive BUFFER_TYPE (set to "none") to force your clock
to be understood as a non-global.
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0055_16.html#wp240059
or http://tinyurl.com/69mly
> 5. The software gives warnings about latches. I use latches for input
> registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
> them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
> REG<=HOST_DATA")? I see no advantage of clocked register here, since my
> target FPGA's cell has both async input pin and clock pin.
Most synthesizers have a form they like to produce latches without warnings.
Check your language reference to see about implementation templates. (I'd
point you the right way if I'd used XST in the past).
> regards,
> vax, 9000
glad to (try to) help,
- John_H
Article: 81039Preben Holm wrote: > Hi everyone, > > I just want to have the filename of the Webpack 7.1 installer for linux? > > > Thanks .sh ;)Article: 81040
Michael Pieber wrote: > Hi together. > > I'm relatively new with FPGAs and I have no experience with rams. Now > I'm working on a ram controller for a MEMEC FPGA board with a xilinx > spartan IIE (@100 MHz). It should be a very simple module, and speed is > not very important, because the data to be written come at a low > frequency. What kind of ram are you talking about here? DDR SDRAM, for instance, has quite tight timing constraints, and requires a carefully considered clocking strategy. SRAM on the other hand may well be a lot simpler, depending on the type. JeremyArticle: 81041
Peter Alfke wrote: > Less! That's the whole idea... > But watch whether your package and density is available. If it is, it > will be chaeper. What about similar packages - for instance, a S3-1500 vs a S3E-1600? JeremyArticle: 81042
A Beaujean wrote: > Pardon me if I am presently missing a very simple way to tell the tool > "Please do not use one of your GCLK resources", but I am not a very > frequent user of VHDL and had no chance to go to any advanced seminar > of any kind. > > A solution to that problem ? > > Please answer if you are aware of some. If you are using synplify, you can use the syn_noclockbuf constraint. JeremyArticle: 81043
Jeremy, The Spartan 3E represents a relayout, with improved design rules, and other optimizations to reduce area, improve yield, and overall reduce the cost. One family is optimized for logic per $, and the other is optimized for IO per $. If both families have the logic, and the IO needed to do you application, then I would say that the new 3E family will have the $ edge since it is the third generation 90nm product in the line. AustinArticle: 81044
Stephen Dcombe wrote:
> I was wondering about possible uses of the FPSLIC devices. I feel
> there must be an application where they would be more suited than
> other SoC solutions but I really can't come up with anything.
>
> If any one has any suggestions they would be greatly received.
Here are some applications:
*************************************************
Octal Fixed 9600 BAUD UART for external MCU.
Common BAUD RATE generator
FPGA implements a 2 bit shift register for each tranmitter
FPGA implements a majority voting filter and a startbit detector on each
receivers
FPGA synchronizes the receiver data with the transmitter data.
Octal Software UART using a single interrupt
handling all 8 transmitters and all 8 receivers
handling H/W or S/W flow control
Maintaining error counters
4 kB SRAM for FIFO buffers (256 level FIFO in both directions)
Thís should fit into the AT40K05.
****************************************************
Low speed HDLC controller (16 kbps) on T1/E1 line.
FPGA implements a synch serial controller with timeslot assignment.
AVR handles the bit stuffing, calulcates CRC etc.
******************************************************
Advanced Timers
Multiple capture channels.
You have up to 16 kB x 8 SRAM for capture data.
You can run the AX series in 40 Mhz.
This means that you can store 8 x 40 = 320 bits of capture info per
microseconds.
If you capture 96 bits with a 64 bit timestamp you need 160 bits or 20 bytes
giving you 500 ns resolution.
you can store a maximum of 16384 / 20 = 819 events.
The SRAM can store sinus waveforms, for easy waveform generation.
*****************************************************
If you need a fieldbus, here is the part.
Many companies have their proprietary serial bus, which is
often a piece of cake to implement on the FPSLIC.
****************************************************
Graphics LCD controller.
64 * 128 = 1024 bytes.
Fits easily into the FPSLIC and you get high speed access to the LCD buffer.
****************************************************
CMOS camera framegrabber.
Implement the CCITT interface in the FPGA
Add a 32 x 15 FIFO in FreeRAM, and store in a shared memory
outside the FPSLIC.
----------------------
Generally things which needs slow processing and fast synchronisation
are excellent applications for the FPSLIC:
Feel free to contact me directly.
--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Article: 81045Stephen Dcombe wrote: > I was wondering about possible uses of the FPSLIC devices. I feel > there must be an application where they would be more suited than > other SoC solutions but I really can't come up with anything. > > If any one has any suggestions they would be greatly received. Implementing filters is another possibility. You have lots of SRAM in an otherwise small FPGA: I think it should be possible with a 100 ns 16 x 16 -> 32 multiply + 32 bit accumulate in 4 clocks on a 5/10 kgate FPSLIC, with both sample and coefficient in the n x 8 SRAM. The AVR can acquire the samples from an external ADC and then start FIR/IIR filtering. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 81046
Preben Holm <64bitNOnoNOSPAM@mailme.dk> writes: > I just want to have the filename of the Webpack 7.1 installer for linux? The filename is "setup". I posted info on my experiences installing on Fedora Core 3 on this newsgroup a few days ago. EricArticle: 81047
Thank you JJ. Are you able to provide me some info on the USB connected LA boxes? Most of my data are below 100KByte in text file, but I have over one thousand of them. What I need is not only to send out the data manually, but also do automation, e.g. send in a 100KB test data in a batch, which goes through my device under test. My DUT then output 100 bytes of demodulated data which is supposed to be captured by the PC and compare with my simulated output. However I am sure I can handle this portion without difficulty. Is there any LAs that can be easily manipulated by my C programs? "JJ" <johnjakson@yahoo.com> wrote in message news:1110981184.435989.320780@l41g2000cwc.googlegroups.com... > Seems you might also consider just putting an SDRam (even 1GByte is <<$ > than PCI 64) next to signal capture and download at leasure later on > using any modest IO scheme.. > > How long are these samples to last for?, if less than 1B, just buffer > it. > > If you absolutely need continuous capture then you have a more > interesting challenge! > > BTW there are data capture boxes you can get off the shelf ie USB > connected logic analyzer for a few $100. If their buffers are big > enough maybe those can be used at least in a lab setup. > > regards > > johnjakson at usa dot com >Article: 81048
I made use of two 1K*10B single port RAMs generated with coregen which is modified to contain my test vector, and P&R with that. However, I have one thousand test vector files in plain text to send to the FPGA one at a time. I am wondering about whether I can write a perl script to manipulate the bitstream and generate an *incremental* bitstream so that I can avoid running ISE for one thousand times? Where can I find such information? Thanks.Article: 81049
"Douglas Sykora" <djsykoraNOSPAMM@execpc.com> wrote in message news:113djevp68pa56d@corp.supernews.com... > Thomas, > Thanks for the tip. I will try the enumerated seed specification as soon > as I get into work. I have been using the range specification such as > 2-10. > Thanks > Doug > "Thomas Entner" <aon.912710880@aon.at> wrote in message > news:42369e19$0$15878$91cee783@newsreader02.highway.telekom.at... > > Hi Doug, > > > > there are versions of DSE that supports seeds like 1-10 20-30, other > > versions need that you write 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 > 28 > > 29 30. Maybe you are writing "1-10" in a version that does not support > this? > > Beside that DSE worked always fine for me (not tested distributed usage > > yet). > > > > Thomas > > > > www.entner-electronics.com Thomas, I tried the typing in the seeds as you suggested, but it did not help. The version I am using (4.2 SP1) allows entering seeds in either format. Thanks, Doug > > > > "Douglas Sykora" <djsykoraNOSPAMM@execpc.com> schrieb im Newsbeitrag > > news:113cqgdrss51rbf@corp.supernews.com... > > > Altera includes the Design Space Explorer (DSE) along with Quartus II. > I > > > have found this tcl script to be very helpful when I can get it to work > > > for > > > me. But lately, it has been very frustrating because it fails to > explore > > > the space I set it up to explore. > > > > > > Has anyone else seen this behavior? > > > - I set up the exploration space in the DSE GUI, for example, to do a > > > seed > > > sweep. > > > - DSE starts by running a compilation flow on the base. > > > - DSE finishes this and archives the results. > > > - DSE stops and displays a message that there are no errors or > warnings. > > > It doesn't go on to the next point in the exploration space. > > > > > > I have also tried this with the distributed computing option. DSE will > > > create archives, one for each exploration point. It then submits one to > a > > > remote computer and fails to actually compile it, and the process ends. > > > > > > If you have seen this behavior, do you know what could be causing it and > > > how > > > to correct it. > > > > > > I have not found any references to this problem in the archives and > > > haven't > > > received much help yet from the Altera support group, but I am hoping > this > > > is forthcoming. > > > > > > I am running with the Windows XP operating system (also tried Windows > > > 2000) > > > and using the latest version of Quartus II (4.2 SP1). > > > > > > I have used DSE successfully, so it doesn't always display this > behavior. > > > > > > Thanks in Advance, > > > Doug > > > > > > > > > > > >
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