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<wtxwtx@gmail.com> wrote in message news:1138639411.086462.285470@o13g2000cwo.googlegroups.com... > Hi Mike, > I disagree with your opinion. > > BLOCK RAM data output is driven by its address, no matter it is old or > brand new. How does it work for a 4K bytes block? Each RAM bit > internally drives a 1-bit tristate data bus selected by its address > decode logic. From outside, it is only one data output bus. > > For any CPUs, its SRAM in cache are also driven by its addresses. So > tristate buses are as ubiquitous as a register. No any exception is for > general FPGA design. > > Only passive tristate bus is rarely used and shouldn't be used for an > active data bus. > > Weng So my earlier comment that you disagreed with should be modified to state: "But it's never good design practice to have [Verilog] tristates with multiple [simultaneous] sources" I don't think anyone doubts that tristate functionality in silicon IP blocks is a bad idea because the issues of multiple simultaneous drivers is excluded.Article: 96101
Hi John, I would like to say: Multiple sources can safely drive a tristate bus without any bad effects if their enable signals are mutually exclusive either by their logic or by physical conditions. There are many situations where mutually exclusive conditions exist by their physical conditions, not by their logic. For example, you must drive a data bus on two different physical conditions, then their enable signals are mutually exclusive. For example, if one chip has to drive a bus, the bus runs with either 64-bit or 32-bit conditions. The source enable signals driving 64-bit and 32-bit are mutually exclusive, no matter how your design logic is. Weng John_H wrote: > <wtxwtx@gmail.com> wrote in message > news:1138639411.086462.285470@o13g2000cwo.googlegroups.com... > > Hi Mike, > > I disagree with your opinion. > > > > BLOCK RAM data output is driven by its address, no matter it is old or > > brand new. How does it work for a 4K bytes block? Each RAM bit > > internally drives a 1-bit tristate data bus selected by its address > > decode logic. From outside, it is only one data output bus. > > > > For any CPUs, its SRAM in cache are also driven by its addresses. So > > tristate buses are as ubiquitous as a register. No any exception is for > > general FPGA design. > > > > Only passive tristate bus is rarely used and shouldn't be used for an > > active data bus. > > > > Weng > > > > So my earlier comment that you disagreed with should be modified to state: > > "But it's never good design practice to have [Verilog] tristates with > multiple [simultaneous] sources" > > I don't think anyone doubts that tristate functionality in silicon IP blocks > is a bad idea because the issues of multiple simultaneous drivers is > excluded.Article: 96102
Hey All, I have a technical screen interview with TI based in dallas. I am a front-end digital design engineer with two years of experience is designing DSPs in FPGAs. This is the first time I would be going through a technical screening-don't know what it means actually...is it a fancier term for a technical interview? Anyways, if anyone has gone through this, please share your experience-it would be good info cheers MORPHEUSArticle: 96103
All: From our legal group- "Xilinx invests a significant amount in research and development, and vigorously protects and enforces its intellectual property rights resulting from its research and development efforts. It is also correct that when Xilinx licenses its software and tools, Xilinx prohibits its customers from reverse engineering and decompiling its software products. Also, the bitstream created by using Xilinx software is owned by Xilinx can only be used on Xilinx programmable products, for example, FPGAs. Xilinx licensing terms and conditions are similar to other companies that provide similar products and services. Therefore, Xilinx sees no basis for amending or modifying the terms and conditions of its software licenses and the rights to use the bitstream created with the use of Xilinx software." For Xilinx sponsored University projects, there may be separate agreements (I know because I am sponsoring a project, and I had to review the new agreement). So, for anyone using our software, read the agreement, and be sure you are in compliance. If you desire to do anything outside of the agreement, please contact our legal department, or the Xilinx University Program. AustinArticle: 96104
Austin Lesea wrote: > So, for anyone using our software, read the agreement, and be sure you > are in compliance. If you desire to do anything outside of the > agreement, please contact our legal department, or the Xilinx University > Program. Austin, Thanks for being direct and bringing this info directly to this forum. The broad assumption is that XDL and the interfaces/libraries that it exposes are a public interface. Combined with the fact that is it openly disclosed outside NDA on a very large number of projects, what is the specific Xilinx statement about XDL and related info being a public use interface to ISE outside of NDA restrictions? JohnArticle: 96105
On a sunny day (Mon, 30 Jan 2006 09:50:46 -0800) it happened Austin Lesea <austin@xilinx.com> wrote in <drljlm$3ls1@xco-news.xilinx.com>: >All: > > From our legal group- > Also, the bitstream created by using Xilinx software is owned >by Xilinx can only be used on Xilinx programmable products, for example, >FPGAs. This looks like arather dangerous typo, I presume you wanted to write: "the bitstream format as generated by Xilinx software " You do not claim rights to the content of my bitstream I hope? ?Article: 96106
morpheus wrote: > Hey All, > I have a technical screen interview with TI based in dallas. I am a > front-end digital design engineer with two years of experience is > designing DSPs in FPGAs. This is the first time I would be going > through a technical screening-don't know what it means actually...is it > a fancier term for a technical interview? Anyways, if anyone has gone > through this, please share your experience-it would be good info > cheers > MORPHEUS > It means whatever TI thinks it means. It could be an engineer asking you technical questions, or it could be a recruiter asking you the same. It's hard to say. On the opposite side from you, I have conducted preliminary phone interviews, I've compiled questions for phone screeners to ask and I've evaluated answers from those same screens. I know that when I do it I usually try to ask questions that are hard enough to trip up the interviewee at least once, and I don't look for a 100% score to recommend a hire. What I do look for is 'yes' answers to the following questions: * Will this guy come up to speed quickly? * Will this guy keep up in the long run? * Can this guy talk about what he does so his work will be traceable? * Can this guy work within a group? * Can this guy understand where we come from? Note that the first two questions start with 'will' -- I think it's unrealistic to hire with the expectation that someone will already know everything about the task. I _do_ think it's realistic that someone will be be _able_ to learn all the local peculiarities quickly, and be useful in a matter of a few weeks. I also think it's realistic to expect that anyone who's not a fresh college hire (and most that are) have already worked in a group with good work documentation. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 96107
John, "XDL and related info being a public use interface to ISE outside of NDA restrictions" is clearly prohibited. But, if XDL is used inside of the agreement, then that is OK. For example, if you created a XDL file with our tools, and then processed it with your tool, and then wanted to use in in silicon other than Xilinx, that is prohibited. If you created your own XDL file, without use of our tools, sent it through your own tools, to do something with it (for reasons unknown) then I suppose (but we can research further) we don't care what you do with it. But if you then used our tools again (to do anything) to the XDL (you created), then again, its use is restricted to Xilinx silicon. So, if our software is part of the chain, then the agreement applies. AustinArticle: 96108
Jan Panteltje wrote: > On a sunny day (Mon, 30 Jan 2006 09:50:46 -0800) it happened Austin Lesea > <austin@xilinx.com> wrote in <drljlm$3ls1@xco-news.xilinx.com>: > > >>All: >> >>From our legal group- > > >>Also, the bitstream created by using Xilinx software is owned >>by Xilinx can only be used on Xilinx programmable products, for example, >>FPGAs. Hmm, yes, not everyone will agree to that claim... > > This looks like a rather dangerous typo, I presume you wanted to write: > > "the bitstream format as generated by Xilinx software " > You do not claim rights to the content of my bitstream I hope? Of course they do! These are lawyers, they claim all rights possible, until someone pushes back. That's how they work. I _can_ sense an opening here, for the (A) company that claims to be "the fastest growing major programmable logic company in 2005" -jgArticle: 96109
Phil Tomson wrote: > I've set up a wiki space for discussion of ideas for an open source XDL tool > suite. For those not familiar with wikis, they are collaborative web spaces > that can be edited by anyone (for now it is editable by anyone; if there are > problems we can restrict edit access to approved authors) or by a > select set of individuals. They're used quite commonly for software projects > now as they are great for discussion of features, todo lists, idea boards, etc. Well Austin just clearified XDL's use: "XDL and related info being a public use interface to ISE outside of NDA restrictions" is clearly prohibited. Which basically includes any public discussion of XDL and open source access to XDL.Article: 96110
On Mon, 30 Jan 2006 14:01:37 +0000 (UTC), christopher.saunter@durham.ac.uk (c d saunter) wrote: >Robin Bruce (robin.bruce@gmail.com) wrote: > >: Hans wrote: >: > If you have to choose a C language I would recommend you check out SystemC >: > which might be better on your CV than Handel-C :-) > >: What's so good about SystemC? :) > >What's so good about AnythingC? > >I have quite strong feelings that whilst a high level language than >Verilog/VHDL could be a real boon to FPGA development, C is far from a >good prototype form for such a language.... uh, in what way is C a higher level language than VHDL anyway? - BrianArticle: 96111
Austin Lesea wrote: > "XDL and related info being a public use interface to ISE outside of NDA > restrictions" is clearly prohibited. Thanks Austin for making this clear. You mentioned that Xilinx provides exemptions to university projects. There is significant documentation to be gleaned from various published works which are easily located with google. Most of these appear to be university sources. Can we assume that source code, VDL files, papers, and instructional materials which describe VDL and related interfaces are approved disclosures by Xilinx that open source can freely use to develop open source tools in support of Xilinx customers? JohnArticle: 96112
John, No, you can not assume anything. In fact, I think you (personally) should talk to our legal department, and reach an agreement. AustinArticle: 96113
Jan, Xilinx restricts the use of the bitstream to only be used with its products. In that sense, we retain "ownership." I am not a lawyer, so I can't speak or quote legalize. What I placed in quotes was from a lawyer. They do not make typos. I might. AustinArticle: 96114
Phil, If you desire an opinion, please contact our legal group. John's email to you is incomplete. Go read my posting, and make your own decision. Or better yet, contact our legal department, AustinArticle: 96115
Correction: See I can make typos... Austin > In that sense, we retain "ownership." I am not a lawyer, so I can't > speak or quote legalize. What I placed in quotes IN MY PREVIOUS POSTING > was from a lawyer.Article: 96116
Jim Granville wrote: > Jan Panteltje wrote: >> On a sunny day (Mon, 30 Jan 2006 09:50:46 -0800) it happened Austin Lesea >> <austin@xilinx.com> wrote in <drljlm$3ls1@xco-news.xilinx.com>: >> >> >>> All: >>> >>> From our legal group- >> >> >>> Also, the bitstream created by using Xilinx software is owned >>> by Xilinx can only be used on Xilinx programmable products, for example, >>> FPGAs. > > Hmm, yes, not everyone will agree to that claim... > >> >> This looks like a rather dangerous typo, I presume you wanted to write: >> >> "the bitstream format as generated by Xilinx software " >> You do not claim rights to the content of my bitstream I hope? > > Of course they do! > These are lawyers, they claim all rights possible, until someone > pushes back. That's how they work. > > I _can_ sense an opening here, for the (A) company that claims > to be "the fastest growing major programmable logic company in 2005" > > -jg > > The (A) company used these exact same EULA restrictions against Clear Logic and won. More details here: http://www.internetcases.com/archives/2005/09/ninth_circuit_a_1.html EdArticle: 96117
Austin Lesea wrote: > Phil, > > If you desire an opinion, please contact our legal group. > > John's email to you is incomplete. Go read my posting, and make your > own decision. Or better yet, contact our legal department, > > Austin What did I miss Austin? .... the EULA NDA terms and your statement clearly mean personal use only, disclosure in public discussions can not assume the other members are under the same NDA terms, and you have been clear that no open source access exists. That leaves limited EDIF and XNF access to open source tools which produce net lists for Xilinx ISE.Article: 96118
Lori Lorenser wrote: > Hi. > > I'm working with the Virtex 4 on a ML403 and want to use the audio codec AC97. At first i want to connect a mp3-player to line in and then i want to manipulate the audiostream and send it to line out. But i don't find a detailled description (e.g not in ml403 userguide) of the audio codec. So i don't know which pin i should use. > > Does anybody know a paper/tutorial/user guide or something else, how to use the audio codec on ml403(virtex 4)? The Xilinx ML40x reference designs all contain an OPB peripheral that can talk to the AC97. The full source is provided, so that would be a good place to start. www.xilinx.com/ml403 Regards, JohnArticle: 96119
Austin Lesea wrote: > John, > > No, you can not assume anything. In fact, I think you (personally) > should talk to our legal department, and reach an agreement. It seems to me that part of the problem is that Xilinx is used to negotiating special provisions with customers one by one, and may even be quite responsive and liberal in doing so with fairly small customers. That's fine for closed projects, but open source efforts under "free software" licensing may only make use of information or components which may be freely shared with all potential users, with the only restrictions on disclosure, permissable uses or modifications being that you cannot impose new restrictions on disclosure, permissable use or modification. As a result, the only usefull answers to the kinds of questions that have been asked are published, public ones. Though some of the questioning and floating of trial answers could take place behind the scenes.Article: 96120
Antti Lukats wrote: > I just love how easy it is to port uClinux to new platform, just > change the UCF file and there you go :) You know Antti, in a very strange way you can take some credit for that fact. Your statement in a comp.arch.fpga posting 18 months ago http://groups.google.com.au/group/comp.arch.fpga/browse_frm/thread/97f020e714a25237/2a12c984240d22e8?tvc=1&q=lukats+uclinux#2a12c984240d22e8 "NIOS uCLinux is WAY easier to get started then MicroBlaze uCLinux thanks to the full integration of the config and integration into Eclipse workbench, as EDK6.3 is also Eclipse based it would be possible todo the same for MicroBlaze uClinux config and build. " p***ed me off so much I went and created the auto-config mechanisms that now make mb-uclinux by far the easiest (and probably most popular) soft-CPU Linux solution around. So, thanks - I think :) JohnArticle: 96121
In article <drlvcp$3ls5@xco-news.xilinx.com>, Austin Lesea <austin@xilinx.com> wrote: >Phil, > >If you desire an opinion, please contact our legal group. > >John's email to you is incomplete. Go read my posting, and make your >own decision. Or better yet, contact our legal department, > Yeah, that's the plan at this point. As is with most everything related to law, the more that is said, the muddier things get ;-) PhilArticle: 96122
cs_posting@hotmail.com wrote: > That's fine for closed projects, but open source efforts under "free > software" licensing may only make use of information or components > which may be freely shared with all potential users, with the only > restrictions on disclosure, permissable uses or modifications being > that you cannot impose new restrictions on disclosure, permissable use > or modification. > > As a result, the only usefull answers to the kinds of questions that > have been asked are published, public ones. I can not personally broker a deal for an open source project, because I can not control the use and modification of the project in the open public. I would not accept the personal liability should Xilinx think I could even control what happens to the information after we publish it. So public discussion, that all can use is the only productive forum for open source uses.Article: 96123
fpga_toys@yahoo.com wrote: > So the question to Xilinx is, will Xilinx release the NDA restrictions > on XDL, and the associated library interfaces so that open source tools > can legally target ISE supported FPGAs? > [...] > So how about a clear definative legal statement about what are legal > ISE interfaces for open source development. See the thread "Xilinx Legal" started by Austin ... no more speculation, the answer remains no open source access. It also means a number of projects which have been posted online are in violation of the Xilinx EULA NDA.Article: 96124
fpga_toys@yahoo.com wrote: > I can not personally broker a deal for an open source project, because > I can not control the use and modification of the project in the open > public. I would not accept the personal liability should Xilinx think I > could even control what happens to the information after we publish > it. > > So public discussion, that all can use is the only productive forum > for open source uses. I think you could get the ball rolling with some email, but I agree that all of the 'decisions' woul d have to be very public, and even enough late-stage discussion to illuminate them, for the result to be of any use for a free and open project. It seems like you are hoping Xilinx legal will meet you here. That might be a good result, but you may have to first talk to them on their turf to issue the invitation.
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