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Is there a cheesy way to quadruple an input clock frequency to a FPGA (XC4000 series) internally ? I'd like to take an 8MHz input to 32MHz Thanx RobArticle: 24251
After the long suppositions and wondering "will they, wont they, can they, cant they?", we finally see an IPO filing from Synplicity. You can read the filing with all the juicy financial detail through www.ipo.com. Once you've read it (and deciphered it?), as informed observers of the synthesis market space (Exemplar/Synopsys/Synplicity etc.) tell me: On balance, would you invest? Cheers Stuart An employee of Saros Technology: Model Technology, Exemplar Logic, TransEDA, Renoir. www.saros.co.ukArticle: 24252
Hi all We are trying to get an XC2S50-5PQ208 but can't find any. Avnet seems to sell them quicker than they can buy them from Xilinx... We plan to buy quantities but need some parts for prototyping extremely quickly (and there's no Virtex with a PQ208 package). I contacted a friend of mine at Xilinx France, too... Still waiting. Can any of you sell us 1 or 2 chips (any size, as long as it's an XC2S with a PQ208 package)? We can give our FedEx account # for shipping (+ small gift) Thanks in advance -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24253
Hi Eric: Next is very easy to try in the graphic editor ( I tested it in flex8K, but I think the result is the same for 10K): Try the previous function and assign the AND4 in the LCELL LC2A2 -for example-; register the four inputs and assign the four registers in the LAB A1. Make a timing analysis and look the results in the delay matrix: one of the delays from the *.Q registered outputs is faster... How to know wich will be the "selected" input of the AND4 is my question... Thanks. Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de noticias U7jh5.28547$227.539978@nnrp1.uunet.ca... > Hi Bernardino.... > > Can you give a reference pointer for the statement: > > >One of the four inputs of the LUTs in the FLEX family is faster than the > >three others. > > I have not come across this little gem before........ > > Eric Pearson > > > > Bernardino León wrote in message ... > >Suppose we have a function like Y = A AND B AND C AND D, that fits in a > >LUT... And suppossing that there isn't any timing constrain in any of the > >inputs > >Is there any way to know - BEFORE compiling - which one of the four inputs > >will be assigned the fastest of the four inputs? > > > >Thanks > >Bernardino Leon > >bleon@lander.es > > > > > > > >Article: 24254
Good point. In one application I have used this for, the incoming clock was a CTT signal from a special 12ch parallel fiber device and the Xilinx supports that standard, while none of the other devices on the board do. In that situation I drive the first DLL's output clock out and back in so that the signal I drive out in LVTTL format is synchronous to the incoming CTT clock, and in a useful format. Then I use another DLL to create and in-phase clock for the FPGA. It takes lots of clock resources, but it works. This is less of a problem in VirtexE since there are twice as many DLLs and clock inputs. Ben rickman wrote: > > I think you are missing something. The clock started as an external > signal and the DLL should compensate for the IOB delay on the input. So > the *incoming* external clock and the internal clock should be inphase. > So why would you need to route it back out again at all? > > Ben Sanchez wrote: > > > > Yes. I think that if you read that app note (it's not right in > > front of me, but memory says this is there) it explains that you > > can only drive a single device with the output of a Virtex DLL. > > You can drive either a BUFG for an internal clock, or an IOB for > > an external clock. Of course, you could always drive an IOB out > > from the output side of the BUFG, but then you don't get > > synchronous edges inside and outside the chip. The external one > > would be lagging the internal clock by one IOB delay time (+/- > > the slight skew of the global clock routing tree, which is > > small). > > > > Ben > > > > seamus wrote: > > > > > > In figure 10 of Xilinx app note 132 (xapp132), is shown a method > > > to de-skew a board level clock (clock is input to two DLL's, the > > > output of the first DLL is driven outside the chip back to other > > > external devices as well as back internal to the first DLL > > > feedback pin; the second DLL is used to generate the clock to be > > > used internal to the chip). > > > > > > My question is, what does this method of using two DLL's gain you > > > over using just one DLL in the standard implementation and > > > driving the externally generated clock to the Xilinx part as well > > > as the other external chips? I don't see any benefit. (I do see > > > a benefit if you had to multiply or divide the original clock > > > source - but that is not my case). Am I missing anything? > > > > > > ----------------------------------------------------------- > > > > > > Got questions? Get answers over the phone at Keen.com. > > > Up to 100 minutes free! > > > http://www.keen.com > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- =========================================================== Ben Sanchez Engineer, Lab Manager e-mail: ben@phoenix.seti.org Project Phoenix voice: 650/960-4565 SETI Institute fax: 650/968-5830 2035 Landings Drive Web: http://www.seti.org Mountain View, CA 94043 ===========================================================Article: 24255
In article <01bffb20$69dd0180$3e06f7a5@drt1>, austin@darkroom88.com (Austin Franklin) wrote: > I have a design that currently uses a PLX 9080, and I need to move it > to a > 64 bit and/or 66MHz PCI interface... PLX does not currently offer a > solution, that I can find...neither does AMCC. Any suggestions for off > the > shelf chips to do this, or any experience with the QuickLogic QL5064 > interface chip? I've been thinking about QuickLogic, but past experience with Actel has put me off OTP technologies. -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 24256
Hi Bernardino.... The times you are mentioning include the routing delays, and of coarse each path must take a different route..... Can you find (and share) some documentation to substantiate your hypothesis? Eric Bernardino León wrote in message ... >Hi Eric: > >Next is very easy to try in the graphic editor ( I tested it in flex8K, but >I think the result is the same for 10K): Try the previous function and >assign the AND4 in the LCELL LC2A2 -for example-; register the four inputs >and assign the four registers in the LAB A1. Make a timing analysis and look >the results in the delay matrix: one of the delays from the *.Q registered >outputs is faster... How to know wich will be the "selected" input of the >AND4 is my question... > >Thanks. > >Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de >noticias U7jh5.28547$227.539978@nnrp1.uunet.ca... >> Hi Bernardino.... >> >> Can you give a reference pointer for the statement: >> >> >One of the four inputs of the LUTs in the FLEX family is faster than the >> >three others. >> >> I have not come across this little gem before........ >> >> Eric Pearson >> >> >> >> Bernardino León wrote in message ... >> >Suppose we have a function like Y = A AND B AND C AND D, that fits in a >> >LUT... And suppossing that there isn't any timing constrain in any of >the >> >inputs >> >Is there any way to know - BEFORE compiling - which one of the four >inputs >> >will be assigned the fastest of the four inputs? >> > >> >Thanks >> >Bernardino Leon >> >bleon@lander.es >> > >> > >> > >> >> > >Article: 24257
I believe that plx offers the plx 9656 PCI chip, which is 64 bit and 66 Mhz. Maybe the are not in production yet, i don't know. Richard Austin Franklin wrote: > I have a design that currently uses a PLX 9080, and I need to move it to a > 64 bit and/or 66MHz PCI interface... PLX does not currently offer a > solution, that I can find...neither does AMCC. Any suggestions for off the > shelf chips to do this, or any experience with the QuickLogic QL5064 > interface chip? > > Thanks! -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 24258
Hi everybody! I'm looking for a development board for the Virtex-EM chips (Package BG404). Somebody knows a company producing such boards? Thanks in advance! LarsArticle: 24259
Hi Eric: You're right : those times include routing delays. That is the reason by which I have selected a placement that forces to a "supposed" equal routing delay. 1) In the example, all registered outputs have the "supposed" same routing delay because all of them are 1 LAB away from the common destiny, and in the same row. 2) The four paths have the same load (1). But delays are different. And this result is completely independent of the distance from sources to load (supposed the four Q`s are the same distance away from destination in terms of rows) and independent of the function : AND, OR... I can not give more timing details becuse the software has not the possibility to split timings in a more detailed manner, like combinatorial, routing... (I wish). You can not separate local routing delay from LUT delay. An extra possibility: the four delays of the LUT are equals and the local interconnect delays are different depending on the input coming to the LUT. As the only information I have is the data book, I can only have an external view of the logic element. In any case, the FLEX 8000 logic element from the data book shows that data 3 does not keep the same path... Then, my question would be which of the LUT inputs is mapped to DATA3? I do not have more information than these suppositions. That`s why I make questions. Bernardino Leon bleon@lander.es Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de noticias 9uEh5.154$Z2.3248@nnrp1.uunet.ca... > Hi Bernardino.... > > The times you are mentioning include the routing delays, and > of coarse each path must take a different route..... > > Can you find (and share) some documentation > to substantiate your hypothesis? > > Eric > > > Bernardino León wrote in message ... > >Hi Eric: > > > >Next is very easy to try in the graphic editor ( I tested it in flex8K, but > >I think the result is the same for 10K): Try the previous function and > >assign the AND4 in the LCELL LC2A2 -for example-; register the four inputs > >and assign the four registers in the LAB A1. Make a timing analysis and > look > >the results in the delay matrix: one of the delays from the *.Q registered > >outputs is faster... How to know wich will be the "selected" input of the > >AND4 is my question... > > > >Thanks. > > > >Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de > >noticias U7jh5.28547$227.539978@nnrp1.uunet.ca... > >> Hi Bernardino.... > >> > >> Can you give a reference pointer for the statement: > >> > >> >One of the four inputs of the LUTs in the FLEX family is faster than the > >> >three others. > >> > >> I have not come across this little gem before........ > >> > >> Eric Pearson > >> > >> > >> > >> Bernardino León wrote in message ... > >> >Suppose we have a function like Y = A AND B AND C AND D, that fits in a > >> >LUT... And suppossing that there isn't any timing constrain in any of > >the > >> >inputs > >> >Is there any way to know - BEFORE compiling - which one of the four > >inputs > >> >will be assigned the fastest of the four inputs? > >> > > >> >Thanks > >> >Bernardino Leon > >> >bleon@lander.es > >> > > >> > > >> > > >> > >> > > > > > >Article: 24260
In a pinch you should be able to use an XCV50 in the same package unless you are using the power down mode (replaces the temperature sense diode). I think even the bitstreams are the same, although the xilinx jtag tool may tell you different. Nicolas Matringe wrote: > Hi all > We are trying to get an XC2S50-5PQ208 but can't find any. Avnet seems to > sell them quicker than they can buy them from Xilinx... We plan to buy > quantities but need some parts for prototyping extremely quickly (and > there's no Virtex with a PQ208 package). I contacted a friend of mine at > Xilinx France, too... Still waiting. > Can any of you sell us 1 or 2 chips (any size, as long as it's an XC2S > with a PQ208 package)? We can give our FedEx account # for shipping (+ > small gift) > > Thanks in advance > -- > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE > Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24261
You'll get a more accurate accounting if you drive your test circuit from flip-flops within the *SAME* LAB. The row routing matrix is a sparse matrix so if you are manually placing the driving flip-flops you may be getting one of them in a situation where there is no direct route to the target LUT, so the connection winds up going through an intermediate switch. That said, I wouldn't be surprised if there was a small difference on one of the inputs; The 4 LUT is separable into a pair of 3 LUTs for the arithmetic and counter modes. This could mean that the 4th input controls a mux to select between the two 3 LUTs. If anything, I'd expect that input to be slightly faster than the others. My guess is you won't see the magnitude of difference that you are apparently seeing though. My money is with the first observation. "Bernardino León" wrote: > Hi Eric: > > You're right : those times include routing delays. That is the reason by > which I have > selected a placement that forces to a "supposed" equal routing delay. > 1) In the example, all registered outputs have the "supposed" same routing > delay > because all of them are 1 LAB away from the common destiny, and in the same > row. > 2) The four paths have the same load (1). > But delays are different. And this result is completely independent of the > distance > from sources to load (supposed the four Q`s are the same distance away from > destination > in terms of rows) and independent of the function : AND, OR... > I can not give more timing details becuse the software has not the > possibility to split > timings in a more detailed manner, like combinatorial, routing... (I wish). > You can not > separate local routing delay from LUT delay. > > An extra possibility: the four delays of the LUT are equals and the local > interconnect > delays are different depending on the input coming to the LUT. > > As the only information I have is the data book, I can only have an external > view of > the logic element. In any case, the FLEX 8000 logic element from the data > book shows > that data 3 does not keep the same path... Then, my question would be which > of the > LUT inputs is mapped to DATA3? > I do not have more information than these suppositions. That`s why I make > questions. > > Bernardino Leon > bleon@lander.es > > Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de > noticias 9uEh5.154$Z2.3248@nnrp1.uunet.ca... > > Hi Bernardino.... > > > > The times you are mentioning include the routing delays, and > > of coarse each path must take a different route..... > > > > Can you find (and share) some documentation > > to substantiate your hypothesis? > > > > Eric > > > > > > Bernardino León wrote in message ... > > >Hi Eric: > > > > > >Next is very easy to try in the graphic editor ( I tested it in flex8K, > but > > >I think the result is the same for 10K): Try the previous function and > > >assign the AND4 in the LCELL LC2A2 -for example-; register the four > inputs > > >and assign the four registers in the LAB A1. Make a timing analysis and > > look > > >the results in the delay matrix: one of the delays from the *.Q > registered > > >outputs is faster... How to know wich will be the "selected" input of the > > >AND4 is my question... > > > > > >Thanks. > > > > > >Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de > > >noticias U7jh5.28547$227.539978@nnrp1.uunet.ca... > > >> Hi Bernardino.... > > >> > > >> Can you give a reference pointer for the statement: > > >> > > >> >One of the four inputs of the LUTs in the FLEX family is faster than > the > > >> >three others. > > >> > > >> I have not come across this little gem before........ > > >> > > >> Eric Pearson > > >> > > >> > > >> > > >> Bernardino León wrote in message ... > > >> >Suppose we have a function like Y = A AND B AND C AND D, that fits in > a > > >> >LUT... And suppossing that there isn't any timing constrain in any of > > >the > > >> >inputs > > >> >Is there any way to know - BEFORE compiling - which one of the four > > >inputs > > >> >will be assigned the fastest of the four inputs? > > >> > > > >> >Thanks > > >> >Bernardino Leon > > >> >bleon@lander.es > > >> > > > >> > > > >> > > > >> > > >> > > > > > > > > > >Article: 24262
Samples end of year... Too late... Richard Meester <rme@quest-innovations.com> wrote in article <398725D4.5ECA333@quest-innovations.com>... > > I believe that plx offers the plx 9656 PCI chip, which is 64 bit and 66 Mhz. > Maybe the are not in production yet, i don't know. > > Richard > > Austin Franklin wrote: > > > I have a design that currently uses a PLX 9080, and I need to move it to a > > 64 bit and/or 66MHz PCI interface... PLX does not currently offer a > > solution, that I can find...neither does AMCC. Any suggestions for off the > > shelf chips to do this, or any experience with the QuickLogic QL5064 > > interface chip? > > > > Thanks!Article: 24263
I have a design that I inherited from a foundation 2.1i sp1 user. Whenever I fix something in one module, something else breaks that was working before. I'm using 2.1i sp5. The local xilinx rep thinks the problem is the result of the way the designer copied design files rather than use the library manager. Has anyone else had a similar problem? What did you do to fix it. -Sue R. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24264
Hi Bernardino.... I played around using your suggestions for a 10K250A and one port always seemed 0.1ns faster in the timing analyser. I usually only use 3 layers of logic max, but someday that 0.3ns will come in handy. Thanks for pointing this gem out. Best of luck in your quest to control this "feature" Eric Pearson Bernardino León wrote in message ... >Hi Eric: > >You're right : those times include routing delays. That is the reason by >which I have >selected a placement that forces to a "supposed" equal routing delay. >1) In the example, all registered outputs have the "supposed" same routing >delay >because all of them are 1 LAB away from the common destiny, and in the same >row. >2) The four paths have the same load (1). >But delays are different. And this result is completely independent of the >distance >from sources to load (supposed the four Q`s are the same distance away from >destination >in terms of rows) and independent of the function : AND, OR... >I can not give more timing details becuse the software has not the >possibility to split >timings in a more detailed manner, like combinatorial, routing... (I wish). >You can not >separate local routing delay from LUT delay. > >An extra possibility: the four delays of the LUT are equals and the local >interconnect >delays are different depending on the input coming to the LUT. > >As the only information I have is the data book, I can only have an external >view of >the logic element. In any case, the FLEX 8000 logic element from the data >book shows >that data 3 does not keep the same path... Then, my question would be which >of the >LUT inputs is mapped to DATA3? >I do not have more information than these suppositions. That`s why I make >questions. > >Bernardino Leon >bleon@lander.es > > >Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de >noticias 9uEh5.154$Z2.3248@nnrp1.uunet.ca... >> Hi Bernardino.... >> >> The times you are mentioning include the routing delays, and >> of coarse each path must take a different route..... >> >> Can you find (and share) some documentation >> to substantiate your hypothesis? >> >> Eric >> >> >> Bernardino León wrote in message ... >> >Hi Eric: >> > >> >Next is very easy to try in the graphic editor ( I tested it in flex8K, >but >> >I think the result is the same for 10K): Try the previous function and >> >assign the AND4 in the LCELL LC2A2 -for example-; register the four >inputs >> >and assign the four registers in the LAB A1. Make a timing analysis and >> look >> >the results in the delay matrix: one of the delays from the *.Q >registered >> >outputs is faster... How to know wich will be the "selected" input of the >> >AND4 is my question... >> > >> >Thanks. >> > >> >Eric Pearson <ecp@focus-systems.nospam.on.ca> escribió en el mensaje de >> >noticias U7jh5.28547$227.539978@nnrp1.uunet.ca... >> >> Hi Bernardino.... >> >> >> >> Can you give a reference pointer for the statement: >> >> >> >> >One of the four inputs of the LUTs in the FLEX family is faster than >the >> >> >three others. >> >> >> >> I have not come across this little gem before........ >> >> >> >> Eric Pearson >> >> >> >> >> >> >> >> Bernardino León wrote in message ... >> >> >Suppose we have a function like Y = A AND B AND C AND D, that fits in >a >> >> >LUT... And suppossing that there isn't any timing constrain in any of >> >the >> >> >inputs >> >> >Is there any way to know - BEFORE compiling - which one of the four >> >inputs >> >> >will be assigned the fastest of the four inputs? >> >> > >> >> >Thanks >> >> >Bernardino Leon >> >> >bleon@lander.es >> >> > >> >> > >> >> > >> >> >> >> >> > >> > >> >> > >Article: 24265
Sounds like a barrel shifter. For that you will choose a window of register bits that you would move up/down by as much as you need in a single clock cycle. Another solution would be to simply use multiplication/division. The above would perform the shifting you need, but it could be time consuming (depending on you target architecture and clock rate). Yury Jamil Khatib wrote: > Hi, > > How can I do a shifter shifts the register contents by an amount that is > resulted from another operation. > > For example > > Shift right (A, by b+c) > shift contents of register 'A' b+c bits to the right in a single clock. > > Regards > Jamil KhatibArticle: 24266
The output is combinatorial when you read from the RAM. The output is synchronous when you write to the RAM. Yury erika_uk@my-deja.com wrote: > Hi, > > should we consider the output of XC4000 SELECT-RAM as combinatorial or > no... > > thanks in advance > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 24267
It all depends on the target architecture and device utilization (Xilinx I presume). Xilinx XC4000/Spartans use TBUFs for logic and for routing purposes. So when your device utilization is rather high using TBUFs for MUXes may diminish the routability of the device. On the other hand if LUTs are plentiful, then you can use them to implement MUXes. Again, it is a trade-off, if the MUX is large then, the combinatorial delays through the logic may be unacceptable, and therefore TBUFs could be used instead. Yury erika_uk@my-deja.com wrote: > hey, > > what are the advantages and disadvantages from using TBUFs( e.g : for > multiplixer purpose ) > > anticipated thanks > > --Erika > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 24268
Anyone intimately familiar with ATA-5/ATA-4?
Disk deasserts DMARQ line after each sector during uDMA66 uDMA transfer
of many sectors. If the bus is renegotiated each time then the transfer
completes fine. No errors of any kind reported by the disk.
Thanks,
Yury
Article: 24269Rick Collins wrote: > > I remember from years ago that Viewlogic has a licensing "quirk" (I used > much stronger language at the time). They had and still seem to have two > types of licenses. You can get a target specific license which will only > let the tools work with the libraries for a specific chip vendor's > devices. Or if you paid a much higher price you can get a full "board" > package that will work with any library including board design libs. Right > The problem was if you paid the big bucks for the board package you > could not share any files with a customer who was using a vendor > specific version. This was not limited to files that were done for other > vendor's chips, but even for the libraries that their license was > authorize for. Right > I investigated extensively and understand just how the licensing works. > I even found a way around the problem by cutting and pasting one line > from the schematic files. But this was a real pain and had to be done > each and every time the file was saved. Not right. If you created the sheet in the restricted version, then edited it with the unrestricted version, it retained the restricted version K line. So the problem is new sheets that are added to the design while using the unrestricted version. > The question is, has Viewlogic found a way to deal with this problem? I > am thinking about buying a full license for board level design. But > there is not much point if I can't share schematics with customers who > only have the chip level package. I have discussed this several times with various people at Viewlogic, without effect. Greg Neff wrote: >The obvious response here is: What does Innoveda (Viewlogic) have to >say about this? I owuld not expect any change. It's the same people. >In any case, I use ViewDraw and ViewSim (latest versions) for FPGA >entry and simulation, and I know that the file formats have not changed >in many years. Since ViewDraw is also used for board schematic >capture, I suspect that nothing has changed. The file format is delightfully ASCII, and is reasonably easy to figure out, even though it is proprietory/un-documented. Unfortunately, I have heard that there is some consideration of changing over to a binary format. I hope that if they do that, they will continue to support the ASCII format, since I have a huge investment in existing designs. I dont think this will happen any time soon, but it does discourage creating tools that directly manipulate the ASCII files.The first generation of my FLIBGEN module generator did this, automatically creating beautiful schematics. The current one uses C++. >Maybe you could write a BASIC program to post-process the schematic >files and replace the line in question. Which would work only if you knew how to generate the security number on the K line. I have no idea how to calculate it. > ... Orcad vs Viewdraw comparison ... >I would be interested to hear what other people think of ViewDraw >versus other board-level schematic capture tools. When clients ask me, I tell them that Orcad has an easier learning curve than Viewdraw, but once you get into complex designs, and particularly with ViewSim simulation backannotation to ViewDraw, the Orcad stuff is just a toy in comparison. For heavy-weight high performance designs, Viewlogic/Innoveda has linkage between Viewdraw and their ePlanner and XTK signal integrity/board layout/crosstalk analysis software, which is second to none. Rick Collins wrote: >Maybe I am just a contrarian, but I saw the licensing working the other >way. I would *only* buy the FPGA workstations since I needed to be able >to support the FPGA stations. Using a board station would make the >design incompatible with the rest of the world of FPGA stations. Well, first of all, Xilinx stopped reselling the restricted version about 2 years ago, and I believe only Lucent now sells a restricted version. Second, the restricted version only works with the designated FPGA vendor's libraries, so you cant use the generic PCB libraries. If you had infinite time, you could create your own, but you would still have the problem that there is no export netlister from the restricted version to PCB packages. >I am not doing ASIC designs, and I am trying to determine if it is best >for me to use Viewlogic for board designs or to continue using Orcad or >even to switch to someother package such as Aldec (am I nuts?!) If you use Aldec, if you are not nuts yet, you will be. >You may be right. I have sent an email off to Innoveda asking about >this. I agree that they should fix it. But every conversation that I >have had with Viewlogic support or sales was along the lines of "we are >just trying to protect our revenue". They just don't seem to get it that >this hurts them. Or maybe not. I agree, maybe not. >If it makes the customers buy extra seats >or buy upgraded seats then it is a plus for Innoveda. But this will >completely keep me away as there is no fix for me other than supplying >my customers with full viewlogic seats. So what I do is tell my clients up front that if I am doing stuff for them, and they want to own it and be able to change it, here is the list of CAE software they will need to buy. Ray wrote: >If you are working in schematics, Orcad and Aldec are going to feel vrey toy-like once >you use VL. On the otherhand, viewlogic's VHDL tools are second rate at best when >compared to the superb VHDL/verilog tool suite offered by Aldec. As always, Ray and I are in total agreement. Austin wrote: >I am sorry to sound so cynical if you are really serious, but I just can't >believe anyone would...COULD make that statement with a straight face, or >at least without a lot of inebriation... OrCAD is undoubtedly the WORST >schematic 'scribbling' program I have ever used. And the worst part is, >they charge a LOT for it! If it was $99, I'd take it seriously. I'd >rather use stone and chisel... > ... more of the same ... >I personally find ViewDraw to be one of the best, if not the best schematic >drawing program out there...and I've used quite a few... What were your >complaints with ViewDraw? And I agree with Austin too :-) >Sorry, I know this isn't the OrCAD bashing group... But we could start :-) Rick Collins wrote: >I am unclear on how you feel about Orcad, Austin. Do you like it or not? >Stop beating around the bush and tell us! ;) I get the same complaint. Viewlogic (and expect Innoveda) have had rather attractive upgrade plans to convert restricted Viewdraw to unrestricted. I now mostly have unrestricted licences. Compared to the time spent screwing around with different versions (and considering what I charge per hour), it just wasn't worth the effort. -- Philip Freidin Mindspring that acquired Earthlink that acquired Netcom has decided to kill off all Shell accounts, including mine. My new primary email address is philip@fliptronics.com I'm sure the inconvenience to you will be less than it is for me.Article: 24270
Ray Andraka a écrit : > > In a pinch you should be able to use an XCV50 in the same package > unless you are using the power down mode (replaces the temperature > sense diode). I think even the bitstreams are the same, although the > xilinx jtag tool may tell you different. What about the BlockRAMs ? I need four of them and I know there won't be enough space in an XCV50 for the logic AND the 16kbits of RAM. -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24271
>Ray Andraka a écrit : >> >> In a pinch you should be able to use an XCV50 in the same package >> unless you are using the power down mode (replaces the temperature >> sense diode). I think even the bitstreams are the same, although the >> xilinx jtag tool may tell you different. > >What about the BlockRAMs ? I need four of them and I know there won't be >enough space in an XCV50 for the logic AND the 16kbits of RAM. > Nicolas: The XCV50 is a virtex part and has the same blockRAM ( and everything elser ) as the XC2S50. I think you're thinking of a XCS50, which is a spartan, which does not have the BlockRAMs. Ray: According to my data book, the XCV50 (Virtex) is not available in the PQ208 package, which is the reason that Nicolas has a problem in the first place. (I think!) I take it that you're past the state of choosing a different package? -KentArticle: 24272
Hi, Could you please suggest me the best FPGA to use that has minimum price, maximum logic gates and provides maximum FIFO memory buffer. Thanks in advance Jamil KhatibArticle: 24273
Galileo Technology has standard 64-bit 66MHz PCI Interface chips (eg. GT64121). See www.galileot.com Mark Austin Franklin wrote: > > I have a design that currently uses a PLX 9080, and I need to move it to a > 64 bit and/or 66MHz PCI interface... PLX does not currently offer a > solution, that I can find...neither does AMCC. Any suggestions for off the > shelf chips to do this, or any experience with the QuickLogic QL5064 > interface chip? > > Thanks!Article: 24274
Hi,
one of disadvantages : if you are planning to port your design to ASIC
some day, or maybe to another FPGA family without tbufs, you'll probably
need to rewrite your code again. so, using plain old muxes implemented in
luts enhance portability. it's not impossible to implement three state in
ASIC,
but not easy.
also it's easier to test your design without three state buffers.
if you're sure your design will be used only in fpga, and if you need to
squeeze
it as much as possible, tbufs are marvelous.
regards,
--
-------------------------------------------
- Domagoj -
- Domagoj@engineer.com -
-------------------------------------------
rickman <spamgoeshere4@yahoo.com> wrote in message
news:39866193.C565C403@yahoo.com...
> For low fan in multiplexors they are slow and consume a lot of long
> lines (one per bit). But for high fan in muxes, they are pretty good.
> You need to decode the select lines. But this can make it easier to
> utilize unique select setups such as a 1 of N select.
>
> I have used TBUF muxes when I needed to make an unusual mux which
> allowed me to pack a variable sized data word into 32 bit data words.
> The size was preselected, but ranged from 1 to 8 bits. I used a 5 bit
> counter and a decoder to give me the 1 of 8 select to enable the
> different tristate enables. This was pipelined to give speed so that the
> 8 enables changed on every clock edge. The slow path then was the enable
> register output through the tristate buffer onto the long line and to
> the data register D input. It ran at the needed 50 MHz in an XC4013XL.
>
> The real beauty is that it used *no* CLBs for the actual mux and only 4
> CLBs for the decodes. Not bad for an 8 to 32 mux array.
>
> It worked so well that I used another, similar TBUF array for the inputs
> to the register which controlled the CE on the data register. This one
> was a little more complicated to figure out, but the decode was purely
> static.
>
>
> erika_uk@my-deja.com wrote:
> >
> > hey,
> >
> > what are the advantages and disadvantages from using TBUFs( e.g : for
> > multiplixer purpose )
> >
> > anticipated thanks
> >
> > --Erika
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
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