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"Nial Stewart" <nials@sqf.hp.com> wrote in message news:3A8AC423.DBABD12@sqf.hp.com... > I came to the conclusion that if graphical entry was the way > forward the software industry would have adopted it years ago. A similar statement is often made by software programmers adept at C (with no EE background): "I think I am going to start writing VHDL" The amusement in this statement, is that many assume because VHDL is a C-like language, the same rules apply. Quite simply, hardware and software are extremely different beasts. And as a result, reasonable design flows for each differ. Software is generally designed with a very serial flow, particularly because it is going to be compiled to run on an architecture that is serial in nature. The Microprocessor generally handles one instruction flow, and only one instruction at a time. So all logic designed is not run all the time, but rather, it is executed in some serial fashion. Many design flows have been tried and have not achieved commercial acceptance due to the fact that efficiency comes from the designer thinking like the architecture that the design is being implemented in. Hardware is parallel. Many a computer science student has been extremely confused by the "ALWAYS" nature of Verilog and/or VHDL, after having spent years studying sequential languages such as C, Basic and Fortran. The problem with language design as a source of documentation, is that it is difficult to quickly read and digest a large state machine, or block diagram, when it is represented in a fashion that must be digested by the reader (or the designer, many months later) in a serial fashion. The problem with graphical design is that the VHDL guru will write perfect code every time, and the graphical tool will not. We, the designers using VHDL, one would at least hope, understand how our VHDL is synthesized into the physical elements that exist in the ASIC or FPGA architecture that we are targeting. These graphical tools DO NOT remove the need to understand VHDL. The issue with the graphical tools, is that the user needs to understand VHDL (or Verilog) better than to write simple code, to effectively use the tools. Just as we need to understand what "good" VHDL looks like, we need to understand what "good" graphical designs look like, so that we can understand what sort of code the tool will produce, from differing styles of implementation. Most of us use VHDL/Verilog for one simple reason, it is a nearly universal format for data exchange whether the purpose is simulation, synthesis, or simply design reuse. These are languages very efficient for the tools. They are not languages as efficient for the human understanding. The graphical tools make this easier. Many of the people who believe that 100% language implementation is the only way to go, are comparing quick and dirty graphical designs to well planned language designs. For the record, I still write 25% of my modules in VHDL without using the tools, as some of these modules are only efficiently written this way. All of the hand-coded modules are leaf-nodes in a hierarchical design. But for those modules that I think about in terms of Block Diagrams (aka Schematics), Truth Tables or State-Machines, I get code just as good out of the graphical tools, as I would if I wrote it by hand. In the case where the graphical stuff needs comments, extra attributes, or other tweaks, I can embed this in the graphical files. The reason many of these graphical tools, such as DesignBook or Renoir, have not gained acceptance is their initial cost, most in the $10K range. No body ever seems to look at this stuff in terms of the burdened labor rate for the engineers doing the design work, and supporting the designs. I find that I get only a 10% gain in initial design implementation using a tool such as Renoir. But I find that in the debug/extension/upgrade/maintenance of a design that my gains are in the 50% range, given the speed with which I can quickly become reacquainted with the details, and see the design more qu ickly in the parallel fashion that it truly exists. I also find that the design files are almost self documenting, so I find that very little supporting documentation is required. Translation of the previous sentence: Documentation is almost free. Given the fact that many engineers just don't get around to documenting designs, this is significant. It is merely an added benefit to me that I can do a design in a graphical tool, and if I tag all of the nets, and comment the pictures, I get perfect VHDL code that I can give my customers, who may not want to buy the tools. As a consultant, the costs of changing gears, and answering questions about old designs is huge, both for me and my clients. The cost is even bigger when a new engineer needs to understand or make changes to an old design. These tools help reduce this cost. Regards, Erik Widding. -- Birger Engineering, Inc. -------------------------------- 781.481.9233 38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.comArticle: 29376
Try this in your top level:
// Xilinx GSR/GTS stuff
reg GTS, GSR;
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
initial begin
GSR = 1; GTS = 1;
#100 GSR = 0; GTS = 0; // or whatever
end
"Craig McAdam" <craig@mysterio.freeserve.co.uk> wrote in message
news:3A8C584C.D8065A97@mysterio.freeserve.co.uk...
> I'm trying to use the Xilinx global GSR signal in a SpartanII design
> (according to Xilinx' own guidelines).
>
> But I cannot get the values assigned to the global GSR signal to take
> effect in other Verilog modules. As an example if I have a simple
module
> (check.v) and testbench (test.v) to try to observe the behaviour -
>
Article: 29377Kostas Marinis wrote: > Greetings all, > > my question relates to the difficulty/complexity of designing and > implementing a 64-bit/66MHz PCI master/target controller core in VHDL. > Could anybody give me an estimate on the amount of time/work such a task > would require to complete? I understand that this is a *very* general > question, and that it basically depends on the experience/ingeniuty/IQ > of the designer, the tools used, the target technology (try implementing > that in a MAX5000! :) and lots of other factors. A rough estimate would > suffice though (something in the form "assuming x years of > VHDL/FPGA/digital design experience, about y to z man-months"). > > There is basically no restriction on the target technology - assume the > fastest/largest device is available (a Virtex-II or Apex maybe?) > You can also assume that access to virtually all FPGA/VHDL tools > currently in the market is available. > Make any other reasonable assumptions you wish, but please state them > appropriately. > I would greatly appreciate it if you avoided answers like "just buy a > ready made core and forget about the whole thing"! ;-) > > Thanks in advance, > > Kostas I had to do this for 32/33 PCI starting from a near standing start. Doing the basic logic isn't all that hard - the PCI is fairly straightforward. That was about 4 weeks all told for both master & slave. Then there's going through the 2.1 spec page by page to make sure that all the edges of the flight envelope are covered - 2 weeks in my case. What helps here is to get *someone else* to write a PCI bus monitor that sits inside your simulation testbench. That's the easy part. Now the fun starts in getting the timing right. Particularly the setup time. In my case 7nsec in a -4 Virtex (not E!) in yours 3nsec in say a -8. To see how hard it is note that Xilinx's PCI-66 core data sheet shows 2 classes of setup times. One set is at the legal 3nsec but the other is 5. From my experience the 2 classes are (1) Things for which you can use registered copies - basically the data/cmd busses. (2) Those that come raw off the PCI bus straight into the control state machines. The one bad aspect of PCI is that its hard to pipeline the control signals. And this even though Xilinx have access to some magic functions like special IRDY/TRDY pins and the ability to put delays on global clock buffers. Very careful coding and a really good understanding of the synthesis and layout tools are essential to get this right rather than huge knowlege of HDL. My case was a bit special since, because this was an ASIC prototype, I couldn't use hard macros or hand placement to get the speed & had to resort to serious low cunning & get pretty devious to get the synth tool to generate something that the layout tool would place & route gracefully [No Virtex floorplanner at the time - I would have happily sacrificed many relatives for that tool] If you have no experience of HDL/synthesis/layout then I can say that this last step is going to take a lot of time - even with the floorplanner.Article: 29378
Arcane question, but... Has anyone had trouble with Altera's 10K50V devices following the process change from E50 to F51 over the course of last year? We have 10-for-10 bad pcbs that have F51s, that work with E50s. They went from 3 to 4-layer metal, same fabs/geometry. Thanks! Joe Curren Printrex, Inc.Article: 29379
Erik Wahlstrom wrote: > We are looking for ways to decrease the place, route and synthesis time > required for the Vertex II 1000 and above. > > Does anyone have any experience comparing, > > Pentium II vs. Pentium III at the same frequency? I just went from a PII-450 to a PIII-600 in what was otherwise the same box & saw very little improvement in P&R time. Down from 58 min for a 75% used XCV400 to 51-52. > What about Cache size. Is there a signifigent speedup going to the 2MB > cache. > When we first built our NT systems we hadn't heard about the bug where, by default, the L2 cache size is set to 0. I thought ``oh goody'' & turned it on - only 512K. Found ~squat improvement. > What about interleaving main memory. > > What about RAMBUS main memory? I know RAMBUS get it's speed up from > pipelining. Basically this is the right area to look at since PAR is fundamentally memory access bounded. I'd forget RAMBUS & go for the AMD system with the fastest DDR you can afford. This applies to the synth & simulation tools as well. ** An important note ** If you are running Win-NT you must have enough memory that it never starts to page. Once it does its performance drops like a brick through a greenhouse roof - for any reasonable size design NT paging => you might as well take that week off you've been planning. I would suggest an absolute min of 384M and preferrably 512. For the big devices then make sure your motherboard supports 1GB.Article: 29380
Depends on the device family. All Virtex devices give you a DLL-based clock-frequency doubler, Virtex-II even does the whole job for you ( multiply by 2, devide by 13 ) inside the "Digital Clock Manager" module, of which each chip has up to 12. Peter Alfke, Xilinx Applications ==================================== mark wrote: > Hi , > > Being new to vhdl I have only ever designed integer counters, so could > someone tell me how you would design a synthesizable divide by 6.5 counter. > > Thanks > > MarkArticle: 29381
Hi, Radhika, If you haven't already solved your problem, I have some "pointers". You didn't mention what family of FPGA you're using; I'm going to assume Spartan (They have LDC & HDC pins.) radhika <radhikamurahari@yahoo.co.uk> writes: >INIT(active low) signal which should be actually >igh during configuration is low . INIT is open collector, so make sure that you have a pull-up resister. Otherwise INIT will never go high. > 3. XPGM is used to configure the PROM and prior > to the configuration we need to make the RESET > pin of the PROM active low ... Yup. Active low reset. I spent a good couple of hours figuring that one out once. > 6.connections for the FPGA pins > connected DATA(of SPROM) to DIN; > CCLK to CLK (of SPROM) > INIT to OE/RESET; You need a pull-up. (4.7k to Vcc) > A short low pulse on PROG pin; > DONE connected to Vcc using 4.7k; This is an FPGA Output pin. YOu do not need a Pull-up. I suggest sonnecting this to the SPROM CE as shown in the FPGA Data sheet's configuration section. > LDC to CE(of SPROM); this pin becomes User I/O as soon as configuration is finished. If your FPGA design doesn't make this output pin HIGH, then it's not going to go high. In you second posting: > in our configuration we found that INIT signal > is initially going low during configuration and This is normal, and a Good Thing. >when it is switching to high both the LDC and >the DONE pins are going high indicating configuration >of FPGA.But we find that the output is erroneous. If the INIT is switchiing HIGH, then I will assume that you do have apull-up on it. If INIT is driven low by the FPGA before DONE goes high, that means there was a configuration bitsream error. If DONE goes high at all, then that means that your configuration was sucessful, and that the FPGAs read the bitstream program without a CRC error. When this happens, INIT becomes a USer I/O, just like LDC and HDC, and all three pins do whatever your FPGA design tells them to do. If the output is erroneous, then probably there's a problem with your design. To check that youre design is really working, try taking an input pin such as a clock, and routing it to an output pin. Then, see if that output pin wiggles. Hope this helps, -KentArticle: 29382
Brian Borts <brian@alphajob.com> writes: > Location: Kanata, Ontario, Canada > Description: Alpha Job Consulting Inc.’s client is a fabulous provider <snip> Umm, When your client wrote "is a fabless provider" ..., and you thought it was a spelling mistake and fixed it? it wasn't. -kArticle: 29383
"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3A8DB618.26E03212@algor.co.uk... > ** An important note ** If you are running Win-NT you must have enough > memory that it never starts to page. Once it does its performance > drops like a brick through a greenhouse roof - for any reasonable > size design NT paging you might as well take that week off you've > been planning. I would suggest an absolute min of 384M and > preferrably 512. For the big devices then make sure your motherboard > supports 1GB. Is this also true for a reasonably floor-planned design? In other words, if the P&R tools have a simpler problem to solve, do they need less memory? Or is the memory requirement largely determined by the size of the target device? And does anyone know the memory footprint of P&R for the largest Virtex and Virtex-II devices? Another data point: a very full XCV300, approx 50% floorplanned, routed just fine in 256MB with no visible paging.Article: 29384
Kent Orthner wrote: > Hi, Radhika, > > If you haven't already solved your problem, I have some "pointers". > > You didn't mention what family of FPGA you're using; I'm going to > assume Spartan (They have LDC & HDC pins.) > > radhika <radhikamurahari@yahoo.co.uk> writes: > >INIT(active low) signal which should be actually > >igh during configuration is low . > > INIT is open collector, so make sure that you > have a pull-up resister. Otherwise INIT will > never go high. > > > 3. XPGM is used to configure the PROM and prior > > to the configuration we need to make the RESET > > pin of the PROM active low ... > > Yup. Active low reset. I spent a good couple of > hours figuring that one out once. > > > 6.connections for the FPGA pins > > connected DATA(of SPROM) to DIN; > > CCLK to CLK (of SPROM) > > INIT to OE/RESET; > > You need a pull-up. (4.7k to Vcc) > > > A short low pulse on PROG pin; > > DONE connected to Vcc using 4.7k; > > This is an FPGA Output pin. YOu do not > need a Pull-up. > I suggest sonnecting this to the SPROM CE as > shown in the FPGA Data sheet's configuration > section. > > > LDC to CE(of SPROM); > > this pin becomes User I/O as soon as configuration > is finished. If your FPGA design doesn't make this > output pin HIGH, then it's not going to go high. > > In you second posting: > > in our configuration we found that INIT signal > > is initially going low during configuration and > > This is normal, and a Good Thing. > > >when it is switching to high both the LDC and > >the DONE pins are going high indicating configuration > >of FPGA.But we find that the output is erroneous. > > If the INIT is switchiing HIGH, then I will assume that > you do have apull-up on it. > > If INIT is driven low by the FPGA before DONE goes high, > that means there was a configuration bitsream error. > > If DONE goes high at all, then that means that your > configuration was sucessful, and that the FPGAs read > the bitstream program without a CRC error. When this > happens, INIT becomes a USer I/O, just like LDC and HDC, > and all three pins do whatever your FPGA design tells > them to do. > > If the output is erroneous, then probably there's a > problem with your design. To check that youre design > is really working, try taking an input pin such as a > clock, and routing it to an output pin. Then, > see if that output pin wiggles. > > Hope this helps, > -Kent I am not quite sure what your system is but I have one thing that you might try. I use a spartanXL chip. To make it work you need to move done out to clock 4. (I think that was in the configuration options window.) I don't have Xilinx at home right now so I can't tell you for sure. If you can't make it work, but you have access to pads power logic, I can send you my circuit. If not, I can send a description of the connection of the pins. Let me know if that is necessary.Article: 29385
Simon Bacon wrote: > "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message > news:3A8DB618.26E03212@algor.co.uk... > > > ** An important note ** If you are running Win-NT you must have enough > > memory that it never starts to page. Once it does its performance > > drops like a brick through a greenhouse roof - for any reasonable > > size design NT paging you might as well take that week off you've > > been planning. I would suggest an absolute min of 384M and > > preferrably 512. For the big devices then make sure your motherboard > > supports 1GB. > > Is this also true for a reasonably floor-planned design? In other > words, if the P&R tools have a simpler problem to solve, do they > need less memory? Or is the memory requirement largely determined > by the size of the target device? > Interesting question. > > And does anyone know the memory footprint of P&R for the largest Virtex > and Virtex-II devices? > > Another data point: a very full XCV300, approx 50% floorplanned, routed > just fine in 256MB with no visible paging. BTW I wasn't saying I need all the 384M. The current design uses ~150M. Its just that I like to get on with other things while PAR is grinding along in the background. For example I'll typically start the post-synth simulation & PAR at the same time and ModelSim is burning another 80-100M. If you add in the 60-70M allocated to NT + its buffers I can get over 300M useage in a couple of mouse clicks. I then start playing around with NGDBUILD to check out some new constraints for the next iteration & NT goes into free-fall.Article: 29386
hi kent glad to receive your mail.I have still not configured my FPGA and I am giving some details regarding the same , 1.we have used XC 4005XL series and the SPROM used is XC 17256l 2.Our reset was initially high and we have made it low using xpgm software.and 3.I have verified the prom by comparing it to the input file and it says that it is successful. 4. I even checked my fpga also.and it is also working. 5.Now i have connected INIT to Vcc through a 4.7k and it goes to OE/RESET(active low).We have given a short 0V pulse on prog pin and We have observed now init is going to high as soon as prog is brought to high which should be the case. 6. But the problem now is that ldc and done are coming to high immediately after the init goes high indicating end of configuration but the o/p is not correct. 7. HDC was remaining high both before and after confn. 8.I have connected my done pin to Vcc through a 4.7K. 9.Since we are trying to configure in Master serial mode we connected M0,M1 and M2 to gnd using 4.7k resistors. I will let u know if we have pads power logic. These are our connections we appreciate any suggestions and how should the cclk be after confn and we have used xilinx bit generator to generate our bit stream. thank you, RadhikaArticle: 29387
hi chris, I tried calling the support hotline and they would not answer my questions probably cos i am a student and they just asked me to send an email to xup@xilinx.com which I did thats about it . I have connected my init signal to Vcc through a 4.7K and now the scenario has changed my init is low and when i apply a 0V pulse at my prog pin and remove the pulse init is going high along with prog pin but ldc adn done are going high at the same moment but i think atleast 3 to 4 clk pulses are required to start confn and how should the cclk be after the end of confn and my hdc is high both during and after configuration. regards radhikaArticle: 29388
Hi there Where on Earth can I order small quantities (ten or even less) of either Altera's or Xilinx' or whatever from? I contacted Altera's Distributor but their minimal order is of US$500, a nonsense for me. Thanks in advance for the kind directions. Yours, Márcio, BrazilArticle: 29389
Hi : The message occured when i use Foundation3.1 : WARNING:NgdBuild:526 - On the RAMB4_S8_S8 symbol "p2/u1/bram4", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. what's meaning? How do i? Thanks a lotArticle: 29390
I'm looking for a Floating Point Unit in VHDL or Verilog. Any ideas anybody?Article: 29391
Emacs VHDL Mode 3.32 beta comes with the following brand new feature:
STRUCTURAL COMPOSITION
- Enables simple structural composition similar to graphical editors:
1. Create a skeleton for a new component
2. Place subcomponents directly from the hierarchy browser
3. Automatically connect subcomponents and create ports
(based on names of actual parameters)
Please feel free to try it out and let me know how it works and how it
could be improved. And whether changing the keybinding `C-c C-c' to
`C-c c' is a crime :-)
http://opensource.ethz.ch/emacs/vhdl-mode.html
Have fun,
Reto
Article: 29392Xilinx now offers for downloading only free suite called WebPACK and it includes fully functioning ModelSim and StateCAD as well as a synthesis tool. All free.Article: 29393
"Joe C." wrote: > Arcane question, but... > Has anyone had trouble with Altera's 10K50V devices following the > process change from E50 to F51 over the course of last year? > We have 10-for-10 bad pcbs that have F51s, that work with E50s. > They went from 3 to 4-layer metal, same fabs/geometry. > Thanks! > Joe Curren > Printrex, Inc. Don't know Altera specifically but I've come across similar situations before. Causes were either: o The new process is faster & so is leading to hold time problems somehwhere. o The metatstability characteristics have changed - got worse. Unlikely if the first possibility is true.Article: 29394
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.parmita.com/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Chip-Guru : http://www.chip-guru.com/ )Article: 29395
We intend to use the VirtexII device for inserting periods each x nanoseconds in a clock with a period of y nanoseconds (for example 3 periods with 8ns each, then 1 or 2 periods of 10ns, then some of 8ns and so on......) so that the phase is shifted dynamically by 2 ns in a certain direction. The shifting should be controlled by an appropriate pulse. In the data sheets I did not find enough information to know if that is possible to realize it with DCM of VirtexII. It would be great if someone could tell me where to get more information about phase shifting applications. Thanks in advance Heinrich FonfaraArticle: 29396
Jon Keeble schrieb: > I'm looking for a Floating Point Unit in VHDL or Verilog. Any ideas anybody? Hi Jon, Don't copy, write your own. As you are interested in emacs ( responding to zimmerman's mail) you can use it to edit your own code. good luck. by michaelArticle: 29397
Hi! I’m using a programming board for serial EEPROM AT17xx from http://members.xoom.com/microele/paralelo/aplicaciones.com It’s algoritm for writing works fine, as seems, but verifying gives: “Bitstream size:11947 Error found:11934” And of course FPGA’s pin D/P don’t go HIGH after power up. Who can help me? Thanks! Best Regards, Yuri ZakharkoArticle: 29398
I found CPLD no internal tri-state buffer to share the same bus. If there are more than 100 registers need to access via external cpu bidirection data port(8051) . How can i avoid the huge100:1 mux output?Article: 29399
Hello" Now,i use the reference design xapp131.zip.it is the source code of fifo.I only utilze the fifostatus_out.But it's scale is 1/16,i want to make it to be 1/32. how i do? thanks
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